ECC counter structures are freed without removing the node from the
stats_list. This can lead to invalid access due to dangling pointers.
Update the ecc counter free logic to set them to NULL upon free, to
remove them from stats_list and free them by validation.
Also updated some of the ecc init paths where error was not propa-
gated to callers and full ecc counters deallocation was not done.
Now, calling unit ecc_free from any context (with counters alloc-
ated or not) is harmless as requisite checks are in place.
bug 3326612
bug 3345977
Change-Id: I05eb6ed226cff9197ad37776912da9dcb7e0716d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2565264
Tested-by: Ashish Mhetre <amhetre@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Add separate flag gpu_dbg_gr to enable common.gr specific debugging.
Add this flag to all the existing debug logs that use gpu_dbg_fn or
gpu_dbg_info for debugging. Also add many other debugging logs that
might be helpful in debugging.
Removing debug log in gv11b_gr_init_get_nonpes_aware_tpc() as it dumps
too much data that does not seem useful.
Batch all interrupt enable functions in gr_init_setup_hw() together for
readability.
Jira NVGPU-5648
Change-Id: I0b857650122cdb1f974b452d28c26e7f142baf61
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2411740
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Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC
errors during acr_construct_execute need to be reported and handled
hence FECS ECC counters are required to be initialized before
acr_construct_execute.
GPC/TPC ECC counters are dependent on the GR config that will be
initialized only after acr_construct_execute.
nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw.
FECS ECC interrupt is enabled by default hence interrupt is not
enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw.
JIRA NVGPU-4439
Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261987
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.
Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.
JIRA NVGPU-4336
Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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FECS_FEATURE_OVERRIDE_ECC bits for SM_L0_CACHE and SM_L1_CHACHE
need to be checked against NV_PGRAPH_PRI_FECS_FEATURE_OVERRIDE_ECC_1
register.
Correct the error of checking those bits against
NV_PGRAPH_PRI_FECS_FEATURE_OVERRIDE_ECC register.
Jira NVGPU-4095
Change-Id: I09737b83496f9e728e0b022bd6a4e75741bd0c49
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210429
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Multiple non-safe functions under NVGPU_DEBUGGER, NVGPU_CILP and other
config flags were moved to fusa files. Although they are guarded by
the C flags, it makes sense to keep those functions in non-fusa
files. Make this change for all hals.
JIRA NVGPU-3853
Change-Id: I8151b55a60cb50c5058af48bab9e8068f929ac3b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204352
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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This patch addresses misra violations due to SDL error reporting
callbacks. In particular, it addresses the following misra violation:
- misra_c_2012_directive_4_7_violation: Calling function
"nvgpu_report_*_err()" which returns error information without testing
the error information.
JIRA NVGPU-4025
Change-Id: Ia10b6b3fd9c127a8c5189c3b6ba316f243cedf04
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196895
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Reduce code complexity of following functions in gr.ecc unit
gp10b_ecc_init(complexity : 17)
gp10b_ecc_detect_enabled_units(complexity : 15)
gv11b_ecc_init(complexity : 23)
gv11b_ecc_detect_enabled_units(complexity : 30)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create four sub functions from gp10b_ecc_init function for
sub units init.
gp10b_ecc_init_lts(complexity : 2)
gp10b_ecc_init_tpc(complexity : 2)
gp10b_ecc_init_tpc_tex(complexity : 8)
gp10b_ecc_init_tpc_sm(complexity : 5)
and reduce gp10b_ecc_init complexity to 3
Create four sub functions from gp10b_ecc_detect_enabled_units function
gp10b_ecc_enable_ltc(with complexity : 4)
gp10b_ecc_enable_tex(with complexity : 4)
gp10b_ecc_enable_smshm(with complexity : 4)
gp10b_ecc_enable_smlrf(with complexity : 4)
and reduce gp10b_ecc_detect_enabled_units complexity to 3
Create four sub functions from gv11b_ecc_init function for
sub units init.
gv11b_ecc_init_tpc(complexity : 10)
gv11b_ecc_init_gpc(complexity : 6)
gv11b_ecc_init_fb(complexity : 6)
gv11b_ecc_init_other_units(complexity : 6)
and reduce gv11b_ecc_init complexity to 5
Create six sub functions from gv11b_ecc_detect_enabled_units function
gv11b_ecc_enable_smlrf(with complexity : 4)
gv11b_ecc_enable_sml1data(with complexity : 4)
gv11b_ecc_enable_sml1tag(with complexity : 4)
gv11b_ecc_enable_smicache(with complexity : 6)
gv11b_ecc_enable_ltc(with complexity : 4)
gv11b_ecc_enable_smcbu(with complexity : 4)
and reduce gv11b_ecc_detect_enabled_units complexity to 3
Jira NVGPU-3662
Change-Id: Id10be4f9a500c300f66756ebae41bfff3b734aea
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159050
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.
Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.
Jira NVGPU-3690
Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
the initialization required for errors that can be injected using hw
support, error injection function. Further, it passes the required
information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
nvgpu_report_ecc_err.
Jira NVGPU-3235
Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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Refactor the ECC code present under gp10b/, gv11b/, and tu104/. To
do this a few things were required:
Firstly, move the ecc related C and H files under the aforementioned
directories over to their new home under hal/gr/ecc/. Also copy over
the ECC HAL code present in gp10b/gp10b.c - not sure why this was
there but it, too, needed to be refactored. Also handle all the
updated header paths and Makefiles to take these movements into
account.
Secondly add a new HAL in GR (gr.ecc) to handle ECC HAL ops. There's
only two: detect and init. init() was copied over from gr and detect
was added so that the common ECC code can call it in a chip agnostic
way. This is required so that the ECC detect can be moved out of the
gp10b init characteristics function.
Lastly update the ECC init flow in the common ecc module to call
detect() right before init().
JIRA NVGPU-3074
Change-Id: Iba1464a904f9a91a45f30902beadf6f912607e40
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090977
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