Fixed following sparse warning by including relevant header:
$TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/therm_gp10b.c:127:6: warning:
symbol 'gp10b_init_therm_ops' was not declared. Should it be static?
Bug 200299572
Change-Id: I2caff721e98739f0c5978cca54d374cd959ac94a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1474004
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Clock gating list for CE was programmed at GR init, but at that time
CE has not yet been brought out of reset. This causes a priv ring
error and the clock gating setting does not take place. Move
programming of CE clock gating list to CE initialization.
Bug 1846641
Change-Id: Ibc9fe2487408358304f80cd679d3b1ecac7cebe8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473301
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Clock gating list contains a register which does not exist on gm20b.
Remove it from the list.
Bug 1846641
Change-Id: Ifb6f5c46482bcaad626bc875e9858d486d3dfa1c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473223
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
KASAN reports below slab-out-of-bounds error when accessing
gr->map_tiles since gr->map_tiles is allocated with wrong(small) size.
fixing it by passing correct size to nvgpu_kzalloc.
BUG: KASAN: slab-out-of-bounds in gr_gk20a_init_map_tiles+0x6f0/0x7b0 ...
....
BUG: KASAN: slab-out-of-bounds in gr_gk20a_zcull_init_hw+0x184/0x848 ...
...
BUG: KASAN: slab-out-of-bounds in gr_gk20a_setup_rop_mapping+0x108/0x1740 ...
...
BUG: KASAN: slab-out-of-bounds in gr_gk20a_setup_rop_mapping+0x108/0x1740 ...
Bug 1918671
Change-Id: I667ac80b20a3d8539ed3eaae6e0f98e91f917819
Signed-off-by: David Pu <dpu@nvidia.com>
Reviewed-on: http://git-master/r/1472491
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- struct nvgpu_falcon to hold properties of falcon controller
- falcon controller interface layer which establish access
to required falcon controller HAL based on struct nvgpu_falcon member
flcn_id & flcn_base parameter.
- each falcon nvgpu_falcon struct initialized during init
with id, base-address along with other properties at HAL.
- Added defines related to flacon controller.
Change-Id: Ia7777c01ecc542150ddd72f8603b7b4475522b58
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1467523
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Remove an unused variable that missed compilation checks because
it gets assigned to by do_div(). This same issue was propagated
to multiple places.
Change-Id: Ica2f675abbb3c08107ea4e6bc19044c0537a7484
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1472365
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
In the Linux kernel many bitmap operations are included in bitmap.h
and not in bitops.h. In nvgpu it seems we assume that these two sets
of functions are contained in the same header. This patch ensures
then when including bitops.h we get both bitmap declarations and bit
ops declarations.
Change-Id: I9fea75d6c920e1a2992922f927f2d91bbdbdedd3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1472364
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
use memset to fill structures with zero instead of
assigning zero.
mark functions local to the file as static
fixing errors in clk, perf and therm modules.
Bug 200299572
Change-Id: I0470298803c35b6faed2edc2a0c1dbf0e47e842e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1472940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix issues related with wrong storage type for
64 bit variables.
(1) Fixed width of HZ_TO_MHZ constant
(2) changed fence_wait timeout to store unsigned
long
bug 200299572
Change-Id: Ie8f2386b738f3aafce75fc2440947e36befac273
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1471611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
We access ROM control register with xve_writel, but we also
add the base register address. This leads to adding the base
address twice, and the access goes to wrong register.
Bug 1846641
Change-Id: I46ef277aac661a08049935b08505120cad1a5e76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1471505
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Write an error to UART on priv ring error. This uncovers any
accesses to missing registers or illegal accesses to registers.
Bug 1846641
Change-Id: Ic1e5ecadcd95777f2b3f7bd77accf98ddce97282
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294683
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Use an nvgpu_mem created from a page in the ACR code instead of
a scatter gather table created by the Linux SGT APIs. The ACR code
needs to have the GPU map a physical page queried from an external
API (other than the regular DMA API).
Note that this code used to explicitly mark the SGT it makes as
bypassing the SMMU. However, that is now taken care of implicitly
by the __nvgpu_mem_create_from_pages() function.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ie40152a7611e985e1b97ac2ddc7e27664b71917c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464082
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The gfp_t argument for dma_alloc_attrs() cannot take DMA_MEMORY_NOMAP -
it's interpreted as __GFP_RECLAIMABLE which has the same integer value.
Use GFP_KERNEL for the flag argument and set DMA_ATTR_NO_KERNEL_MAPPING
for dma attrs which the code was trying to do with the flag that is
meant for the coherent allocation API.
Bug 200299572
Change-Id: Ie4d988fbeeb954f6f7ccd4f9fb438968d76f0c6c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1468315
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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nvgpu is being modularized for kernel-4.4 and newer kernels.
__alloc_fd() can't be used on modules as it is not exported.
So, use a wrapper tegra_fd_alloc() instead of __alloc_fd()
bug 200290850
Change-Id: I0e63307d429774440753698643ba7620c1e1f9f6
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1469313
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Use struct nvgpu_mem for DMA allocations (and the corresponding
nvgpu_dma_alloc_sys()) instead of custom rolled code. This migrates
away from using linux scatter gather tables directly. Instead this
is hidden in the nvgpu_mem struct. With this change the semaphore.c
code no longer has any direct Linux dependencies.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I92167c98aac9b413ae87496744dcee051cd60207
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464081
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Add a function to create a nvgpu_mem from a list of arbitrary pages.
This API is useful for pages not necessarily allocated by the Linux
page allocator. It is useful for making nvgpu_mems that represent
carveouts or other things like that.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ibcb6432f077a6b0ecf9d183248e47a1f9ecb3ddd
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464080
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Replace a couple of boolean fields in nvgpu_mem with bits in a
bitmap introduced in an earlier patch.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Iffc31bd629cab9a37e5a4fd13377eb9090353410
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464079
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Move and rename the functions that build sgtables for nvgpu_mems into
the Linux specific DMA code.
One place outside of the Linux code do include the Linux DMA header.
That will be fixed in a subsequent patch.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ie43c752b8f998f122af70f7c7eb727af0b0d98df
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464078
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Add an API for creating a special sub-nvgpu_mem struct. This struct
comes with some fairly important caveats but is very useful for the
semaphore code.
Also, make sure that in nvgpu_mem_begin() and nvgpu_mem_end() no
additional mappings are made if not necessary. More importantly during
nvgpu_mem_end() it would be possible to vunmap() a CPU mapping of a
DMA allocation that does not expect this to happen.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I579429da9ff7288488753a113bafc558e0f17a0f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464077
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Get function declaration from fb_gm20b.h. This solves
Sparse warnings due to the missing of function prototype.
bug 200299572
Change-Id: Ie692f88e5bfc771bfcbb713adda3776521788f8c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/1468858
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This
includes some functions in allocators that were used only for
debugging.
Remove include of linux/debugfs.h on files that do not deal with
debugfs.
linux/debugfs.h implicitly included linux/fs.h, which we relied on.
Add explicit include of linux/fs.h for all files where this is the
case.
Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467897
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Hide the Linux specific nvgpu_mem fields so that in subsequent patches
core code can instead of using struct sg_table it can use mem_desc.
Routines for accessing system specific fields will be added as needed.
This is the first step in a fairly major overhaul of the GMMU mapping
routines. There are numerous issues with the current design (or lack
there of): massively coupled code, system dependencies, disorganization,
etc.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I2e7d3ae3a07468cfc17c1c642d28ed1b0952474d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464076
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An extra semicolon was left in the nvgpu_log() macro. Remove this
semicolon.
Change-Id: I36d15d165b2f6ecf7e5f6c5cc477254fc9fc9252
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464075
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move the Linux specific header files to include/nvgpu/linux/ to keep
the header files more organized. Having tons of Linux specific stuff
pollute the top level include seems like a bad idea.
Change-Id: I4913429c79d49f91c521021e5c0a613db453006a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464074
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Separated parameters for GM20B GPC PLL revisions B1 (default), and C1
(new, not characterized, yet). For now, used C1 spec settings.
Skipped PL divider glitch WAR, since revision C1 is glitchless.
Bug 1851797
Bug 1867980
Change-Id: I12dc101d002a41230e9323c47af234f6bae8e034
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1461680
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