Create interrupt hal unit under hal.gr.intr.
This holds the interrupt and exception related hals.
Move enable_exceptions and enable_gpc_exceptions hal functions to
hal.gr.init location.
Modify enable_exceptions hal to pass gr->config and enable or disable
parameters.
Modify enable_gpc_exceptions to pass gr->config parameter.
Add new hal function enable_interrupts with enable or disable parameter
This hal helps to enable and disable the gr interrupts as needed.
gr init calls that use these hals are modified to
g->ops.gr.intr.enable_exceptions
g->ops.gr.intr.enable_gpc_exceptions
JIRA NVGPU-3016
Change-Id: Ib62f8bf0b5289b815c8eff4d32a47387f24af51b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077857
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Move g->ops.gr.commit_global_bundle_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_bundle_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Jira NVGPU-2961
Change-Id: I6358dce963857402aa1d4d5606bf75398b9be83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077216
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Move g->ops.gr.get_global_ctx_cb_buffer_size() and
g->ops.gr.get_global_ctx_pagepool_buffer_size() hals to hal.gr.init
unit
Move corresponding hal definitions to hal.gr.init unit
Jira NVGPU-2961
Change-Id: Ifff3e2073f6d9bca5b37244f7e107bad885e7ca7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077215
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Remove below variables from struct gr_gk20a
u32 bundle_cb_default_size;
u32 min_gpm_fifo_depth;
u32 bundle_cb_token_limit;
u32 attrib_cb_default_size;
u32 alpha_cb_default_size;
u32 attrib_cb_gfxp_default_size;
u32 attrib_cb_gfxp_size;
u32 attrib_cb_size;
u32 alpha_cb_size;
Instead add below hals in hal.gr.init unit to get all of above sizes
u32 (*get_bundle_cb_default_size)(struct gk20a *g);
u32 (*get_min_gpm_fifo_depth)(struct gk20a *g);
u32 (*get_bundle_cb_token_limit)(struct gk20a *g);
u32 (*get_attrib_cb_default_size)(struct gk20a *g);
u32 (*get_alpha_cb_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_size)(struct gk20a *g);
u32 (*get_attrib_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_alpha_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_global_attr_cb_size)(struct gk20a *g, u32 max_tpc);
Define these hals for all gm20b/gp10b/gv11b/gv100/tu104 chips
Also add hal.gr.init support for gv100 chip
Remove all accesses to variables from struct gr_gk20a and start using
newly defined hals
Remove below hals to initialize sizes since they are no more required
g->ops.gr.bundle_cb_defaults(g);
g->ops.gr.cb_size_default(g);
g->ops.gr.calc_global_ctx_buffer_size(g);
Also remove definitions of above hals from all the chip files
Jira NVGPU-2961
Change-Id: I130b578ababf22328d68fe19df581e46aebeccc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077214
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Add new hal fifo_access to control the gr_gpfifo_ctl_r register to
enable or disable the access bit and semaphore access bit.
g->ops.gr.init.fifo_access function call with true or false
parameter to enable or disable the fifo_access.
JIRA NVGPU-2951
Change-Id: I67ad7ce9f176d7ce347e8acb425f7a4bb9e088ca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077705
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init_pbdma_intr_descs HAL ops is used to update the internal values of
the struct intr within struct fifo_gk20a. Three kinds of
intr_descriptors are filled i.e. device_fatal_0, channel_fatal_0 and
restartable_0. Breaking them into separate HALs has the advantage of
reusing the h/w headers corresponding to the device_fatal_0 as they are
same across all the architectures while those of channel_fatal_0 varies.
Another advantage is to now decouple pbdma from filling in values
within the fifo_gk20a struct. A new method gk20a_fifo_init_pbdma_descs
is constructed that initializes the above intr struct by calling the
separate HAL ops for these.
Jira NVGPU-2950
Change-Id: I78ddc61a5d9b2088d34259af90f8b85817bf19d9
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072741
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The following HAL pointers are moved to a separate HAL unit named pbdma.
pbdma_acquire_val
get_pbdma_signature
dump_pbdma_status
handle_pbdma_intr_0
handle_pbdma_intr_1
read_pbdma_data
reset_pbdma_header
The functions corresponding to these HAL units are also moved to
pbdma_{arch} files under hal/fifo correspondinging to arch gm20b,
gp10b, gv11b and tu104. Any calls to gk20a_readl and gk20a_writel
are replaced by nvgpu_readl and nvgpu_writel respectively.
Jira NVGPU-2950
Change-Id: I9723f30ddf6582df02c03fceb1fba26a206e1230
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071782
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Move load_smid_config and program_sm_id_numbering hal functions to
corresponding hal files in hal.gr.init.
Add new hal for get_sm_id_size and new static function in common.gr
init code for gr_load_sm_id_config.
JIRA NVGPU-2951
Change-Id: I27755306d278db9fcd5ab60169a64057b2989ea8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075875
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Move load_tpc_mask and setup_rop_mapping hal functions to hal.gr.init.
Existing load_tpc_mask hal code is split to two parts, one as a common
code in gr_load_tpc_mask and register write to init.tpc_mask hal
functions.
Modify pd_tpc_per_gpc and pd_skip_table_gpc hals in the
hal.gr.init to pass struct nvgpu_gr_config as a parameter.
JIRA NVGPU-2951
Change-Id: I52e26d0f023afa511a8cf8c3e4c54f45350be4ae
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2074892
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Add new hals in unit hal.gr.init to commit RTV circular buffer
g->ops.gr.init.commit_rtv_cb()
g->ops.gr.init.commit_gfxp_rtv_cb()
Remove tu104 hal to commit global ctx buffers
gr_tu104_commit_global_ctx_buffers() since we have specific hals to
commit RTB circular buffer
Update gr_gk20a_commit_global_ctx_buffers() to directly call
hal.gr.init hals to commit RTV buffers
Jira NVGPU-2961
Change-Id: I12a53386654ebfeb98bf187385bb8b839070d569
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075230
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Move g->ops.gr.commit_global_timeslice() hal operation to hal.gr.init
unit as g->ops.gr.init.commit_global_timeslice()
Drop channel pointer in parameter list since it was unused
Also change return type to void since it never returns error
Move corresponding gm20b and gv11b hal operations to hal.gr.init unit
Jira NVGPU-2961
Change-Id: I68deef45af1d52149eb354a1478cc2b5f2e4ec2a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075228
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Add a new hal operation g->ops.gr.init.load_method_init() in hal.gr.init
unit that reads method init netlist bundle and writes those values to
h/w appropriately
Use new hal in gr_gk20a_init_golden_ctx_image() instead of direct
register accesses
Jira NVGPU-2961
Change-Id: If1edd09445e55b5ad9cb1ec7b0f32cab9bfd6f05
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075227
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Native and vgpu were using different paths for fifo
init/deinit code.
Use same nvgpu_fifo_init_support for init code:
nvgpu_fifo_init_support
g->ops.fifo.setup_sw
vgpu_fifo_setup_sw (NEW)
Use same nvgpu_fifo_remove_support for deinit code:
nvgpu_fifo_remove_support (NEW)
g->ops.fifo.cleanup_sw (NEW)
vgpu_fifo_cleanup_sw (NEW)
Also implemented gk20a_fifo_cleanup_sw for native case.
Jira NVGPU-1306
Jira NVGPU-2855
Change-Id: Iefe303cc224f804a206422e2efffda9da1616d89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029649
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Add new hal operation g->ops.gr.init.fe_go_idle_timeout() in hal.gr.init
unit to enable/disable fe_go_idle timeout
Use this hal in gr_gk20a_init_golden_ctx_image() instead of direct
register access
Remove timeout disable/enable code in gk20a_init_sw_bundle() since
parent API gr_gk20a_init_golden_ctx_image() is already taking care of
that
Jira NVGPU-2961
Change-Id: Ice72699059f031ca0b1994fa57661716a6c66cd2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072550
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Earlier falcon HAL ops were embedded in the falcon structure. For clear
separation of common and HAL these ops will have to be accessed through
g->ops.falcon interfaces.
With these changes nvgpu_falcon_* functions directly call falcon gpu
ops functions for falcon. Falcon registers and HAL functions are
exported from falcon_gk20a.h. HAL files per platform are now
updated with base falcon functions.
Falcon software state such as is_falcon_supported, is_interrupt_enabled
and flcn_base are set from software init functions defined per chip.
JIRA NVGPU-2038
Change-Id: Ib1729d2833cd2c6c7b2c8ed7cbc17d4d6daeba73
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023077
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Add fifo sub-unit to common.fifo to handle init/deinit code
and global support functions.
Split init into:
- nvgpu_channel_setup_sw
- nvgpu_tsg_setup_sw
- nvgpu_fifo_setup_sw
- nvgpu_runlist_setup_sw
- nvgpu_engine_setup_sw
- nvgpu_userd_setup_sw
- nvgpu_pbdma_setup_sw
Split de-init into
- nvgpu_channel_cleanup_sw
- nvgpu_tsg_cleanup_sw
- nvgpu_fifo_cleanup_sw
- nvgpu_runlist_cleanup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_userd_cleanup_sw
- nvgpu_pbdma_cleanup_sw
Added the following HALs
- runlist.length_max
- fifo.init_pbdma_info
- fifo.userd_entry_size
Last 2 HALs should be moved resp. to pbdma and userd sub-units,
when available.
Added vgpu implementation of above hals
- vgpu_runlist_length_max
- vgpu_userd_entry_size
- vgpu_channel_count
Use hals in vgpu_fifo_setup_sw.
Jira NVGPU-1306
Change-Id: I954f56be724eee280d7b5f171b1790d33c810470
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2029620
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Register write from gr_gk20a_init_fs_state function are moved to hal.
New hal added for setting the pd_tpc_per_gpc, pd_skip_table_gpc and
cwd_gpcs_tpcs_num.
pd_tpc_per_gpc helps to describe the number of tpcs in each logical
gpc.
pd_skip_table helps to skip certain TPCs during distribution.
cwd_gpcs_tpcs_num helps to set number of tpcs and gpcs in CWD.
remove write for depreciated NV_PBE_PRI_ZROP_SETTING_NUM_ACTIVE_FBPS
and NV_PBE_PRI_CROP_SETTINS_NUM_ACTIVE_FBPS fields from
BES_ZROP_SETTINGS and BES_CROP_SETTINGS registers. Both these fields
changed to NUM_ACTIVE_LTCS from gm20b onwards and those are being
set in existing hal functions.
JIRA NVGPU-2951
Change-Id: I905b98356e8eadaf7e2481850de841c050ea50c5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072249
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create new hals for wait_idle and wait_fe_idle under gr.init.
modify functions to following hals and use same hals for all chips.
gr_gk20a_wait_idle -> gm20b_gr_init_wait_idle
gr_gk20a_wait_fe_idle -> gm20b_gr_init_wait_fe_idle
JIRA NVGPU-2951
Change-Id: Ie60675a08cba12e31557711b6f05f06879de8965
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072051
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gr_gk20a_init_golden_ctx_image() right now resets sys/gpc/be units by
directly accessing gr_fecs_ctxsw_reset_ctl_r() register
Move this register write/read sequence to common.hal.gr.init unit
through HAL operation g->ops.gr.init.override_context_reset()
Use new HAL in gr_gk20a_init_golden_ctx_image()
Also fix the delay() operations. delay() should be added before we read
back gr_fecs_ctxsw_reset_ctl_r() register and not after
Jira NVGPU-2961
Change-Id: I70d3a61b5aa60846815dee52ecac544066542695
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070608
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Add new HAL unit common.hal.gr.init with below source files
hal/gr/init/gr_init_gm20b.c
hal/gr/init/gr_init_gm20b.h
In gr_gk20a_init_golden_ctx_image() we force FE power mode on and also
disable it. Extract out this sequence into new unit and expose new HAL
operation that takes a boolean flag to enable/disable power mode
g->ops.gr.init.fe_pwr_mode_force_on()
Use new HAL operation in gr_gk20a_init_golden_ctx_image()
Set this HAL for all the chips
Jira NVGPU-2961
Change-Id: I1dd35d94fda5e5296af67c0abc944e200fb752ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070607
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The functions gk20a_dump_eng_status and gv11b_dump_eng_status belongs
to engine_status HAL unit.
1) The corresponding declaration and definitions of the above functions
are moved from fifo_{arch} files to engine_status_{arch} files.
2) The corresponding HAL pointer .dump_eng_status is moved from
fifo to engine_status HAL unit.
3) gv11b_dump_eng_status is now based to gv100b_dump_eng_status
4) Small changes in the files for ENGINE_STATUS such as correction of
HEADER DEFINES etc
Jira NVGPU-1315
Change-Id: I7fc06eab97206bc3b78c6f5c7aa30fa2c034961c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033632
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The corresponding HAL pointer for gk20a_fifo_wait_engine_idle is not
being invoked anywhere and hence they are removed from the code.
The function gk20a_fifo_wait_engine_idle belongs to engine unit and is
only called in a non-safe build, hence its moved to engine unit and is
restricted by a non-safe build flag NVGPU_ENGINE
Also, gk20a_fifo_wait_engine_idle is renamed to nvgpu_engine_wait_for_idle
Jira NVGPU-1315
Change-Id: Ie550c7e46a4284dfe368859d828b1994df34185f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033631
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is_fault_engine_subid_gpc HAL pointer belongs to engine HAL unit instead of
fifo. This patch moves the HAL pointer to a newly constructed engine
HAL unit.
The following new files are added under HAL/fifo/
engines_gm20b.h
engines_gm20b.c
engines_gv11b.h
engines_gv11b.c
Jira NVGPU-1315
Change-Id: If28686bf7350563b06b13348a9fe3ef0099c35b2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2031659
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Create Compression Bit Cache(CBC) unit to have comptags
cache related functionality in one place. In this patch
Moved following gpu ops from ltc to cbc and renamed accordingly:
void (*init)(struct gk20a *g, struct gr_gk20a *gr);
u64 (*get_base_divisor)(struct gk20a *g);
int (*alloc_comptags)(struct gk20a *g, struct gr_gk20a *gr);
int (*ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max);
u32 (*fix_config)(struct gk20a *g, int base);
To avoid ambiguity renamed function pointer from
init_comptags to alloc_comptags.
Moved following function from ltc.h to cbc.h:
nvgpu_ltc_alloc_cbc -> nvgpu_cbc_alloc
Also changed file name that implemented
nvgpu_cbc_alloc functionality from
os/ltc.c -> os/linux-cbc.c
JIRA NVGPU-2897
Change-Id: Ide32a98567e9a3f0a784d62221a6f484f8343e53
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030194
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In case of FBPA we need to consider mask of active FBPAs on dGPUs.
For that we have GR unit HAL g->ops.gr.add_ctxsw_reg_pm_fbpa()
Generic support to consider active mask of unit need not be in a HAL,
move it to common code in add_ctxsw_buffer_map_entries_subunits() itself
This API now supports providing active_unit_mask as its parameter
In case we don't need to consider unit mask caller will simply pass
~U32(0U) to indicate all units are active
In case of FBPA, add a new HAL g->ops.gr.hwpm_pm.get_active_fbpa_mask()
which gets mask of active FBPAs, and pass this value to common API
add_ctxsw_buffer_map_entries_subunits()
Jira NVGPU-2895
Change-Id: I0d208ce53abcd36929c25a4d248868d6eaa5c70d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069472
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Create a new HAL unit hal.gr.hwpm_map that provides chip specific
support to common.gr.hwpm_map unit
We currently have common.gr HAL g->ops.gr.add_ctxsw_reg_perf_pma()
to handle chip specific alignment of perf_pma list
We only adjust the offset of list and remaining code is same
Hence delete above HAL, and add new HAL under hal.gr.hwpm_map
g->ops.gr.hwpm_map.align_regs_perf_pma() which returns correct
alignment if HAL is defined
Remove gr_gv100_add_ctxsw_reg_perf_pma() and
gr_gk20a_add_ctxsw_reg_perf_pma() APIs since they are no longer used
Simplify perf_pma parsing by fixing alignment with new HAL and then
directly calling add_ctxsw_buffer_map_entries()
Jira NVGPU-2895
Change-Id: I1852db846e1f5441e482028c79a3f39c5142b0c2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069471
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Currently ACR chip specific properties set using HAL ops but
need to move out from HAL ops as ACR unit doesn't access
H/W directly & uses other engines to execute ACR on chip.
To fix used GPUID to init ACR chip specific properties
JIRA NVGPU-2909
Change-Id: I8fa1abcace6f7870bd116d39f94430497d80840b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032666
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In gr_gk20a_init_gr_config() we right now directly access a register
from hw_pri_ringmaster_*.h h/w header to read FBP count
Add a new HAL operation to PRIV_RING unit and start using it in GR code
instead of directly accessing register
g->ops.priv_ring.get_fbp_count()
Jira NVGPU-2894
Change-Id: I8a7b5423e28ef40612f55cb2915d7a2cff2f7435
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030673
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Below HALs to get max FBPs, max LTC per FBP, max LTS pet LTC values are
right now defined by GR unit.
g->ops.gr.get_max_fbps_count()
g->ops.gr.get_max_ltc_per_fbp()
g->ops.gr.get_max_lts_per_ltc()
These HALs only read registers from hw_top_*.h h/w unit, and as such
belong to TOP unit. Move them appropriately as below
g->ops.top.get_max_fbps_count()
g->ops.top.get_max_ltc_per_fbp()
g->ops.top.get_max_lts_per_ltc()
Remove hw_top_*.h h/w header include from gr_gk20a.c and gr_gm20b.c
Jira NVGPU-2894
Change-Id: I995d9f56edb65c9de98d2d15d34ecb72920a65c6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030672
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
