Commit Graph

271 Commits

Author SHA1 Message Date
ajesh
a6cbfca58c gpu: nvgpu: fix MISRA violations in bitops unit
Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset.  OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.

Jira NVGPU-3545

Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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2019-06-11 22:26:41 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Thomas Fleury
0624d908cd gpu: nvgpu: unit: add channel close tests
Add branch coverage for:
- nvgpu_channel_kill
- nvgpu_channel_close

Also, modified gk20a_free_channel as follows:
- use nvgpu_assert to check ch->g (so that it can be tested)
- make sure g is non-NULL before calling nvgpu_get_poll_timeout

Jira NVGPU-3480

Change-Id: Ie1fa231b022da47b9ef9022ae67a6b3d73c28a8b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129724
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2019-06-10 19:45:17 -07:00
Thomas Fleury
6602baaf41 gpu: nvgpu: unit: add tsg setup_sw/cleanup_sw coverage
Add unit test for:
- nvgpu_setup_sw
- nvgpu_cleanup_sw

Made nvgpu_tsg_init_support return void, since it cannot fail.

Jira NVGPU-3476

Change-Id: Ifff115e98c097375d7920b79ae9e13657d54a357
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124512
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2019-06-09 22:55:18 -07:00
Lakshmanan M
57170db65a gpu: nvgpu: fifo: Call os specific channel open only for kernel mode submit
Restricted the os specific channel open only for kernel mode submit.
For linux, g->os_channel.open is just noop.
For QNX, nvgpu creates the sync point notifier thread for
job tracking. This job completion tracking is only required
for kernel mode submit. This sync point notifier thread
is not required for user mode submit.

JIRA NVGPU-2944

Change-Id: Ie37824aac3609090ef9da378202dbc211a2eb0b3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131386
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2019-06-06 16:29:50 -07:00
Deepak Nibade
649a2b57a8 gpu: nvgpu: add debugger flag for hal.gr.gr unit
Add NVGPU_DEBUGGER flag for common.hal.gr.gr unit and corresponding
hals.

Also add this flag for deferred reset functionality

Jira NVGPU-3506

Change-Id: Iee4fbc1305346bb4d779cd69e8fd5539cb07206b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130149
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2019-06-06 16:28:44 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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2019-06-06 06:55:58 -07:00
Thomas Fleury
97762279b7 gpu: nvgpu: make nvgpu_init_mutex return void
Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.

This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.

Jira NVGPU-3476

Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
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2019-06-05 10:25:52 -07:00
Philip Elcan
f83447d134 gpu: nvgpu: mm: make num_user_mapped_buffers a u32
The vm object num_user_mapped_buffers was declared as an int. However,
it is an unsigned value. Being a signed value required a cast to
unsigned when calling nvgpu_big_zalloc() which causes a CERT-C INT31
violation. So, avoid the cast and use an unsigned type. And fix related
INT30 violations related to num_user_mapped_buffers as well.

To avoid introducing new MISRA/CERT-C violations, update the upstream
user of these changes, fifo/channel.c and make the equivalent uses of
this value, num_mapped_buffers a u32 as well.

JIRA NVGPU-3517

Change-Id: I6f6d9dfe4a0ee16789b8cd17b908a3f3f9c4a40c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127427
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2019-06-04 15:15:33 -07:00
Seema Khowala
a72bfa63b2 gpu: nvgpu: Add NVGPU_FEATURE_POWER_PG compiler flag
This flag is added to compile out below features from
safety build
-elpg

JIRA NVGPU-3425

Change-Id: I439edb444a4ebe1732a379aecbb0ffc8b48eb97c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127449
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2019-06-04 12:05:49 -07:00
Deepak Nibade
d16ddb244f gpu: nvgpu: remove g->ops.gr.halt_pipe hal
Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe

Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe

Jira NVGPU-3506

Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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2019-06-03 04:15:41 -07:00
Thomas Fleury
a1248d87fe gpu: nvgpu: add refcounting for MMU debug mode
GPC MMU debug mode should be set if at least one channel
in the TSG has requested it. Add refcounting for MMU debug
mode, to make sure debug mode is disabled only when no
channel in the TSG is using it.

Bug 2515097

Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123017
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2019-06-01 06:36:14 -07:00
Seema Khowala
1e7405a5dc gpu: nvgpu: Add NVGPU_FEATURE_CHANNEL_TSG_CONTROL compiler flag
This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id

JIRA NVGPU-3516

Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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2019-05-31 16:55:43 -07:00
Mahantesh Kumbar
90aee0086f gpu: nvgpu: rename NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU
renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0

JIRA NVGPU-3418

Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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2019-05-30 19:27:14 -07:00
Mahantesh Kumbar
120defb7cb gpu: nvgpu: compile out PMU mutex code for safety
Compile out PMU mutex calls called from other unit when
PMU RTOS support is disabled for safety build by setting
NVGPU_LS_PMU build flag to 0

NVGPU JIRA-3418

Change-Id: I040a744d5102f7fd889d4e8ad6e94129eadb73dd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124698
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2019-05-30 19:25:42 -07:00
Rajesh Devaraj
fcb7635a92 gpu: nvgpu: gops initialization for SDL
This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
  reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.

Jira NVGPU-3237

Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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2019-05-30 02:18:05 -07:00
Seema Khowala
31cbde4412 gpu: nvgpu: Add NVGPU_FEATURE_CHANNEL_TSG_SCHEDULING compiler flag
This flag is added to compile out below features from
safety build
-get_timeslice
-set_timeslice
-set_priority
-set_interleave
-reschedule_runlist
-boosted_ctx

JIRA NVGPU-3513

Change-Id: I9addacf96693195f05d216a177d5d4f670eba888
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124438
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2019-05-30 00:17:13 -07:00
Debarshi Dutta
040533a6ca gpu: nvgpu: separate usermode and kernelmode setup/free
nvgpu_channel_bind_setup is split into user_mode and kernel_mode
specific initialization. Avoid allocation of resources specific to
kernel_mode submits when the channel supports user_mode submits and
vice-versa. In future, a safety build will be used to compile out the
kernel_mode specific initialization for safety builds.

Jira NVGPU-3479

Change-Id: Idf158abc24a0b969a5c40f54fee6be4301a08773
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2122844
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2019-05-29 23:16:37 -07:00
Thomas Fleury
dbbb7d2965 gpu: nvgpu: remove nvgpu_tsg_update_sm_error_state_locked
Remove nvgpu_tsg_update_sm_error_state_locked which is not
used anymore.

Jira NVGPU-3476

Change-Id: I4188f6ff71c02045f1628d4be1599c891c2219b5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124411
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2019-05-23 17:45:58 -07:00
Seema Khowala
4cf2d2166c gpu: nvgpu: Add NVGPU_VPR compiler flag
This flag is added to compile out vpr support for
safety build.

JIRA NVGPU-3518

Change-Id: I6646a39ff6f1b7fd0948aacc3ede4a7a48bec734
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123900
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2019-05-23 17:45:40 -07:00
Debarshi Dutta
47dc0b9ebd gpu: nvgpu: move chip specific channel HAL files to hal/fifo/
Moved the channel HAL files from common/fifo/ to hal/fifo

Jira NVGPU-3248

Change-Id: Ibb85b7c0e71422dbd774a518e4f0bba0b97ef807
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123399
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2019-05-23 02:19:47 -07:00
Debarshi Dutta
0eb0242bdd gpu: nvgpu: rename public channel unit APIs
Rename the public channel unit APIs to follow the convention of
nvgpu_channel_*.

gk20a_channel_deterministic_idle -> nvgpu_channel_deterministic_idle
gk20a_channel_deterministic_unidle -> nvgpu_channel_deterministic_unidle
gk20a_wait_until_counter_is_N -> nvgpu_channel_wait_until_counter_is_N
nvgpu_gk20a_alloc_job -> nvgpu_channel_alloc_job

Jira NVGPU-3248

Change-Id: I358d63d4e891f6d92c70efe887c07674bc0f9914
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123398
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2019-05-23 02:19:38 -07:00
Mahantesh Kumbar
3d1169544f gpu: nvgpu: alloc space for PMU's struct nvgpu_pmu at runtime
Allocating space for struct nvgpu_pmu at run time as part of
nvgpu_pmu_early_init() stage and made required changes to
dependent fiels as needed.

JIRA NVGPU-1972

Change-Id: I2d1c86d713e533c256ba95b730aa2e9543a66438
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110109
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2019-05-23 00:56:55 -07:00
Mahantesh Kumbar
0a64f6cb2d gpu: nvgpu: PMU pmu.c/h header include cleanup
Some headers are not required to include in pmu.c/h as
lot of PMU code restructure happened, so removed headers
which not required anymore.

JIRA NVGPU-1972

Change-Id: Iead7f049d167cdaaaf7c75c2a5e19ae7b068fe6b
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110108
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2019-05-23 00:56:45 -07:00
Debarshi Dutta
f39a5c4ead gpu: nvgpu: rename gk20a_channel_* APIs
Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.

Jira NVGPU-3248

Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-05-21 09:26:16 -07:00
Thomas Fleury
3881dd6a26 gpu: nvgpu: fix build issue w/ NVGPU_CHANNEL_WDT
Fix build issue w/ safety build.
Add missing } when NVGPU_CHANNEL_WDT is not set.

Jira NVGPU-3012

Change-Id: I60f017a0203662b9acc8a2fa791079deade93736
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121305
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Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-18 03:54:52 -07:00
Antoine Chauveau
b8ba882399 gpu: nvgpu: Remove assertion which triggers intermittently
Partially revert patch c0e725a, which causes intermittent test
failures.

Bug 2599340

Change-Id: I4ac7ef007b4a7beaa2010cc3795ed0f78b4ce9c7
Signed-off-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120867
2019-05-17 04:52:47 -07:00
Debarshi Dutta
4c30bd599f gpu: nvgpu: rename tsg_gk20a*/gk20a_tsg* functions.
rename the functions with the prefixes tsg_gk20a*/gk20a_tsg*
to nvgpu_tsg_*

Jira NVGPU-3248

Change-Id: I9f5f601040d994cd7798fe76813cc86c8df126dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120165
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2019-05-17 01:49:27 -07:00
Debarshi Dutta
1dea88c6c7 gpu: nvgpu: Add NVGPU_CHANNEL_WDT flag
NVGPU_CHANNEL_WDT feature is embedded within the NVGPU_CHANNEL_WDT flag
to allow it to be compiled out for safety builds.

Jira NVGPU-3012

Change-Id: I0ca54af9d7b1b8e01f4090442341eaaadca8e339
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114480
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 23:28:13 -07:00
Seema Khowala
6f5cd4027c gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below functions
gk20a_enable_channel_tsg
gk20a_disable_channel_tsg

Rename
gk20a_disable_channel_tsg -> nvgpu_channel_disable_tsg
gk20a_enable_channel_tsg -> nvgpu_channel_enable_tsg

JIRA NVGPU-3388

Change-Id: I0c18c4a14a872cecb12ae3089da886be9da43914
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115211
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 16:25:22 -07:00
Philip Elcan
78c7e601f8 gpu: nvgpu: debug: fix MISRA 5.7 violation
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.

JIRA NVGPU-3346

Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 11:57:32 -07:00
Seema Khowala
fb603ef467 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert
nvgpu_channel_deferred_reset_engines

JIRA NVGPU-3388

Change-Id: I745de9fb618803824ae62ed586944ce5d838c92a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115787
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:47:24 -07:00
Seema Khowala
334f855ac4 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add void to ignore
the return value
update_gp_get

Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count

JIRA NVGPU-3388

Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:47:14 -07:00
Seema Khowala
766dfb2cb1 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_runlist_reload_ids

JIRA NVGPU-3388

Change-Id: Ie2bf6c48d4f9e673695dc6587df24651e9d8c78c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115767
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:47:05 -07:00
Seema Khowala
c0e725a576 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_preempt_channel

JIRA NVGPU-3388

Change-Id: Id60d10c0d1593a6b798a037b9ec0efe6c4d20dd5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115762
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:56 -07:00
Seema Khowala
7ebb9d85d9 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below functions and print error messages
g->ops.tsg.force_reset
nvgpu_channel_wdt_stop

JIRA NVGPU-3388

Change-Id: Ia02b0fe040d2181a2b2dc24ec56e443f59505e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:46 -07:00
Seema Khowala
c986b60c6f gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value and nvgpu_assert for
g->ops.mm.cache.fb_flush(g)

JIRA NVGPU-3388

Change-Id: I24ccc4ae57a2827423db4eb96726a0fe5a7f04df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:36 -07:00
Seema Khowala
c2b3da8e47 gpu: nvgpu: channel MISRA fix for Rule 17.7
Change gk20a_free_priv_cmdbuf from int to void type

Rename
gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry
channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q
free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry

JIRA NVGPU-3388
JIRA NVGPU-3248

Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:27 -07:00
Thomas Fleury
93bfdd3207 gpu: nvgpu: remove unused ch->gpfifo.wrap
ch->gpfifo.wrap was set when updating ch->gpfifo.get,
but never used afterwards. Removed.

Jira NVGPU-3388

Change-Id: I198e9ba0c3716a200a8937c2488cf35e04c0166f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 18:40:21 -07:00
Seema Khowala
8d34edfee0 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add err message
ch_data->unbind_single_channel

JIRA NVGPU-3388

Change-Id: Iac979c464600507b3fcfa907d9babc8bdc232338
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115832
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:10:27 -07:00
Seema Khowala
970096bfe4 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below functions and add warn/err messages
nvgpu_cond_broadcast_interruptible
nvgpu_cond_broadcast
nvgpu_cond_init

JIRA NVGPU-3388

Change-Id: Ie5fd9c461c00066d703e0d5900fc0248da2204db
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114919
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 22:28:22 -07:00
Seema Khowala
877de5b6bd gpu: nvgpu: channel MISRA fix for Rule 8.4
JIRA NVGPU-3388

Change-Id: I7633639f78f5585bdfb0b99459f82b36136fd31a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114894
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 22:28:12 -07:00
Seema Khowala
e7d50bd224 gpu: nvgpu: channel MISRA fix for Rule 10.4
Change local variable types to match types defined in struct
being accessed to assign local variables

Change input param types to match types defined in struct
being accessed to pass input params

JIRA NVGPU-3388

Change-Id: If3edc34de14d35d13e0a24e3c48f9cecc2df2a24
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114872
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 22:27:52 -07:00
Seema Khowala
e6a8e63bb6 gpu: nvgpu: channel MISRA fix for Rule 10.1
JIRA NVGPU-3388

Change-Id: I11b287239a36eaab5582428eb0d209520d0f286a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114871
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 22:27:43 -07:00
Seema Khowala
671f1c8a36 gpu: nvgpu: channel MISRA fix for Rule 21.2
Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 04:39:34 -07:00
Seema Khowala
26d13b3b6b gpu: nvgpu: channel MISRA fix for Rule 21.2
Rename functions starting with '_' and '__'.
__gk20a_channel_kill -> nvgpu_channel_kill
_gk20a_channel_from_id -> nvgpu_channel_from_id__func
gk20a_channel_from_id -> nvgpu_channel_from_id

JIRA NVGPU-3388

Change-Id: I3b5f63bf214c5c5e49bc84ba8ef79bd49831c56e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114037
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 04:39:08 -07:00
Seema Khowala
842c42249d gpu: nvgpu: channel MISRA fix for Rule 8.6
Remove unused function prototype.

JIRA NVGPU-3388

Change-Id: I3e6ce2321ab0ef5a73c257fc4ece984c02a0a051
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114036
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-09 04:38:53 -07:00
Seema Khowala
3d64bc19df gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of nvgpu_timeout_init and spit
error message. Also return to the calling function
upon timeout init error in few cases.

JIRA NVGPU-3383

Change-Id: I97fcc7343051842a74d9bf379c372b7094c8de86
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113157
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-07 20:28:21 -07:00
Thomas Fleury
44f6c10947 gpu: nvgpu: submit MISRA fixes for Rule 5.7
Renamed local variable
- sync_fence -> flag_sync_fence

As "sync_fence" is already used to represent a type.

Also, renamed for consistency:
- fence_wait -> flag_fence_wait
- fence_get -> flag_fence_get

Jira NVGPU-3384

Change-Id: Ib40d068f0ebda985303a85a385f4123955d3b4c9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111613
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 17:55:42 -07:00
Thomas Fleury
47b7820cb6 gpu: nvgpu: submit MISRA fixes for Rule 17.7
Check return value of gk20a_channel_add_job, and clean up
in case of failure.

Jira NVGPU-3384

Change-Id: Ic818d8bcf97fef6360aedd7a2a0a5a7f6f69150f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111612
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-06 17:55:28 -07:00