Commit Graph

2615 Commits

Author SHA1 Message Date
seshendra Gadagottu
caf168e33e gpu: nvgpu: gv11b: fix for gfx preemption
Used chip specific attrib_cb_gfxp_default_size and
attrib_cb_gfxp_size buffer sizes during committing
global callback buffer when gfx preemption is requested.
These sizes are different for gv11b from gp10b.

Also used gv11b specific preemption related functions:
gr_gv11b_set_ctxsw_preemption_mode
gr_gv11b_update_ctxsw_preemption_mode

This is required because preemption related buffer
sizes are different for gv11b from gp10b. More optimization
will be done as part of NVGPU-484.

Another issue fixed is: gpu va for preemption buffers
still needs to be 8 bit aligned, even though 49 bits
available now. This done because of legacy implementation
of fecs ucode.

Bug 1976694

Change-Id: I284e29e0815d205c150998b07d0757b5089d3267
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1630520
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Tested-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-01-08 12:16:49 -08:00
Sourab Gupta
667c9fd10b gpu: nvgpu: include nvgpu types.h explicitly in fence.h
QNX needs defines for u32 data type, which is retrieved from
nvgpu/types.h. We need to explicity include this for fence.h

Change-Id: I0768042b8b10db550a1e321a0c3c1d86d981f9b0
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1626401
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-08 08:45:48 -08:00
Sourab Gupta
3f4919ef32 gpu: nvgpu: replace pr_err with nvgpu_err
Replace the linux specific pr_err with nvgpu_err function

Change-Id: I856a3030c62009b078a8cdfc0050b541a66e6eaa
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1626400
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-08 08:45:40 -08:00
Sourab Gupta
cc94cb3b2b gpu: nvgpu: remove dma-buf.h include in channel
The patch removes the dma-buf.h include from channel_gk20a.c,
now that there are no references to dma_buf present here.

Change-Id: I079c3c3763e7ac4f91e43a4bc54a23ec8d5a23fa
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1626396
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-08 08:45:05 -08:00
David Nieto
1f71f475e2 DNI: gpu: nvgpu: Increase GV100 ctxsw timeouts
During bringup and before nvlink is up GV100 on the DDPX platform operates
with a very, very slow sysmem link. In order to get sysmem test to pass
it is neccesary to significantly increase most timeouts by an order the
magnitude.

Bug 2040544

Change-Id: I26858afde4ae80c70f86b47cfff674b6b00b5bf8
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627417
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2018-01-05 13:54:37 -08:00
Terje Bergstrom
dde1913f16 gpu: nvgpu: Do not disable ELPG when committing buffers
Committing buffer addresses only writes to the memory. There's no
need to disable ELPG for the duration, so drop the ELPG protection.

Change-Id: I8d8d08506387197e4737e0311df4a20085496056
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631149
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-01-04 11:04:43 -08:00
Terje Bergstrom
031eb0ec83 gpu: nvgpu: Remove gk20a specific optimization
Remove compute optimization specific to gk20a. We do not support
gk20a anymore.

Change-Id: Ibd548eee8d891a667f28a451d586fcfaac7f026a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631144
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2018-01-04 11:04:39 -08:00
Deepak Nibade
e0aca109b1 gpu: nvgpu: fix erroneous gk20a_put() call
With a recent rework we moved gk20a_get() call to nvgpu_ioctl_tsg_open(),
but corresponding gk20a_put() call remained in gk20a_tsg_release()

So if a TSG is opened and released from within kernel with APIs
gk20a_tsg_open()/gk20a_tsg_release() we mistakenly drop extra refcount
through gk20a_put()

Fix this by moving gk20a_put() call to nvgpu_ioctl_tsg_release() which
balances gk20a_get() call in nvgpu_ioctl_tsg_open()

Bug 200374011

Change-Id: Id0cec0426e6231309dc530ab5c934dacaba9f8da
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1630969
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-04 08:46:10 -08:00
Deepak Nibade
c7b7dbe39a gpu: nvgpu: return error code in failure cases
In gk20a_ce_create_context(), if gk20a_tsg_open() or gk20a_open_new_channel()
fails, we bail out from the function without setting the error code
This could mislead the caller and report incorrect success

Fix this by setting error code explicitly in failure cases

Bug 200374011

Change-Id: Idf6cba4a57740107bada698295745352f7b5d5ac
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1631506
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-04 08:46:07 -08:00
Deepak Nibade
5ad1c28b5f gpu: nvgpu: fix TSG leak from CE code
In gk20a_ce_delete_gpu_context(), we unbind the channel from TSG and
close the channel. But we do not drop the TSG refcount leaking
the TSG reference

Fix this by explicitly dropping TSG refcount

Also, do not explicitly unbind the channel from TSG
gk20a_channel_close() will internally unbind the channel from TSG

Bug 200374011

Change-Id: Ie4aa32f1d0bff4231f41aa2b33743cdc63e967c7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1629972
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-01-04 08:45:48 -08:00
Sourab Gupta
965ff380cf gpu: nvgpu: add golden_img_loaded flag to gr ctx desc
The patch adds the boolean flag 'golden_img_loaded'
to gr ctx desc. This is needed for refactoring the ctx
initialization.

Change-Id: I6d6df273e764a4cd06d062d59427dd33f4669778
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617174
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-01-04 00:36:21 -08:00
Terje Bergstrom
86691b59c6 gpu: nvgpu: Remove bare channel scheduling
Remove scheduling IOCTL implementations for bare channels. Also
removes code that constructs bare channels in runlist.

Bug 1842197

Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627326
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-02 13:53:09 -08:00
Terje Bergstrom
14fa8207e2 gpu: nvgpu: Remove TSG required flag
Remove nvgpu internal flag indicating that TSGs are required. We now
require TSGs always. This also fixes a regression where CE channels
were back to using bare channels on gp106.

Bug 1842197

Change-Id: Id359e5a455fb324278636bb8994b583936490ffd
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1628481
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2018-01-02 13:53:05 -08:00
Terje Bergstrom
b983c67d84 gpu: nvgpu: Initialize CE once channels resumed
Initialize CE channels and vidmem clearer only once channels have
been enabled.

Change-Id: Id4c870ee7d4632044b97cead5d0d7b8317170430
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1628167
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2017-12-29 13:31:03 -08:00
Terje Bergstrom
32353ab744 gpu: nvgpu: Implement abstraction for finding TID
Implement abstraction for finding the thread ID of thread currently
being run. This is tracked for context switch tracing.

In Linux kernel this is implemented by returning PID.

Change-Id: Id46a318894f9a2ff3c85d2c8ef0b02c52783f122
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627239
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-28 10:02:09 -08:00
David Nieto
8fb6a8562e gpu: nvgpu: gv11b: Report LTC errors per slice
Add support to report ltc ecc errors per slice

(1) use new logic to detect subunits
(2) store size of array and check before comparison to prevent out of bounds
 derefencing
(3) use new hashing to prevent collisions or entries with permuted names

bug 2037425

Change-Id: I63b9f0df43b9dceddc1bae17924c4723072f569e
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1620854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Tested-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-28 10:01:36 -08:00
Terje Bergstrom
f19f22fcc8 gpu: nvgpu: Remove support for channel events
Remove support for events for bare channels. All users have already
moved to TSGs and TSG events.

Bug 1842197

Change-Id: Ib3ff68134ad9515ee761d0f0e19a3150a0b744ab
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618906
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-28 10:01:32 -08:00
Terje Bergstrom
aa52601f62 gpu: nvgpu: Remove support for bare channels
Remove remaining support for bare channels. All users of bare
channels have already moved to TSGs.

Bug 1842197

Change-Id: I1ff12677253b160dac9bebe6925ad0839ea07cfc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1618905
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-28 10:01:28 -08:00
Supriya
ea1b69d3f5 gpu: nvgpu: Fix crash on read fail of mc_boot_0_r
This CL handles
- erroneous use of boot_0 function pointer
before being assigned in __nvgpu_check_gpu_state
- And proper handling of error returned from gk20a_readl
in gk20a_mc_boot_0
With these fixes crash is not seen in case mc_boot_0 read
returns 0 in gk20a_mc_boot_0
- And also this handles the recursion caused by mc.boot_0()
calling nvgpu_readl and nvgpu_readl in turn
calling mc.boot_0 in case of read failure

Bug 2010966

Change-Id: Ia087811c67d88948b7fc5fff35e0fabc6ea91989
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1616274
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2017-12-28 03:01:48 -08:00
Terje Bergstrom
3a956a573d gpu: nvgpu: Implement abstraction for finding TGID
Implement abstraction for finding the process ID of thread currently
being run. This is tracked for context switch tracing.

In Linux kernel this is implemented by returning TGID.

Change-Id: Ia6bcbd92c8cc25467694a35476e5d5f717194105
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615985
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2017-12-27 02:21:07 -08:00
seshendra Gadagottu
cb55553544 gpu: nvgpu: do channel resume after hw init
During finalize power on, resume channels only after
complete hw initialization is done. Otherwise it will
cause issues with unexpected usage of hw. During first
boot will not see these issues because there will no channels.
But after rail gate/ungate or suspend/resume these issues
can be seen if channels are present before rail-gate/suspend.

Bug 2039195

Change-Id: Ie96e2f2b91902ba18b37e9a167344eeae07ba8c2
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1625506
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-26 18:41:00 -08:00
Seema Khowala
57a7064ff4 gpu: nvgpu: gv11b: remove cde support
Change-Id: I04df795b20413a2d07a252d77b3eba853890fcae
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1624087
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-26 15:15:39 -08:00
Deepak Goyal
49be5d4929 gpu: nvgpu: gv11b: implement ecc scrubber
Check the availability of ecc units by checking
relevant ecc fuse and fuse overrides.

During gpu boot, initialize ecc units by scrubbing
individual ecc units available.  ECC initialization
should be done before gr initialization.

Following ecc units are scrubbed:
SM LRF
SM L1 DATA
SM L1 TAG
SM CBU
SM ICACHE

Bug 200339497

Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612734
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-14 09:03:45 -08:00
Terje Bergstrom
6e3f9112ea gpu: nvgpu: Disallow use of bare channels
All channels need to now be wrapped in TSGs. Disallow use of bare
channels by preventing creation of GPFIFO for them.

Bug 1842197

Change-Id: Id0ebee4c590804b96c09f8951e35ba2680b596e7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612697
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-12-12 14:03:57 -08:00
David Nieto
258ae44712 gpu: nvgpu: gv11b: PMU parity HWW ECC support
Adding support for ISR handling of ECC parity errors for PMU unit and setting
the initial IRQDST mask to deliver ECC interrupts to host in the non-stall
PMU irq path

JIRA: GPUT19X-83

Change-Id: I8efae6777811893ecce79d0e32ba81b62c27b1ef
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611625
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2017-12-11 16:42:01 -08:00
Richard Zhao
fa1b18c171 gpu: nvgpu: vgpu: add tsg release command
gv11b needs tsg release callback to release CE method buffer.

Bug 2022929

Change-Id: I32e27a5fa49eb61b9c2fc72ea32034191a9be48e
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1611631
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aparna Das <aparnad@nvidia.com>
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2017-12-10 10:36:39 -08:00
Deepak Nibade
f3dcf5f534 gpu: nvgpu: fix int declaration
variable g->gr.ctx_vars.regs_base_index is declared as "int", but it is assigned
value from unsigned int pointer
Since we expect it to be unsigned at all the places, declare it as "u32" instead
of "int"

Jira NVGPU-449

Change-Id: I2a5b35698c655fa0caa3e38e37ed4d84569c996a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612446
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-08 11:58:22 -08:00
Deepak Nibade
ac78f5d95e gpu: nvgpu: use nvgpu API to check for allocated memory
In __gr_gk20a_exec_ctx_ops(), we directly access linux specific pages to check
if memory is allocated or not
Since we need to remove this linux specific dependency from common code,
use common API nvgpu_mem_is_valid() to check if memory is allocated or not

Jira NVGPU-448

Change-Id: Iad62482ad1c0dfad3b96c6c125c2641bbe6ea596
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612445
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-08 11:58:18 -08:00
Deepak Nibade
9f404b811c gpu: nvgpu: fix unsigned int declaration
In gr_gk20a_init_access_map(), we declare num_entries as "unsigned int"
But this variable is implicitly type casted into "int" while calling subsequent
functions

Hence explicitly declare it as type "int"

Also declare variable "w" as "int" too since we use it to compare against
num_entries

Jira NVGPU-446

Change-Id: I289da6951db0a9ed6b8d6bcb3ee4f6071a4ddaf0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612444
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-08 11:58:15 -08:00
Deepak Nibade
6ec7da5eba gpu: nvgpu: use nvgpu list APIs instead of linux APIs
Use nvgpu specific list APIs nvgpu_list_for_each_entry() instead of calling
Linux specific list APIs list_for_each_entry()

Jira NVGPU-444

Change-Id: I3c1fd495ed9e8bebab1f23b6769944373b46059b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612442
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-12-08 11:58:07 -08:00
Sourab Gupta
5791b47d81 gpu: nvgpu: remove inline keyword from css_hw_set_handled_snapshots
The patch removes the inline qualifier from the
'css_hw_set_handled_snapshots' function, otherwise
it leads to QNX compilation failure.

Change-Id: I5c3462b61fbfb2b549e711dd2b45032b3a87089c
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1610984
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-12-05 23:14:03 -08:00
David Nieto
1b125d8cbe gpu: nvgpu: fix indexing in locate pte function
The current code does not properly calculate the indexes within the PDE
to access the proper entry, and it has a bug in assignement of the big
page entries. This change fixes the issue by:

(1) Passing a pointer to the level structure and dereferencing the
index offset to the next level.
(2) Changing the format of the address.
(3) Ensuring big pages are only selected if their address is set.

Bug 200364599

Change-Id: I46e32560ee341d8cfc08c077282dcb5549d2a140
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1610562
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Bhosale <dbhosale@nvidia.com>
2017-12-05 10:25:37 -08:00
Terje Bergstrom
da9b1bbac2 gpu: nvgpu: Introduce include/nvpgu/sizes.h
We use SZ_* #defines in some parts of nvgpu, but we don't explicitly
include a header that defines it. Add include/nvgpu/sizes.h that in
Linux #includes linux/sizes.h.

Change-Id: I8f506d85c7eaa12e649f5874a87533e2f0fe9438
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607575
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2017-12-01 08:37:08 -08:00
Mahantesh Kumbar
5e9f4bbf8d gpu: nvgpu: remove linux dependent from pmu_gk20a.c
- Removed Linux dependent header
- Moved thermal alarm post from pmu_gk20a.c
to clk_arb.c
- Implemented nvgpu_clk_arb_send_thermal_alaram()
method to post
NVGPU_GPU_EVENT_ALARM_THERMAL_ABOVE_THRESHOLD

JIRA NVGPU-403

Change-Id: Ibf85c2f3a6e704fdcc0502745fab820f7ea428f4
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1608313
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-11-30 23:53:31 -08:00
Sami Kiminki
d73ad6c07d gpu: nvgpu: Alignment check for compressible fixed-address mappings
Add an alignment check for compressible-kind fixed-address
mappings. If we're using page size smaller than the comptag line
coverage window, the GPU VA and the physical buffer offset must be
aligned in respect to that window.

Bug 1995897
Bug 2011640
Bug 2011668

Change-Id: If68043ee2828d54b9398d77553d10d35cc319236
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606439
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2017-11-30 18:57:19 -08:00
Deepak Nibade
7cecf8cf9e gpu: nvgpu: remove linux specific include from gr_*.c files
Remove linux specific #include "common/linux/os_linux.h" from common source
files gr_gk20a.c/gr_gm20b.c/gr_gp10b.c

Remove use of ZERO_OR_NULL_PTR() and simply check if pointer is NULL or not

Jira NVGPU-405

Change-Id: I663fe298cc720f0b0e22beaa05697b18b375a204
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1607233
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2017-11-30 03:58:47 -08:00
seshendra Gadagottu
7a4cb4a6ab gpu: nvgpu: gv11b: gfxp wfi timeout
For gv11b, configured gfx preemption wfi timeout in usec.
Set timeout unit as usec in gr_gv11b_init_preemption_state.
Used default timeout as 1msec and this timeout value can
be modified through sysfs node:
/sys/devices/gpu.0/gfxp_wfi_timeout_count

For gp10b:
gfxp_wfi_timeout_count is in syclk cycles

For gv11b:
gfxp_wfi_timeout_count is in usec

Bug 2003668

Change-Id: I68d52ce996a83df90b8b3a8164debb07e5cb370f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599658
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2017-11-29 13:17:18 -08:00
Deepak Nibade
b6b71bd4a8 gpu: nvgpu: fix cleanup path in css_gr_create_client_data()
In css_gr_create_client_data(), we call css_gr_free_client_data() in case
cur->perfmon_start is zero

css_gr_free_client_data() deletes the node from list, and performs some
cleanup if cur->perfmon_start is non-zero

Hence it is incorrect to call css_gr_free_client_data() in clean up path
since node is not added to the list, and cur->perfmon_start is zero anyways

Fix the cleanup path, and remove call to css_gr_free_client_data()

Jira NVGPU-397

Change-Id: I9cb1abf4d6a02716156c9ea2d4a7963e1c92a531
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606977
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-11-29 11:54:14 -08:00
Debarshi Dutta
312f6c2c5f gpu: nvgpu: remove dependency on linux header for sim_gk20a*
This patch removes linux dependencies from sim_gk20a.h under
gk20a/sim_gk20a.h. The following changes are made in this patch.

1) Created a linux based structure sim_gk20a_linux that contains a
common sim_gk20a struct inside it. The common struct sim_gk20a doesn't
contain any linux specific structs.
2) The common struct sim_gk20a contains an added function pointer which
is used to invoke gk20a_sim_esc_readl() method.
3) sim_gk20a.c is moved to nvgpu/common/linux along with a new header
sim_gk20a.h that contains the definition of struct sim_gk20a_linux.
4) struct gk20a now contains a pointer of sim_gk20a instead of the
entire object. The memory for this struct is allocated and  initialized during
gk20a_init_support() and freed during invocation of
gk20_remove_support().
5) We first obtain the pointer for struct sim_gk20a_linux from the
pointer of sim_gk20a using the container_of method in order to work on
the struct.

JIRA NVGPU-386

Change-Id: Ic82b8702642377f82694577a53c3ca0b9c1bb2ab
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603073
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-11-28 22:50:27 -08:00
Deepak Nibade
830d3f10ca gpu: nvgpu: cleanup uapi header includes
With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes
are not needed so remove them

Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common
definition instead

Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in
gp10b/fifo_gp10b.c by defining new common flag
NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API
nvgpu_gpfifo_user_flags_to_common_flags()

Jira NVGPU-363

Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606108
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2017-11-28 09:47:03 -08:00
Deepak Nibade
ce06f74d6b gpu: nvgpu: move cycle state buffer handler to linux
We use dma_buf pointer cyclestate_buffer_handler in common code
But since this is linux specific, we need to move this out of common code and
into linux specific code

Move dma_buf pointer cyclestate_buffer_handler from common channel code to
struct nvgpu_channel_linux

Fix all pointer accesses to this handle

Move gk20a_channel_free_cycle_stats_buffer() to ioctl_channel.c since it is
mostly linux specific
And since gk20a_channel_free_cycle_stats_buffer() needs to be called while
closing the channel, call it from nvgpu_channel_close_linux()

Jira NVGPU-397
Jira NVGPU-415

Change-Id: Ifb429e49b8f7a1c9e2bc757f3efdd50b28ceca1f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603909
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-11-28 09:46:54 -08:00
Deepak Nibade
861b11a968 gpu: nvgpu: move snapshot_client memory handling to linux
We right now store dmabuf fd and dma_buf pointer for gk20a_cs_snapshot_client
But since dma_buf and all related APIs are linux specific, we need to remove
them from common code and move them to linux specific code

Add new linux specific structure gk20a_cs_snapshot_client_linux which includes
struct gk20a_cs_snapshot_client and linux specific dma_buf pointer

In gk20a_attach_cycle_stats_snapshot(), we first handle all dma_buf related
operations and then call gr_gk20a_css_attach()

Move gk20a_channel_free_cycle_stats_snapshot() to ioctl_channel.c
In gk20a_channel_free_cycle_stats_snapshot(), we call gr_gk20a_css_detach()
and then free up dma_buf in linux specific code

We also need to call gk20a_channel_free_cycle_stats_snapshot() while closing
the channel, so call it from linux specific nvgpu_channel_close_linux()

Jira NVGPU-397
Jira NVGPU-415

Change-Id: Ida27240541f6adf31f28d7d7ee4f51651c6d3de2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603908
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-11-28 09:46:50 -08:00
Deepak Nibade
87f42744e0 gpu: nvgpu: initialize gr->max_comptag_mem in linux
We initialize gr->max_comptag_mem in common code and with a global variable
declared in <linux/mm.h>

Move this linux specific dependency to linux specific files i.e.
initialize gr->max_comptag_mem during linux specific probe functions

Jira NVGPU-414

Change-Id: I9415938bf1288b24950ba7ecc71abee3162dae64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606195
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-11-28 09:10:10 -08:00
Konsta Holtta
4f8ba3ad0e gpu: nvgpu: fix fence_from_* retvals
The functions gk20a_fence_from_semaphore and gk20a_fence_from_syncpt
return errno-like codes, so replace two conditions with better-fitting
errors than -1.

Change-Id: Ic9a43cd0365c1eb187e7dc19da14acdd2fbc3f1c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1605563
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2017-11-27 13:44:22 -08:00
Deepak Nibade
c6b9177cff gpu: nvgpu: define error_notifiers in common code
All the linux specific error_notifier codes are defined in linux specific
header file <uapi/linux/nvgpu.h> and used in all the common driver

But since they are defined in linux specific file, we need to move all the
uses of those error_notifiers in linux specific code only

Hence define new error_notifiers in include/nvgpu/error_notifier.h and
use them in the common code

Add new API nvgpu_error_notifier_to_channel_notifier() to convert common
error_notifier of the form NVGPU_ERR_NOTIFIER_* to linux specific error
notifier of the form NVGPU_CHANNEL_*

Any future additions to error notifiers requires update to both the form
of error notifiers

Move all error notifier related metadata from channel_gk20a (common code)
to linux specific structure nvgpu_channel_linux
Update all accesses to this data from new structure instead of channel_gk20a

Move and rename below APIs to linux specific file and declare them
in error_notifier.h
nvgpu_set_error_notifier_locked()
nvgpu_set_error_notifier()
nvgpu_is_error_notifier_set()

Add below new API and use it in fifo_vgpu.c
nvgpu_set_error_notifier_if_empty()

Include <nvgpu/error_notifier.h> wherever new error_notifier codes are used

NVGPU-426

Change-Id: Iaa5bfc150e6e9ec17d797d445c2d6407afe9f4bd
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593361
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2017-11-27 09:23:11 -08:00
Deepak Nibade
5b41eb839a gpu: nvgu: use API to check for valid memory
Use API nvgpu_mem_is_valid() to check if buffers are allocated or not
instead of directly accessing linux specific sg_table

Jira NVGPU-416

Change-Id: I83da79f4a57ec5a765f32c69bf76e708753e11fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1604587
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2017-11-27 04:19:29 -08:00
Konsta Holtta
75ebe51113 gpu: nvgpu: drop num_pts argument in nvgpu_nvhost_sync_create_fence
For nvhost_sync_create_fence, num_pts corresponds to the number of
syncpoints in the array given to it, and the wrapper
nvgpu_nvhost_sync_create_fence only supports one syncpoint at a time.
Use 1 explicitly and make it impossible for the caller of this wrapper
to use something else by mistake.

Change-Id: I2497c1dd4fed0906e3bb07e8f5ddd3a9346cb381
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1604339
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2017-11-27 04:19:26 -08:00
Supriya
6194cfdef5 gpu: nvgpu: split init_falcon_setup_hw
This CL is as part of phased changes to support NO LSPMU
Changes done are to add new pmu ops :
- setup_apertures
- update_lspmu_cmdline_args
These would be called from pmu op init_falcon_setup_hw

JIRA NVGPU-296

Change-Id: Idbcec5c93ca3150df5c9fb81d65b9fce778cecb8
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589004
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2017-11-27 01:49:17 -08:00
Debarshi Dutta
536ec21b56 gpu: nvgpu: remove dependency on linux header for regops_gk20a*
This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.

1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.

JIRA NVGPU-417

Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
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2017-11-23 03:03:36 -08:00
Konsta Holtta
ba2e59dc41 gpu: nvgpu: use submit callback only in linux code
Move the implementation for channel job update callbacks that is based
on Linux specific work_struct usage to Linux-specific code.

This requires a bit of extra work for allocating OS-specific priv data
for channels which is also done in this patch. The priv data will be
used more when more OS-specific features are moved.

Jira NVGPU-259

Change-Id: I24bc0148a827f375b56a1c96044685affc2d1e8c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1589321
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2017-11-22 17:18:56 -08:00