Fix issues related with wrong storage type for
64 bit variables.
(1) Fixed width of HZ_TO_MHZ constant
(2) changed fence_wait timeout to store unsigned
long
bug 200299572
Change-Id: Ie8f2386b738f3aafce75fc2440947e36befac273
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1471611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Write an error to UART on priv ring error. This uncovers any
accesses to missing registers or illegal accesses to registers.
Bug 1846641
Change-Id: Ic1e5ecadcd95777f2b3f7bd77accf98ddce97282
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294683
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
nvgpu is being modularized for kernel-4.4 and newer kernels.
__alloc_fd() can't be used on modules as it is not exported.
So, use a wrapper tegra_fd_alloc() instead of __alloc_fd()
bug 200290850
Change-Id: I0e63307d429774440753698643ba7620c1e1f9f6
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/1469313
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Use struct nvgpu_mem for DMA allocations (and the corresponding
nvgpu_dma_alloc_sys()) instead of custom rolled code. This migrates
away from using linux scatter gather tables directly. Instead this
is hidden in the nvgpu_mem struct. With this change the semaphore.c
code no longer has any direct Linux dependencies.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I92167c98aac9b413ae87496744dcee051cd60207
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464081
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Replace a couple of boolean fields in nvgpu_mem with bits in a
bitmap introduced in an earlier patch.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Iffc31bd629cab9a37e5a4fd13377eb9090353410
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464079
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Move and rename the functions that build sgtables for nvgpu_mems into
the Linux specific DMA code.
One place outside of the Linux code do include the Linux DMA header.
That will be fixed in a subsequent patch.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: Ie43c752b8f998f122af70f7c7eb727af0b0d98df
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464078
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This
includes some functions in allocators that were used only for
debugging.
Remove include of linux/debugfs.h on files that do not deal with
debugfs.
linux/debugfs.h implicitly included linux/fs.h, which we relied on.
Add explicit include of linux/fs.h for all files where this is the
case.
Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467897
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Hide the Linux specific nvgpu_mem fields so that in subsequent patches
core code can instead of using struct sg_table it can use mem_desc.
Routines for accessing system specific fields will be added as needed.
This is the first step in a fairly major overhaul of the GMMU mapping
routines. There are numerous issues with the current design (or lack
there of): massively coupled code, system dependencies, disorganization,
etc.
JIRA NVGPU-12
JIRA NVGPU-30
Change-Id: I2e7d3ae3a07468cfc17c1c642d28ed1b0952474d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1464076
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
FECS trace used hrtimer for sleeping between frames. The resolution
does not need to be that high, and hrtimers are not portable, so
replace the delay with nvpgu_usleep_range().
Bug 200290850
Change-Id: I10fc56fcf6f6d407413384d557ae4bfdfa4239ef
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1465761
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
perfbuf mapping fixes:
- Allocate VM specifically for perfbuf use: using the PMU's
results in mmu faults for larger buffers where 64k pages are used.
- Make 4GB boundary check work for large address spaces
- remove requirement to have allow_all flag set
- track perfbuf ownership and clean up appropriately
Bug 1880196
JIRA EVLR-1074
Change-Id: Ieee4eb17b64acf9b6ede37bf8e6a91892cda4a7e
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: http://git-master/r/1460809
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Copy is_fmodel to struct gk20a at probe time, and access it from
gk20a instead of platform_gk20a.
JIRA NVGPU-16
Change-Id: Ib8d793ea2b02b62da3bfdbb6372d9927658b7ec6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463540
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Add nvgpu_firmware data structure, and return it instead of Linux
struct firmare from nvgpu_request_firmware. Also add abstraction
for releasing firmware: nvgpu_release_firmware.
JIRA NVGPU-16
Change-Id: I6dae8262957c0d4506f710289e3a43a6c1729fc7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463538
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Remove linux list includes <linux/list.h>
and include <nvgpu/list.h> since we now use
nvgpu list APIs instead of linux APIs
Jira NVGPU-13
Change-Id: I59bd433a9bc5c15d4c40e6fe4b18cf44246ba3b2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1462080
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Move Linux driver specific code to common/linux/module.c. This includes
module initialization, power management, and interrupt functions.
Move pci.c, pci.h and nvgpu_common.c under common/linux as they're
Linux only files.
JIRA NVGPU-16
Change-Id: If92b4dd78ebc0c2bbfa9fbca258e9552e4979b4b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1456162
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Monitoring INA3221 is currently missing on some customer designs.
Use PCI vendor/device ids and VBIOS version to identify such device,
and set power_sensor_missing flag. This flag is subsequently used
to skip power device and power policy programming in PMU.
Bug 1903258
Change-Id: Ia6b5ce563b5cc3593e138635639025b830e4535e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1460936
(cherry picked from commit 42f236c210931d28d2699858bb0663b91cf11046)
Reviewed-on: http://git-master/r/1463104
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The debugfs submit profiling stats report the distribution of submit
times at different percentiles. The original code reports the lowest
entry in every percentile-bin as being representative for that
bin. This means that where debugfs reports the 50th percentile, it
actually reports the ~45.001th percentile. This is especially
inconveniant when looking at the 100th percentile, which does not in
fact reflect the maximum.
This patch changes the code to instead report the highest entry in
every percentile-bin.
Change-Id: Ibde3aaf6445e08af09a4a96156f8421cbeb8bae5
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/1461658
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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From Volta onwards, new DSS ZBC registers are
added for ZBC feature and save/restore of new
ZBC reglist is taken care by ctxsw firmware.
Therefore, PMU should save ZBC reglist only
for PRE-volta chips.
JIRA GPUT19X-20
Change-Id: I7d92274208ca42cc77bf57ea3cc416b5ecf32842
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1460244
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uart is littered with gk20a_channel_poll_timeouts prints if nvgpu_dbg_mask
has gpu_dbg_fn bit set. This function is looping every living kernel
so removing this print in order to not keep uart busy printing it.
Change-Id: I0a02f32140573ee088e46bf6869bff7ffcb1a429
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1455081
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For dGPU, instance block is in vidmem, and context_ptr
was not properly computed, leading to reporting pid=0 in
FECS traces.
Use gk20a_mm_inst_block_addr, which handles all cases
to determine instance block physical address.
Bug 1899195
Change-Id: If003d9f00aff66d808e66c06baf6ded38699981a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1461646
(cherry picked from commit 0a58c5ace0)
Reviewed-on: http://git-master/r/1462396
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Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I46b9ccb80e0b67efb86ec85676e5a55ff835c0ec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460113
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
