Split the nvgpu_sgt code out from the nvgpu_mem code. Although the
two chunks of code are related the SGT code is distinct and as
such should be its own unit. To do this a new source file has been
added - nvgpu_sgt.c - which contains all the nvgpu_sgt common APIs.
These are the facade APIs to abstract the actual details of how any
given nvgpu_sgt is actually implemented.
An abstract unit - nvgpu_sgt_os - was also defined. This unit
exists solely for the nvgpu_sgt unit to call so that the OS
specific nvgpu_sgt_os_create_from_mem() API can be moved from the
common nvgpu_sgt unit. Note this also updates the name of what the
OS specific units are expected to call. Common code may still use
the generic nvgpu_sgt_create_from_mem() API.
JIRA NVGPU-1391
Change-Id: I37f5b2bbf9f84c0fb6bc296c3e04ea13518bd4d0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946012
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Some buffers like userd are physically addressed. If nvlink is
enabled, or device is not iommuable, this requires buffer to be
physically contiguous.
Add NVGPU_DMA_PHYSICALLY_ADDRESSED to identify such buffers, in
order to force physically contiguous allocation, only in above
cases.
Bug 2422486
Change-Id: I6426e23b064904e812e6b33e6d706391648a51ae
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
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changes in path because we move the nvhost linux user-interface
from include/linux/ to include/uapi/linux
depends on I2e116dc8f6c33f53c03fb56b923931b6e600b534
Bug 2062672
Change-Id: If2e165852432d5795cf6680cfeb5d4b661fdee74
Signed-off-by: Anuj Gangwar <anujg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1953731
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions. Also set pointer to NULL when freed.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I21ff1ae93ac7b92a71502f97785252c04964e72f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Instead of just the base address of the main register range, store
(also) the base address of usermode area. All regs may not be always
available; on vgpu guests we have only the usermode regs.
Store the usermode addr we get from a platform resource directly in
gv11b_vgpu_probe() for vgpu. In that case the main reg addr is unset.
The base address is computed in gk20a_pm_finalize_poweron() for native
environments; when the reg addr is read from a resource, the chip is
still unknown and as such the HAL op for reading the usermode base
offset is unavailable.
Bug 200145225
Bug 200467197
Change-Id: I8855bb54a6456eb63b69559c84398f7eeaec3513
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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Enable the unified address space config for
o gp10b
o gv11b
gm20b is suffering from a problem in a T214 MODS test. This should
work for the time being in more recent chips. Also this will
increase the soak time these changes get before being released.
Other chips (vGPUs, dGPUs) will (possibly) be enabled at a later
date.
Bug 200105199
Change-Id: I03a6803c6369d89e8a318886fc642b55c5538dd9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1951858
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Currently has_timedout variable is protected by wmb at places
where it is being set and there is no correspoding rmb whenever
has_timedout variable is read. This is prone to errors for
concurrent execution. This change is supposed to fix this issue.
Rename has_timedout variable of channel struct to ch_timedout.
Also to avoid rmb every time ch_timedout is read,
ch_timedout_spinlock is added to protect ch_timedout
variable for taking care of concurrent execution.
Bug 2404865
Bug 2092051
Change-Id: I0bee9f50af0a48720aa8b54cbc3af97ef9f6df00
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the prototype parameter.
JIRA NVGPU-847
Change-Id: I980ca7ba8adc853de9c1b6f6c7e7b3e4ac12f88e
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1926980
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Add a flag to nvgpu_gpu_characteristics to expose FECS tracing capability to
userspace.
This is required for adding nvrm_gpu APIs for CTXSW set of IOCTLs which were
requested in several bugs.
nvrm_gpu APIs would query this flag to check the availability of IOCTLs.
Bug 2169678
Bug 2169677
Bug 2169675
Bug 2169674
Bug 2169673
Bug 2168342
Change-Id: Ie6ba80a4144637546b97fa93baae67b8d0c4d425
Signed-off-by: Anup Mahindre <amahindre@nvidia.com>
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs
to qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
While linux os code does not need to be MISRA-compliant this
change switches over all memcpy() uses to nvgpu_memcpy()
with appropriate casts applied to maintain consistency within
the nvgpu source base.
JIRA NVGPU-849
Change-Id: I2c21a7845df5709dafa19508c121f8afa27cc4fc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950995
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gk20a.h depends on definition of struct pmgr_pmupstate. Change that
to a pointer and use forward declaration, and allocation and
free functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: I7ced14d6629e033b0ccef3a93a3dbf099e43ba4c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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gk20a.h depends on definition of struct clk_pmupstate. Change that
to a pointer and use forward declaration, and allocation and free
functions.
Fix a few build breaks by adding explicit includes where previously
a header file had gotten included implicitly.
JIRA NVGPU-596
Change-Id: Iafe7d72a6fd31543653e0e10e2d2e552b6c3514b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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clk_gp106.h and clk_gv100.h define conflicting symbols, which prevent
including them both at the same time. One of the conflicting structs
is namemap_cfg, which has different definitions in clk_gp106.h and
include/nvgpu/clk.h.
Move all constants used only by clk_*.c to be defined there, delete
the extra namemap_cfg structure definition, and modify code to cope
with the unified namemap_cfg.
JIRa NVGPU-596
Change-Id: Id68919da4567ec1507eda0cfaa19bf047a7bfc59
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1945285
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The gk20a struct was not zero'ed out which could cause some
unexpected crashes, especially when NVGPU code is checking if
a function pointer is not NULL to decide to run the corresponding
function.
JIRA NVGPU-1246
Change-Id: I1a32c871fce59d6bf4729187af1b670c763a631a
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1946761
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Add support for backtrace prints when BUG() is being called.
To support backtrace calls, the -rdynamic compiler flag is
now being used. On host, it fully works as expected, on
target only exported symbols (in libnvgpu-drv.export) are
visible.
JIRA NVGPU-1246
Change-Id: Ia075ac99228e8377bdb3142fef2e56c2fea2d967
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943478
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Ifb8cb992a5cb9b04440f162918a8ed2ae17ec928
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822587
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gk20a.c is used only in Linux build. It's in theory common code, but
in practice implements OS specific policies. Also implement
os/posix/gk20a.c to implement gk20a_init_gpu_characteristics(),
gk20a_get() and gk20a_put() which are called from common code.
JIRA NVGPU-596
Change-Id: I6a6079ca6d4c6a225f0dd0e1cd7c439333a704bf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This adds the initial unit test for the fuse module and testing for
gp10b. It verifies the exposed APIs for this device in the fuse module.
To allow the hal_init to pass before the HAL for
read_gcplex_config_fuse() can be overridden, the default behavior of the
POSIX implementation for nvgpu_tegra_fuse_read_gcplex_config_fuse() is
changed.
This provides 100% code and branch coverage for this unit/device.
JIRA NVGPU-938
Change-Id: I9efa8080c12ace637581c77aa35aab3f86a94760
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
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Update the debug crash dump to be clearer, more concise and
avoid many of the misformatting issues that have crept in over
the last couple years.
This also changes the debug prints to move from pr_err() in
the Linux kernel to nvgpu_err(). This makes it easier to
filter all nvgpu messages in a log file with a single grep
command.
Change-Id: I00ca9e6c32da7a79c8f6903a139bf6b43e89618a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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Originally the order for output was:
1. Dump platform deps (sync-points/host1x stuff)
2. Dump PBDMA status
3. Dump engine status
4. Dump channel status
The updated ordering is:
1. Dump channel status
2. Dump PBDMA status
3. Dump engine status
4. Dump platform deps (sync-points/host1x stuff)
The purpose of this is to put the useful information first and
relegate the less useful info to later in the dump. We naturally
scan downwards and treat stuff at the top as most important.
The end goal is to make the debug dump as useful in as little
time as possible. So instead of making an engineer dig through
a complex jumble of information to find the useful stuff the
hope is that the useful stuff is immediately available.
Change-Id: I9d2b755676b7e5dc2f8949f14dc36f3d337e2a3f
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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This function returns a boolean describing if a given log
mask is enabled for a given GPU. Previously this returned
and int but the bool type is far better suited for this.
Also implement this function in posix, as it may be useful
to have implemented there if any common code chooses to
use this function.
Change-Id: I7382e73df83282763df1bdbccbbb219c9f3e6f1b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938341
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
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Add a fifo HAL for querying the doorbell token of a specific channel and
call it instead of doing the calculation directly. For Volta the token
is just the channel id plus the possible base number.
Bug 200145225
Change-Id: Ifbb150191575fdc72e413a14c799cab7e52d8c14
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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MISRA Rule-15.6 requires that all if-else blocks and loop blocks
be enclosed in braces, including single statement blocks. Fix errors
due to single statement if-else and loop blocks without braces
by introducing the braces.
JIRA NVGPU-775
Change-Id: Ib70621d39735abae3fd2eb7ccf77f36125e2d7b7
Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928745
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Posix interface.
JIRA NVGPU-1036
Change-Id: I2da417edc992f16de24cdff536c0538f1fde8b61
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929901
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in OS/Linux interface.
JIRA NVGPU-1036
Change-Id: I39b20f1d0e1a1da56d452f2c3d5ee049666cefe8
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929900
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MISRA rule 10.4 doesn't allow arithmetic conversions on operands of
different essential type category.
Fix violations where an arithmetic conversion is performed on boolean
and non-boolean types.
JIRA NVGPU-994
Change-Id: I2af9937678462b632bb6ec6178e10d02104fc3bc
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
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Import userd and gpfifo buffers from userspace if provided via
NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX. Also supply the work submit token
(i.e., the hw channel id) to userspace.
To keep the buffers alive, store their dmabuf and attachment/sgt handles
in nvgpu_channel_linux. Our nvgpu_mem doesn't provide such data for
buffers that are mainly in kernel use. The buffers are freed via a new
API in the os_channel interface.
Fix a bug in gk20a_channel_free_usermode_buffers: also unmap the
usermode gpfifo buffer.
Bug 200145225
Change-Id: I8416af7085c91b044ac8ccd9faa38e2a6d0c3946
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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Add a mmap callback on the control device node for mapping the usermode
register region to userspace. Each such mapping is removed when the GPU
railgates, and brought back again on unrailgate.
The mapping offset must be 0 and its size must be 4 KB.
Bug 200145225
Change-Id: Ie8d3758da745b958376292691d7d1d02a24e7815
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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Usermode submit needs to access the usermode region of registers from
userspace. Store the start address of register resource in struct
nvgpu_os_linux to be used in remap to userspace.
Bug 200145225
Change-Id: I3796b6bf67942af0cc16c86accb82a013032bfc8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
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This fixes a bug where the POSIX dma module was calling malloc for
dma allocation requests with the incorrect size.
Bug found as a result of JIRA NVGPU-1235
Change-Id: Ia2933dc90f12d84a7da91a50eb3eafd6eb0e129e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1930799
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