MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for all 17.7 violations instandard C functions
in power-related files.
JIRA NVGPU-1036
Change-Id: I6b9f2fa6f3cbf5f746a0e8499d3e8962d4781fe3
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1929905
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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-On Turing, LS PMU RTOS is bootstrapped by SEC2 RTOS,
so PMU needs some time to boot & get ready to process
request as boot happened bit late in flow.
-So issue here is, code execution reaches function
gk20a_init_pstate_pmu_support() to send boardobj
commands to PMU before PMU ready to accept.
-As a result, this cause command request failure
as PMU is not ready yet due to falcon clock is
slower compared CPU clock.
-To fix issue, waiting for pmu_ready flag to become
true before staring PSTATE requests to PMU.
-pmu_ready flag will be set to true as soon as
INIT message received from PMU RTOS.
-Pre Turing-PMU RTOS will be ready much ahead of
reaching this point.
JIRA NVGPU-1150
Change-Id: I4fb5d4ca6dabc22fac34ae32880d7a1f3164e1b7
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925240
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MISRA rule-14.4 doesn't allow the usage of function pointers & integer
types as booleans in the controlling expression of an if statement or
an iteration statement.
Fix violations where a function pointer or a function whose return
value is an integer, is used as a boolean in the controlling expression
of if and loop statements.
JIRA NVGPU-1021
Change-Id: Ic5336268394ba4396ce80744c25930d2fb44dc42
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932147
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: I8c9ad786a741b78293d0ebc4e1c33d4d0fc8f9b4
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921260
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move all files under perf/* to pmu_perf/* since pmu_perf is logically
appropriate name for PMU's perf unit
Rename perf.c to pmu_perf.c
Also rename the HAL from gops.perf to gops.pmu_perf
Jira NVGPU-1102
Change-Id: I79e73b8b102ddf6b49783c2f38d861cd43b0b4c6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1819301
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This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.
JIRA NVGPU-647
Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810743
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Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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- Created volt ops under pmu_ver to support volt_set_voltage,
volt_get_voltage & volt_send_load_cmd_to_pmu.
- Renamed volt load, set_voltage & get_voltage gp10x method names.
- Added new volt load, set_voltage & get_voltage methods for gv10x
using RPC & added code to handle ack in pmu_rpc_handler() along
with struct rail_list changes.
- Updated volt ops of gp106 & gv100 to point to respective methods.
- Added member volt_dev_idx_ipc_vmin & volt_scale_exp_pwr_equ_idx to
"struct nv_pmu_volt_volt_rail_boardobj_set" & "struct voltage_rail"
made changes to update members as needed.
- Added member volt_scale_exp_pwr_equ_idx to
"struct vbios_voltage_rail_table_1x_entry" to read
value from VBIOS table & update rail boardobj set interface.
- Defines for volt RPC "NV_PMU_RPC_ID_VOLT_*"
- Define struct's volt load, set_voltage & get_voltage to execute
volt RPC.
Change-Id: I4a41adcf7536468beaa8a73f551b1d608aabd161
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1659728
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Fix below sparse warnings by making function
static or including right header:
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c:45:6: warning: symbol 'gp10b_init_fecs_trace_ops' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp106/hal_gp106.c:195:5: warning: symbol 'gp106_init_gpu_characteristics' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pstate/pstate.c:175:5: warning: symbol 'pstate_construct_super' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pstate/pstate.c:195:5: warning: symbol 'pstate_construct_3x' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pstate/pstate.c:204:15: warning: symbol 'pstate_construct' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pstate/pstate.c:218:5: warning: symbol 'pstate_insert' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/clk/clk_arb.c:1457:6: warning: symbol 'nvgpu_clk_arb_ioctl_event_dev' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pmgr/pmgr.c:68:5: warning: symbol 'pmgr_pwr_devices_get_power_u64' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pmgr/pmgr.c:80:5: warning: symbol 'pmgr_pwr_devices_get_current_u64' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/pmgr/pmgr.c:92:5: warning: symbol 'pmgr_pwr_devices_get_voltage_u64' was not declared. Should it be static?
Bug 200299572
Change-Id: I0112ba3af5b858d2ce2a37a8366dcb6be1eb688d
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/1482866
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gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: Ic3e6d7780ce62ccd87ff4759ac8ae6c3627199a0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457349
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
- check return value of nvgpu_mutex_init in pstate.c
- add new callback gk20a_deinit_pstate_support() to
deinitialize pstate support
- add corresponding nvgpu_mutex_destroy calls
Jira NVGPU-13
Change-Id: I206bf2324e8fe95f4ed52c29ac5d8981327632b2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1321296
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Instead of using Linux APIs for mutex and spinlocks
directly, use new APIs defined in <nvgpu/lock.h>
Replace Linux specific mutex/spinlock declaration,
init, lock, unlock APIs with new APIs
e.g
struct mutex is replaced by struct nvgpu_mutex and
mutex_lock() is replaced by nvgpu_mutex_acquire()
And also include <nvgpu/lock.h> instead of including
<linux/mutex.h> and <linux/spinlock.h>
Add explicit nvgpu/lock.h includes to below
files to fix complilation failures.
gk20a/platform_gk20a.h
include/nvgpu/allocator.h
Jira NVGPU-13
Change-Id: I81a05d21ecdbd90c2076a9f0aefd0e40b215bd33
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1293187
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Most of BIOS parsing code is not specific to any particular GPU. Move
most of the code to generic files, and leave only chip specific parts
dealing with microcontroller boot into chip specific files.
As most of the parsing is generic, they do not need to be called via
HALs so remove the HALs and change the calls into direct function
calls.
All definitions meant to be used outside BIOS code itself are now in
<nvgpu/bios.h>
Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1302222
GVS: Gerrit_Virtual_Submit
- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
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JIRA DNVGPU-170
1) Add clock frequency controller VBIOS structure definitions
2) Parse VBIOS tables and build boardobj structures for clock frequency
controller.
3) send clock frequency controller data structures to PMU
4) implement public function to send load/unload command to pmu
to enable/disable clock frequency controller support
Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1248209
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07)
Reviewed-on: http://git-master/r/1270897
GVS: Gerrit_Virtual_Submit
Modification of the arbiter to remove all locking
from the arbiter callback and move the callbacks
out of the global queue
Adding modification to call for updated values of
vf table from arbiter init function and on
vf table update
JIRA: DNVGPU-170
Change-Id: I7a7d34c0590522901e06356c06fd8114ebf10f37
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1243212
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1268009
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
JIRA DNVGPU-143
The arbiter is charged with selecting the proper
frequencies when multiple applications submit
simultaneously clock change requests
On the current implementation, the arbiter guarantees
that the selected frequency will be always higher
or equal to the request, as long as the request is
in range.
The current code is not yet realtime friendly, as
requests are not pre-allocated.
Summary of changes:
(1) pstate/vf switch no longer selects boot frequency
(2) changed mclk code change to accept input freq
(3) added arbiter
(4) now a single session can submit concurrent requests
the last request is the one that applies for that
session
(5) modified locking mechanism to reduce lock contention
(6) Added callback to notify the arbiter that the VF
table has changed and is no longer valid (PMU/Thermals
must call this when VF table is invalid)
(7) changed internal API to work with MHz
(8) added debugfs for stats
Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239461
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267120
Reviewed-by: Automatic_Commit_Validation_User
Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.
Jira DNVGPU-125
Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
- Read voltage tables from VBIOS & construct
then send to PMU.
- compare & set voltage based on
mclk/gpc2clk clk, take higher voltage
between two & set.
JIRA DNVGPU-122
Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1224365
(cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c)
Reviewed-on: http://git-master/r/1244657
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This CL covers the following implementation,
1) Power Sensor Table parsing.
2) Power Topology Table parsing.
3) Add debugfs interface to get the current power(mW), current(mA) and
voltage(uV) information from PMU.
4) Power Policy Table Parsing
5) Implement PMU boardobj interface for pmgr module.
6) Over current protection.
JIRA DNVGPU-47
Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1217189
(cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6)
Reviewed-on: http://git-master/r/1241953
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
JIRA DNVGPU-123
now a function can be called with GPC2CLK value
It will take care calculating slave clock values
and calling VF inject to program clock
Made programming of boot clock code to use this
newly created function.
Change-Id: I74de7e9d98e379e94175ed2d9745ce3ab6c70691
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1221976
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1235056
JIRA DNVGPU-123
function was added to retrieve V for F or
F for V for a given clock domain.
Clock domain can be master or slave.
F or V can be intermediate point between two
successive V or F values in VF table.
VF table should be cached before calling this function.
A F value below Fmin will return Vmin.
F > Fmax will return error
A V value above Vmax wil return F max.
A V value below Vmin will return error.
Change-Id: I28b4e8647510c6933e9e1204cfff31d74616e11a
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1211234
(cherry-picked from commit 5b83b03f2454fbec8d49a064ed09b09c92d3e9fa)
Reviewed-on: http://git-master/r/1235054
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
