MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for gm20b.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I0c8b3f04c943a1cea23ce3f678ebb915e8a5a5da
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971166
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MISRA rule 16.3 states all switch clause to have break statement.
Fixing the missing break statement for default case.
Two consecutive labels without statement need not have break.
So no break is added for case without any statement.
This also makes the switch statement well-formed covering 16.1.
JIRA NVGPU-1510
JIRA NVGPU-1536
Change-Id: I2c16888cbcb429f49f1f260e18b7c6eba55aa83c
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1964328
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violations where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I2e7ad84751aa8b7e55946bb1f7e15e4af4cbf245
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1827823
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the result of a bitwise operation is used as a
boolean in the controlling expression of if and loop statements.
JIRA NVGPU-1020
Change-Id: I6a756ee1bbb45d43f424d2251eebbc26278db417
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1936334
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I61a2d24830428ffc2655bd9c45bb5403c7f22c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1943058
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MISRA rule 14.4 doesn't allow the usage of non-boolean variable as
boolean in the controlling expression of an if statement or an
iteration statement.
Fix violations where a non-boolean variable is used as a boolean in the
controlling expression of if and loop statements.
JIRA NVGPU-1022
Change-Id: I957f8ca1fa0eb00928c476960da1e6e420781c09
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1941002
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MISRA rule 14.4 doesn't allow the usage of integer types as booleans
in the controlling expression of an if statement or an iteration
statement.
Fix violations where the integer variables err, ret, status are used
as booleans in the controlling expression of if and loop statements.
JIRA NVGPU-1019
Change-Id: Ia2ec5f1db3c7a1884efe5ba7b8b4d9ebbd021734
Signed-off-by: Amurthyreddy <amurthyreddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1921373
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MISRA Rule-17.7 requires the return value of all functions to be used.
Fix is either to use the return value or change the function to return
void. This patch contains fix for calls to nvgpu_readl.
JIRA NVGPU-677
Change-Id: I432197cca67a10281dfe407aa9ce2dd8120030f0
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807528
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GM20B GPCPLL registers are accessed via sys address space with the
exception of the last dvfs2 register that can be accessed only through
bcast address. However, in debugfs loop dvfs2 sys address should be
used as loop terminator; otherwise, loop body is never executed, and
GPCPLL registers debugfs node is broken. Fixed it in this commit.
Change-Id: Ifea839757fda7d97b2c9238178227ab198526ab0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808784
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In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h
JIRA NVGPU-597
Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
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Before passing in an unsigned value to abs() cast the result
of the subtraction to signed.
In Linux this happens automatically but on non-Linux platforms
abs() does not necessarily do this. clang flags this case as
a pointless operation: abs(x) obviously must equal x for any
unsigned x.
This change should hopefully preserve the Linux behavior but
avoid the compiler warning from clang.
JIRA NVGPU-525
Change-Id: I71320964c0922f1e4890c8b25d801f17e54ed3c0
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724093
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
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Currently gpu sysfs retrieves Fmax@Vmin by direct call into Tegra DVFS
driver that introduces compile time dependencies on CONFIG_TEGRA_DVFS.
In addition incorrect clock is used for DVFS information access.
Re-factored sysfs node to use generic GPU clock operation for Fmax@Vmin
read. This would fix a bug in target clock selection, and allows to
remove dependency of sysfs on CONFIG_TEGRA_DVFS.
Updated nvgpu_linux_get_fmax_at_vmin_safe operation itself so it can be
called on platforms that does not support Tegra DVFS, although 0 will
still be returned as Fmax@Vmin on such platforms.
Bug 2045903
Change-Id: I32cce25320df026288c82458c913b0cde9ad4f72
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1710924
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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Switching GPU clock in/out of bypass concurrently with h/w thermal
throttling may result in unpredictable/unstable clock output from GPU
linear divider. Hence, made sure thermal throttling is disabled before
bypass entry, and enabled after bypass exit.
Bug 1893467
Change-Id: Ia919c599eeb0115e11a34370aea3982aa935db2f
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1677022
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Modify HAL clk->get_maxfreq() signature to match the one in
clk->set_rate() and clk->get_rate(). It allows support of multiple
clocks.
Implement clk.get_maxfreq operation for vgpu and use it to
fill max_freq field in GPU characteristics query.
JIRA NVGPU-388
Change-Id: I93bfc2aa76e38b8a5e0ac55d87c4e26df6fea77f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1597329
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GM20B GPCPLL dvfs register cannot be accessed through sys registers
bank (as other PLL registers), instead bcast bank must be used. This
limitation was already taken into account for production access, but
dbugfs access has incorrectly used sys bank. Fixed bank access in
this commit.
Change-Id: Ic7ca640c586addea3aaae4f10a98af8497d6f3cb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1504241
Reviewed-on: https://git-master.nvidia.com/r/1543854
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Add a pointer to struct gk20a to the FUSE APIs. This helps
QNX builds avoid any static data definitions.
Also this change plumbs struct gk20a in some of the Linux clk
code and fixes a few minor style nits.
Change-Id: I27dfb2c4e9a352f784d6cead150460d8e9e808d3
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537611
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Reviewed-by: Richard Zhao <rizhao@nvidia.com>
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Reviewed-by: Sourab Gupta <sourabg@nvidia.com>
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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the clk
and clk_arb sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I553353df836b187b8eac61e16b63080b570c96b8
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1511076
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Applied dfs_det_cal field mask when updating DFS external calibration
setting to prevent overflow for negative setting (not happening so far
with ADC offset always below Vmin, but may be needed if/when ADC fusing
changes).
Change-Id: I94b415edec84111b957b73ccfc80c1a8640b8e3a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1504242
(cherry picked from commit 9b8072ffcc02f6684a56609c25d1d77ed0852f7a)
Reviewed-on: https://git-master.nvidia.com/r/1525831
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Enabled GM20B GPCPLL revision C1 during internal calibration in order
to read calibration status and results.
Bug 1942225
Change-Id: I8fb5f43669bb308de7439792033f640d26f8a3dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1504228
(cherry picked from commit a5bed86858fe0e28482bea1a57ecd3085f146ad1)
Reviewed-on: https://git-master/r/1511085
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Reviewed-by: Samuel Payne <spayne@nvidia.com>
Tested-by: Samuel Payne <spayne@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Remove <soc/tegra/fuse.h> includes and include
<nvgpu/fuse.h> header to remove direct dependency
on platform specific header
Use specific APIs like below to read/write fuses
nvgpu_tegra_fuse_write_bypass()
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable()
Remove old code which was compiled for kernel versions
less than 4.4 since we support only k4.4 and greater
versions now
Jira NVGPU-75
Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497518
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Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Move debugfs code from clk_gm20b.c to file in Linux module
common/linux/debug_clk.c
This file will be compiled only if CONFIG_DEBUG_FS is set
Define below new HAL APIs for various clock operations
which can be accessed from debug file
init_debugfs()
get_voltage()
get_gpcclk_clock_counter()
pll_reg_write()
get_pll_debug_data()
Export nvgpu_pl_to_div() and nvgpu_div_to_pl() so
that these can be accessed from debug_clk.c
Add new structure nvgpu_clk_pll_debug_data so that
all required register values for debugging can be
made available in debug_clk.c
Add new API gm20b_get_gpc_pll_parms() so that statically
defined variable can be accessed in debug_clk.c too
Remove global variable dvfs_safe_max_freq and add
it to struct clk_gk20a so that it can accessed
from both clk_gm20b.c and debug_clk.c
Jira NVGPU-62
Change-Id: I3ae70b40235e78141a686686930e1f178ad59453
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1488903
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
clk/clk_common.c includes some linux specific clock
calls which can be easily replaced
Move linux specific call to platform file
Rest of the APIs are removed by directly substituting
API code into caller function
Jira NVGPU-49
Change-Id: Ia70e7a65c877649699b5d064683c34c0cb696d2e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483862
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Use common fuse APIs in clk_gm20b.c
Include <nvgpu/fuse.h> in clk_gm20b.c and remove
tegra specific include <soc/tegra/fuse.h>
Jira NVGPU-49
Jira NVGPU-75
Change-Id: I3e89ee7fc20d67fc26ee289e35a68560ff442ada
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483861
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Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
clk_gm20b.c has number of calls specific to linux and
tegra-soc environment
In order to unify the driver, move all of those calls
to tegra/linux specific file tegra/linux/clk.c
All the clk_*() and tegra_dvfs_*() calls are now
abstracted behind GPU's clock operations and shoule be
accessed using g->ops.clk.<API> format
Remove <linux/clk.h> and <soc/tegra/tegra-dvfs.h> from
clk_gm20b.c
Remove <linux/version.h> from clk_gm20b.c too since
we only support k4.4 and higher version only
Jira NVGPU-49
Change-Id: Ib26811e0423bbd3868b9a46e662b80a8ca088dc5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483092
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We currently register gm20b clock operations gm20b_clk_ops
in function gm20b_register_gpcclk() which is in clk_gm20b.c
Since this is common clock framework and hence linux dependency,
move this clock registration to platform specific file
Note that all the clock operations remain in clk_gm20b.c.
APIs in platform file will eventually call operations
in clk_gm20b.c
Jira NVGPU-49
Change-Id: Ib0b0d9f4719b196d764825a7dddb08f1fbd7a567
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1483091
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Remove gk20a_platform dependencies from gk20a.h. This makes
gk20a_platform a Linux platform specific data structure. Add #include
for platform_gk20a.h in the source files that still depend on Linux.
JIRA NVGPU-16
Change-Id: Ib098accd34a1f5066eb8680c387f9b178169f3f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463547
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Added GPCPLL poweron voltage field to GPU clock structure. Initialized
it differently for GPCPLL revisions B1 and C1.
Bug 1924194
Change-Id: Ide7a08445afd3ab9aea21f75871b750f45c02c99
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1481263
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Put all debugfs dependencies inside #ifdef CONFIG_DEBUG_FS. This
includes some functions in allocators that were used only for
debugging.
Remove include of linux/debugfs.h on files that do not deal with
debugfs.
linux/debugfs.h implicitly included linux/fs.h, which we relied on.
Add explicit include of linux/fs.h for all files where this is the
case.
Change-Id: I16feffae6b0e3a2edf366075cdc01ade86be06f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1467897
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Separated parameters for GM20B GPC PLL revisions B1 (default), and C1
(new, not characterized, yet). For now, used C1 spec settings.
Skipped PL divider glitch WAR, since revision C1 is glitchless.
Bug 1851797
Bug 1867980
Change-Id: I12dc101d002a41230e9323c47af234f6bae8e034
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1461680
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Use platform agnostic delay functions instead of Linux kernel APIs.
This allows removing dependency to Linux header linux/delay.h. At the
same time remove #include lines for other unused Linux headers.
JIRA NVGPU-16
Change-Id: I05df9d72edaf4bb061febe0cb40fc8a7cf9f51c7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1460114
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Add nvgpu_* wrappers for determining if we're running in simulation
or silicon, and if we're running in hypervisor.
The new wrappers require struct gk20a pointer, and gk20a_fence_wait()
did not have access to one. Add struct gk20a pointer as the first
parameter.
JIRA NVGPU-16
Change-Id: I73b2b8f091ca29fb1827054abd2adaf583710331
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1331565
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