In gr_gv11b_set_gpc_tpc_mask(), we calculate tpc_count_mask based on
number of TPCs
But since we could change number of TPCs runtime, we would end up
calulating incorrect tpc_count_mask
Hence instead of calculating tpc_count_mask, just hard code it to
width of fuse register i.e. hard code tpc_count_mask to 4-bit value
Bug 2031635
Change-Id: Ia6f74d39d066775a5d133897305554df1e54157e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617917
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
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Convert tpc number from pes-aware to non-pes-aware
number. tpc id is converted to one that is numbered
in order starting from the active tpcs within PES0
followed by the active tpcs in subsequent PESs.
Bug 1842197
Change-Id: I18d4b20ee4998e5a2ca5439793fe2479b4326c1a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1615419
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gr_gv11b_init_fs_state() calls gr_gm20b_init_fs_state() which
disables vdc_4to2. This should no longer be done on gv11b, so
instead of calling gr_gm20b_init_fs_state() copy the relevant
lines to gr_gv11b_init_fs_state() and drop vdc_4to2 disable.
gv11b_ltc_init_fs_state() also disables it to match the state.
Remove that disable, too.
Change-Id: I3a3fd87a3e8836e495cb818570c971b3d29a6dd1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1619966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Wei Sun <wsun@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Check the availability of ecc units by checking
relevant ecc fuse and fuse overrides.
During gpu boot, initialize ecc units by scrubbing
individual ecc units available. ECC initialization
should be done before gr initialization.
Following ecc units are scrubbed:
SM LRF
SM L1 DATA
SM L1 TAG
SM CBU
SM ICACHE
Bug 200339497
Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1612734
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Pre-gv11b we only had 2 TPCs in a GPC. But on gv11b we have 4 TPCs in a GPC.
Hence update gr_gv11b_set_gpc_tpc_mask() as per new configuration and allow
setting bits based on number of TPCs
Bug 2031635
Change-Id: I44f5f6ce5f3e2501c229c9fcda36fb330ebf8bd0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614044
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For gv11b, configured gfx preemption wfi timeout in usec.
Set timeout unit as usec in gr_gv11b_init_preemption_state.
Used default timeout as 1msec and this timeout value can
be modified through sysfs node:
/sys/devices/gpu.0/gfxp_wfi_timeout_count
For gp10b:
gfxp_wfi_timeout_count is in syclk cycles
For gv11b:
gfxp_wfi_timeout_count is in usec
Bug 2003668
Change-Id: I68d52ce996a83df90b8b3a8164debb07e5cb370f
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599658
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Remove all linux and soc specific includes from common source file gr_gv11b.c
Use common nvgpu_usleep_range() instead of linux specific usleep_range()
Remove redundant kernel version checks pertaining to unsupported kernel versions
Use nvgpu_tegra_fuse_*() APIs instead of soc specific APIs
Jira NVGPU-405
Change-Id: I6f1602c6ab9f61046d68d3c465eb23873910960d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606980
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
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With recent rework in nvgpu most of the <uapi/linux/nvgpu.h> includes
are not needed so remove them
Remove use of NVGPU_DBG_GPU_REG_OP_* in gk20a/gr_gk20a.c and use common
definition instead
Remove use of NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE in
gp10b/fifo_gp10b.c by defining new common flag
NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE and then parsing it in API
nvgpu_gpfifo_user_flags_to_common_flags()
Jira NVGPU-363
Change-Id: I8e653275ea3f443f24be7284d54f2115636aba3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1606108
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This patch removes the dependency on the header file "uapi/linux/nvgpu.h"
for regops_gk20a.c. The original structure and definitions in the
uapi/linux/nvgpu.h is maintained for userspace libnvrm_gpu.h. The
following changes are made in this patch.
1) Defined common versions of the NVGPU_DBG_GPU_REG_OP* definitions inside
regops_gk20a.h.
2) Defined common version of struct nvgpu_dbg_gpu_reg_op inside
regops_gk20a.h naming it struct nvgpu_dbg_reg_op.
3) Constructed APIs to convert the NVGPU_DBG_GPU_REG_OP* definitions from
linux versions to common and vice versa.
4) Constructed APIs to convert from struct nvgpu_dbg_gpu_reg_op to
struct nvgpu_dbg_reg_op and vice versa.
5) The ioctl handler nvgpu_ioctl_channel_reg_ops first copies from
userspace into a local storage based on struct nvgpu_dbg_gpu_reg_op which
is copied into the struct nvgpu_dbg_reg_op using the APIs above and
after executing the regops handler passes the data back into userspace
by copying back data from struct nvgpu_dbg_reg_op to struct
nvgpu_dbg_gpu_reg_opi.
JIRA NVGPU-417
Change-Id: I23bad48d2967a629a6308c7484f3741a89db6537
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1596972
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Add a translation layer to convert from the NVGPU_AS_* flags to
to new set of NVGPU_VM_MAP_* and NVGPU_VM_AREA_ALLOC_* flags.
This allows the common MM code to not depend on the UAPI header
defined for Linux.
In addition to this change a couple of other small changes were
made:
1. Deprecate, print a warning, and ignore usage of the
NVGPU_AS_MAP_BUFFER_FLAGS_MAPPABLE_COMPBITS flag.
2. Move the t19x IO coherence flag from the t19x UAPI header
to the regular UAPI header.
JIRA NVGPU-293
Change-Id: I146402b0e8617294374e63e78f8826c57cd3b291
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1599802
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- in the native case, replace calls for init_cyclestats with
the gm20b version, as each chip had identical versions of the code.
- in the virtual case, use the vgpu version of the function in order
to get the new max_css_buffer_size characteristic set to the mempool
size.
JIRA ESRM-54
Bug 200296210
Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578934
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For SCG to work, smid numbering needs to be done
based on scg performance of tpcs. For gv11b and
gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table"
to do this.
Used local variable "index" to avoid multiple computations in
the function: gr_gv100_init_sm_id_table
index = sm_id + sm
Add deug info for printing initialized gpc/tpc/sm/global_tpc
indexs.
Bug 1842197
Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583916
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For pre-silicon platforms, clock gating
should be skipped as it is not supported.
Added new flags "can_"x"lcg" to check platform
capability before programming SLCG,BLCG and ELCG.
Bug 200314250
Change-Id: Iec7564b00b988cdd50a02f3130662727839c5047
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566251
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Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I8feaa95a9830969221f7ac70a5ef61cdf25094c3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542988
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Number of sm is being reported incorrectly. This is because
we are not taking into account that each TPC have 2 sm.
Bug 1951026
Change-Id: I7c666aa2a0470a14aad29ab1a80ae9d23958a743
Signed-off-by: Sandarbh Jain <sanjain@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527771
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Tested-by: Alexander Lewkowicz <alewkowicz@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_PRIVSECURITY
Jira NVGPU-74
Change-Id: I4c11e3a89a76abe137cf61b69ad0fbcd665554b7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525714
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
- Created HAL to configure gpc mmu unit for gv11b.
- Earlier chips needs writes to NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS
register to know supported number of LTCS by reading NUM_ACTIVE_LTCS
but gv11b support auto update from fuse upon reset, so skipped
LTCS update for GPCS & skipping helps to fix compression failure
issue.
Bug 1950234
Change-Id: I628af7d1399e4fe3126895e3a703a19147f7a12f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1517733
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
The new SET_BES_CROP_DEBUG3 sw method is used to flip two fields
in the NV_PGRAPH_PRI_BES_CROP_DEBUG3 register. The sw method is
used by the user space driver to disable enough ROP optimizations
to maintain ZBC state of target tiles.
Bug 1942454
Change-Id: I3109fb4120674b15db4998693d0aa65bf0c3c8b5
Signed-off-by: Lauri Peltonen <lpeltonen@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1516205
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
gr_gk20a_handle_sm_exception is initialized to
handle_sm_exception and new gr ops handle_tpc_sm_ecc_exception
is initialized to gr_gv11b_handle_tpc_sm_ecc_exception
to handle sm ecc errors per tpc.
JIRA GPUT19X-75
JIRA GPUT19X-109
Change-Id: Iefa95b185b9eed23f9f54e231405fcd9fd83ccc0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514039
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
