In order to maintain separate mappings of GR TSG and global context
buffers for different subcontexts, we need to separate the memory
struct and the mapping struct for the buffers. This patch moves
the mappings of all GR ctx buffers to new structure
nvgpu_gr_ctx_mappings.
This will be instantiated per subcontext in the upcoming patches.
Summary of changes:
1. Various context buffers were allocated and mapped separately.
All TSG context buffers are now stored in gr_ctx->mem[] array
since allocation and mapping is unified for them.
2. Mapping/unmapping and querying the GPU VA of the context
buffers is now handled in ctx_mappings unit. Structure
nvgpu_gr_ctx_mappings in nvgpu_gr_ctx holds the maps.
On ALLOC_OBJ_CTX this struct is instantiated and deleted
on free_gr_ctx.
3. Introduce mapping flags for TSG and global context buffers.
This is to map different buffers with different caching
attribute. Map all buffers as cacheable except
PRIV_ACCESS_MAP, RTV_CIRCULAR_BUFFER, FECS_TRACE, GR CTX
and PATCH ctx buffers. Map all buffers as privileged.
4. Wherever VM or GPU VA is passed in the obj_ctx allocation
functions, they are now replaced by nvgpu_gr_ctx_mappings.
5. free_gr_ctx API need not accept the VM as mappings struct
will hold the VM. mappings struct will be kept in gr_ctx.
6. Move preemption buffers allocation logic out of
nvgpu_gr_obj_ctx_set_graphics_preemption_mode.
7. set_preemption_mode and gr_gk20a_update_hwpm_ctxsw_mode
functions need update to ensure buffers are allocated
and mapped.
8. Keep the unit tests and documentation updated.
With these changes there is clear seggregation of allocation and
mapping of GR context buffers. This will simplify further change
to add multiple address spaces support. With multiple address
spaces in a TSG, subcontexts created after first subcontext
just need to map the buffers.
Bug 3677982
Change-Id: I3cd5f1311dd85aad1cf547da8fa45293fb7a7cb3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2712222
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The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and
ga100 sources have been collapsed. However, the ga100, ga10b sources
are not safety certified, so mark them as NON_FUSA by replacing
CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA.
Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support
by default on standard build.
Jira NVGPU-4771
Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092
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Query the num_perfmon requires golden context to be ready. Accessing
golden context might require gr_instance_id, specific to a GR engine.
On TOT, get_num_hwpm_perfmon() called from perfmon HAL which might
require to call nvgpu_gr_exec_with_err_for_instance().
It internally calls nvgpu_grmgr_config_gr_remap_window() to change
gr_window_remap register points to a current gr_instance_id for MIG.
This approach indirectly mandates to call
nvgpu_gr_exec_with_err_for_instance() which can be
completely avoided. get_num_hwpm_perfmon() is just a query call
which can be moved after the golden context creation.
Using this logic, we can avoid unnecessary invocation of
nvgpu_gr_exec_with_err_for_instance() during perform specific
HAL accesses.
1) Moved get_num_hwpm_perfmon() after golden context creation.
2) Added nvgpu_assert() if (g->num_sys_perfmon == 0U).
JIRA NVGPU-5656
Change-Id: I59a6ab4df93763adbc0765fa5e4d1712b2477521
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2542438
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If user calls IOCTL to allocate object context for two channels in same
TSG in parallel, nvgpu_gr_setup_alloc_obj_ctx() could end up racing and
trying to allocate object context for both channels at the same time.
This could result in corrupting object context.
Fix this by introducing per-TSG mutex ctx_init_lock to serialize context
initialization for all channels within TSG.
In ideal scenario nvrm_gpu is the only caller of all the IOCTLs, and
nvrm_gpu makes sure to initialize object context for each channel in
serial order. Because of this new lock does not cause any contention.
Jira NVGPU-6431
Change-Id: Ibb1cbb4878748929bb7f23e8666c283c39ecbf5a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538333
(cherry picked from commit 8be447838dc1ecbd5637eb6bd13b8f338eaf33cd)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2538773
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GVS: Gerrit_Virtual_Submit
Currently, we are performing obj ctx alloction for bellow classes
1. VOLTA_COMPUTE_A
2. VOLTA_DMA_COPY_A
3. VOLTA_CHANNEL_GPFIFO_A
In safety, we use Async CE but not GRCE.
So allocating obj context only for COMPUTE_A and return success(0) for
all other valid classes, after setting class in the channel struct.
Jira NVGPU-4378
Change-Id: Ie99872e062cc66f9ddf699397a13df85c3d8d59e
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2287486
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- nvgpu_gr_ctx_load_golden_ctx_image() does not return any error, change
the return type to void
- Check for preemption modes greater than CILP in
nvgpu_gr_ctx_check_valid_preemption_mode
- Check if received class is valid or not in
nvgpu_gr_setup_set_preemption_mode
- Compile out entire nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode since
it is really not doing anything in safety
- Remove the switch statement in nvgpu_gr_obj_ctx_set_compute_preemption_mode
since it is not possible to receive any other value than supported.
Previous function calls ensure that input values are validated.
- nvgpu_gr_obj_ctx_commit_global_ctx_buffers() does not return any
error, change the return type to void
- gops.gr.init.preemption_state HAL is not needed in safety since it
only configures gfxp related timeout
- remove redundant call to gops.gr.init.wait_idle in
nvgpu_gr_obj_ctx_commit_hw_state. We trigger wait despite earlier
failure in same function call.
Jira NVGPU-4457
Change-Id: I06a474ef7cc1b16fbc3846e0cad1cda6bb2bf2af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260938
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In nvgpu_gr_setup_set_preemption_mode function, nvgpu_channel_enable_tsg
and nvgpu_channel_disable_tsg calls are changed to gops calls.
In this function beginning nvgpu_tsg_from_ch is checked for NULL pointer
so nvgpu_channel_enable_tsg and nvgpu_channel_disable_tsg functions
never fail with NULL tsg pointer for branch coverage.
Jira NVGPU-3968
Change-Id: If2e1fee493426e56d62865b015dc8b21bad494b6
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258788
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Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Move code used only with graphics under
CONFIG_NVGPU_GRAPHICS check.
gm20b_gr_init_load_sw_bundle_init hal get called
without CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION check.
Remove dead code in
nvgpu_gr_ctx_check_valid_preemption_mode function.
Jira NVGPU-3968
Change-Id: I399126123006ae44dba29b3c08378d11fe82e543
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247346
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This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id
JIRA NVGPU-3516
Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Below MISRA 5.7 violation is reported in common.gr.setup unit
nvgpu/drivers/gpu/nvgpu/common/gr/gr_setup.c:218:
identifier_reuse: Identifier "class" is already used to represent a type.
nvgpu/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h:27:
type_declaration: Declaring a type with identifier "class".
Fix this by changing variable name "class" to "class_num"
Jira NVGPU-3407
Change-Id: I7517995b105c65c2fa78f4959aad9e3f04585f02
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114363
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo
Remove fifo.get_preempt_timeout
Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel
Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal
Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc
JIRA NVGPU-3144
Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
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Debug boolean flag dump_ctxsw_stats_on_channel_close is right now stored
in gr_gk20a.ctx_vars struct
This flag logically is property of gr.ctx units since it indicates
whether each context should dump ctxsw stats on channel/context close
Move this flag to struct nvgpu_gr_ctx_desc and remove it from
gr_gk20a.ctx_vars
Expose below API from gr.ctx unit to check if flag is set
nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of this variable from platform
specific probe functions
Jira NVGPU-3112
Change-Id: Id675e047237f82e9b8198a42082e99c95824578f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099399
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.
Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c
Call gr free before the gk20a free call in nvgpu_free_gk20a.
Rename struct gr_gk20a to struct nvgpu_gr
JIRA NVGPU-3132
Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Many of the functions in common.gr.obj_ctx and common.gr.fs_state units
directly dereference struct gr_gk20a to obtain other structures
e.g. API nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode() obtains pointer
to nvgpu_gr_config struct by direct access g->gr.config
Such accesses add dependency of these units on gr.h and hence create
circular dependency with common.gr.gr unit
Fix this by receiving all required structures in the function parameter
list itself
Jira NVGPU-1886
Change-Id: Iee973ae33fc7e1707b8f025ad61683f725dedb53
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094995
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Add new API nvgpu_gr_setup_free_subctx() in common.gr.ctx to free subctx
Call this via hal g->ops.gr.setup.free_subctx()
Subctx allocations happens through gr.setup api right now hence it makes
sense to provide subctx free api through same unit
Remove g->ops.channel.free_ctx_header() hal since we now have gr.setup
hal
Remove gv11b/subctx_gv11b.* files since they are no longer needed and
all the code in them has been moved to common units
Jira NVGPU-1886
Change-Id: I3d58fc3665ed9b6ffba830249a4cd30af7b857f4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094994
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Created class unit under hal and moved all valid class check related
functionality to this unit. Moved all class defs from gr to a new header
include/nvgpu/class.h.
Moved following hals from gr to newly created class unit:
bool (*is_valid_class)(struct gk20a *g, u32 class_num); -->
bool (*is_valid)(u32 class_num);
bool (*is_valid_gfx_class)(struct gk20a *g, u32 class_num); -->
bool (*is_valid_gfx)(u32 class_num);
bool (*is_valid_compute_class)(struct gk20a *g, u32 class_num); -->
bool (*is_valid_compute)(u32 class_num);
JIRA NVGPU-3109
Change-Id: I01123e9b984613d4bddb2d8cf23d63410e212408
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095542
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Add api nvgpu_gr_setup_set_preemption_mode() in common.gr.setup to
set various preemption modes
Define new hal g->ops.gr.setup.set_preemption_mode() that calls above
common api
Move corresponding code from gr_gp10b.c to common.gr.setup unit
Jira NVGPU-1886
Change-Id: I7cb0187a4809156e5f90f39727a782b17219afa3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092170
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Add below apis in common.gr.setup to allocate/free context
nvgpu_gr_setup_alloc_obj_ctx()
nvgpu_gr_setup_free_gr_ctx()
Define two new hals
g->ops.gr.setup.alloc_obj_ctx()
g->ops.gr.setup.free_gr_ctx()
Move corresponding code from gr_gk20a.c to common.gr.setup unit
Jira NVGPU-1886
Change-Id: Icf170a6ed8979afebcedaa98e3df1483437b427b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092169
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Add new unit common.gr.setup that provides runtime setup interfaces to
other units outside of GR unit or to OS-specific code
Move zcull setup call to this unit.
New unit now exposes nvgpu_gr_setup_bind_ctxsw_zcull() to setup zcull
This API internally calls common.gr.zcull API nvgpu_gr_zcull_ctx_setup()
Add new hal g->ops.gr.setup.bind_ctxsw_zcull() and remove
g->ops.gr.zcull.bind_ctxsw_zcull()
Remove nvgpu_channel_gr_zcull_setup() from channel unit
Also remove ctx/subctx header includes sicne channel code need not
configure zcull
Remove gm20b_gr_bind_ctxsw_zcull() since binding is done from common
code
Jira NVGPU-1886
Change-Id: I6f04d19a8b8c003734702c5f6780a03ffc89b717
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2086602
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