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vinodg
bb942331e8 gpu: nvgpu: compile out unused code in gr.falcon unit 
NVGPU_GR_FALCON_METHOD_HALT_PIPELINE section is used only
with CONFIG_NVGPU_ENGINE_RESET setting.

Jira NVGPU-4453

Change-Id: Ia33e370486ebcd2052b7ec9d530503f93e798cbf
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253865
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Tejal Kudav
c8c8e59a46 gpu: nvgpu: unit: add priv_ring unit tests 
Add unit tests for common.priv_ring unit.

JIRA NVGPU-934

Change-Id: Ic825f571a3032cf9a194773df09a255bcba1bf79
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248567
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Debarshi Dutta
037c5761e7 gpu: nvgpu: handle syncpoint buffer alloc failure 
Add check for syncpoint buffer allocation failure in the function
nvgpu_channel_sync_syncpt_create. Return NULL if the allocation fails.

Also, put a reference to the syncpoint allocated if the above
buffer allocation fails.

Change-Id: I56ab03df3b37a3c8148ee17ec6a7829686e44de6
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247637
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
8592b0591c gpu: nvgpu: Add fail scenarios in ACR unit tests 
- Add more fail scenarios in ACR unit tests to cover
  branches
- Return "err" value when "get_lsf_ucode_details" ops
  for fecs fails.

JIRA NVGPU-4319

Change-Id: Ic9ba0afb26b23f6e0c0ebd76feae5b1ba3098b93
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252801
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
648de73142 gpu: nvgpu: unit: add SWUTS for common.mm.gmmu.pd_cache 
Add the SWUTS documentation for the common.mm.gmmu.pd_cache unit
test.

JIRA NVGPU-3943

Change-Id: Ifbc6600ccb1b86f5d82984996f491968c68e53ab
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247246
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
c6074ad443 gpu: nvgpu: unit: add SWUTS for common.mm.gmmu.page_table 
Add the SWUTS documentation for the common.mm.gmmu.page_table unit
test.

JIRA NVGPU-3943

Change-Id: Ic01fd9cc6c21dfa91c480570e6f260d75395385d
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2240264
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
fd97e5db1c gpu: nvgpu: unit: add SWUTS for common.mm.page_table_faults 
Add the SWUTS documentation for the common.mm.page_table_faults unit
test.

JIRA NVGPU-3943

Change-Id: Ie3e8a2b8f5aebf2fc96af9108aa7b202fbb16ba7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2240263
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
c34008a8cf gpu: nvgpu: unit: add SWUTS for common.mm.dma 
Add the SWUTS documentation for the common.mm.dma unit test.

JIRA NVGPU-3943

Change-Id: I5e89214d2c37f33b5059229076fd5db66b7d3d39
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2240262
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Nicolas Benech
86f1b2336a gpu: nvgpu: unit: add test function name to logs 
This patch adds the test function name to output logs to make it
easier to establish traceability between SWUTS and test results.
Also, the unit test name as defined in the UNIT_TEST macro can
now be used to clarify the subcase when a given test function is
used several times with different arguments.

JIRA NVGPU-3510

Change-Id: I652ecd8c06fd89e4d78d419f73b35b69ae71a8ef
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2241879
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
1ab3f73230 gpu: nvgpu: unit: improve coverage for gm20b channel HAL 
Add unit test for the following HAL:
- gm20b_channel_force_ctx_reload

Jira NVGPU-4384

Change-Id: Icb802348349a790371e6d84efe449c309105c5e8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250014
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
770090630c gpu: nvgpu: add error injection test in common.gr.setup 
Add error injection test for gr.setup.alloc_obj_ctx function.
Add doxygen for test_gr_setup_alloc_obj_ctx_error_injections call.

Clear ch->subctx variable after freeing the memory.

Jira NVGPU-3968

Change-Id: I17541ad86e3efb540bd3c8a9d008767c588377f3
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250094
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Prateek sethi
eb7e295534 nvgpu_rmos: Add fault injection instances for QNX devctl APIs 
Jira NVGPU-2667

Change-Id: I950d69906e626bfc62e9f112f1469d772b70d14e
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252568
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Rajesh Devaraj
0d19c7a546 gpu: nvgpu: update fault injection 
This patch updates fault injection for nvgpu_thread_create_priority().

JIRA NVGPU-2694

Change-Id: I254649cfd6b7a76afe89b227991fbe9e03c422ea
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252737
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
ajesh
c46a68c231 gpu: nvgpu: add rwsem unit test 
Add unit tests for rwsem unit.

Jira NVGPU-2698

Change-Id: Id8c6f336b3cc2c458f42a8c21a9bace3a7711e05
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208425
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Deepak Nibade
df5924cf57 gpu: nvgpu: unit: add common.class unit tests 
Add unit tests for API exposed by common.class unit

Jira NVGPU-4373

Change-Id: Id72df78c5a3c8a85ac71dd3b559d19c296c87b5f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2246808
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
84a24c9593 gpu: nvgpu: Remove TPC powergate from safety build 
- Remove non-safe TPC powergate feature from the safety
  build by introducing a new flag:
  CONFIG_NVGPU_TPC_POWERGATE

- Move nvgpu_init_power_gate_gr() under same compile time flag.
  and move HAL function gr_gv11b_powergate_tpc() to tpc_gv11b.c

- Also, remove the negative test scenario and
  usage of tpc_powergate from unit tests

JIRA NVGPU-4149

Change-Id: If489482401e94de499e472b16b1bc091b00992e6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242323
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Tejal Kudav
836abc253d gpu: nvgpu: unit: common.fbp tests 
Add unit tests for all the APIs exposed by common.fbp unit.

JIRA NVGPU-4393

Change-Id: I4aef64359919418ee5446925331fa9ef9eb5d5f0
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244373
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
44a87d320e gpu: nvgpu: split lists for hwpm control regs 
FECS ucode introduces separate register lists for control registers, so
that they can be restored separately from PM state.
Added support for:
- LIST_compressed_nv_perf_sys_control_ctx_regs
- LIST_compressed_nv_perf_pma_control_ctx_regs
- LIST_compressed_nv_perf_fbp_control_ctx_regs
- LIST_compressed_nv_perf_gpc_control_ctx_regs

Bug 200507276

Change-Id: Ifce398bcb298822f3a46cf372ef9610a46a8df0c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2193528
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Prateek sethi
31ac3a1f6e gpu: nvgpu: doxygen: add NVCPU_IS_AARCH64 flag 
The doxygen config file did not have NVCPU_IS_AARCH64 flag which is
required by os_utils barrier subunit.
Add flag to enable source enclosed with the flag.

JIRA NVGPU-4410

Change-Id: Ic3be19d636db775a489a9cbdb0c82da8a069ffcd
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2249533
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
8fa2fcd9da gpu: nvgpu: unit: use gr/ce engine interrupt mask 
nvgpu_engine_interrupt_mask has been split into
nvgpu_gr_engine_interrupt_mask and nvgpu_gr_engine_interrupt_mask.
Update test_engine_interrupt_mask to combine them.

Jira NVGPU-3693

Change-Id: I1e09ff3efd83415120773da75f8b512a481ee14c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2249913
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
0ba37ecf4d gpu: nvgpu: unit: enable pbdma tests on target 
Add missing pbdma, runlist and channel files to tmake
makefile and fix compilation issues.
Update exports to fix link issues.
Update required tests in JSON file.

Jira NVGPU-3490

Change-Id: Ib5f7dd15ebbd81c5f5f304f8c22ea8299c469a93
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247248
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Rajesh Devaraj
b5acb44f2f gpu: nvgpu: add flag to enable the usage of 3lss error injection support 
This patch introduces the flag CONFIG_NVGPU_3LSS_ERR_INJECTION to enable
the usage of 3lss error injection support in non-safety build (DEV PCT).

JIRA ESS-4206

Change-Id: I9081d6073e66d3657b4cf8b5ee691f031555739a
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247708
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
2a81cea0e0 gpu: nvgpu: unit: setup preemption error test 
Add Setup set_preemption_mode error tests with
test_gr_setup_preemption_mode_errors function.

Update Doxygen for test_gr_setup_preemption_mode_errors.

Jira NVGPU-3698

Change-Id: I21e84c9f7f2618656cb6b79b97802e182aed4516
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247378
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
b5ab4342fd gpu: nvgpu: update gr code for safety build 
Move code used only with graphics under
CONFIG_NVGPU_GRAPHICS check.

gm20b_gr_init_load_sw_bundle_init hal get called
without CONFIG_NVGPU_GR_GOLDEN_CTX_VERIFICATION check.

Remove dead code in
nvgpu_gr_ctx_check_valid_preemption_mode function.

Jira NVGPU-3968

Change-Id: I399126123006ae44dba29b3c08378d11fe82e543
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247346
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
c50de751dd gpu: nvgpu: compile out unused code in gr.falcon hal 
gm20b_gr_falcon_submit_fecs_sideband_method_op is used only with
graphics support. Add CONFIG_NVGPU_GRAPHICS checking for that function.

Jira NVGPU-3968

Change-Id: I858f9b27ec668ebbfa02abf89dd58d7496f5678d
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
27cc81dafa gpu: nvgpu: unit: add tests for common.fifo.engine 
Add unit tests for:
- nvgpu_engine_setup_sw
- nvgpu_engine_cleanup_sw
- nvgpu_engine_init_info
- nvgpu_engine_get_ids
- nvgpu_engine_check_valid_id
- nvgpu_engine_get_gr_id
- nvgpu_engine_get_active_eng_info
- nvgpu_engine_enum_from_type
- nvgpu_engine_interrupt_mask
- nvgpu_engine_act_interrupt_mask
- nvgpu_engine_get_all_ce_reset_mask

Jira NVGPU-3693

Change-Id: I8cbaea1918b284ac09a502225fa674f84c08eb8e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242701
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
e647a146e1 gpu: nvgpu: store engine_id in CE engine_info 
engine_id was not updated in engine_info structure for CE.
Add engine_id update in gp10b_engine_init_ce_info.

Jira NVGPU-3490

Change-Id: I260767a2baf1d04702f7c2b622069fdaa33d49cb
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242700
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
945e9ebee2 gpu: nvgpu: checks in nvgpu_engine_init_info 
Return error in nvgpu_engine_init_info if g->ops.top.get_device_info
is NULL. In particular, do not attempt to init CE info.

Jira NVGPU-3693

Change-Id: I521cb43233a48b6e765ffd0b1feee81a30dbd739
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242699
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Philip Elcan
95c3e56961 gpu: nvgpu: unit: propagate fault injection to threads 
Change approach to how the fault injection state is stored to facilitate
propagating fault injection state to child-threads. Rather than each
unit maintaining a thread-local object, there is a thread-local
container stored in the posix-fault-injection itself. This container is
initialized for each test module so that is independent of other other
test modules (for parallel test module execution). When child threads
are created with nvgpu_create_thread(), the fault injection container is
configured for the child.

JIRA NVGPU-3981

Change-Id: I9b580dc7f1621a7770eef8eba796f3918f2738bf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2238474
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Philip Elcan
0f5dd4e9b6 gpu: nvgpu: unit: fix configs for qnx unit test binaries 
Set the unit test configs correctly for the QNX unit test build.

The defines __NVGPU_UNIT_TEST__ and
NVGPU_UNITTEST_FAULT_INJECTION_ENABLEMENT were not being set for the
unit tests in the QNX build, only for the libnvgpu_ut.so. Therefore,
some structs were defined differently in the two files causing
segfaults.

JIRA NVGPU-3981

Change-Id: Ia4fbaae7df89b9034a3d50a8c99eefe1d19898a8
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245554
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Tejal Kudav
aec0296c17 gpu: nvgpu: Remove Non-FUSA code from common.fbp 
Rop_L2_en_mask and num_fbps are not accessed by Safety code; so move
their initialization code out Safety build using CONFIG_NVGPU_NON_FUSA.

JIRA NVGPU-4393

Change-Id: I9c518239cbfc99bbe0140386ecd4ca111f59b358
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244372
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
a8c9c800cd gpu: nvgpu: reorganization of MC interrupts control 
Previously, unit interrupt enabling/disabling and corresponding MC level
interrupt enabling/disabling was not done at the same time.
With this change, stall and nonstall interrupt for units are programmed
at MC level along with individual unit interrupts. Kept access to MC
interrupt registers through mc.intr_lock spinlock.

For doing this separated CE and GR interrupt mask functions.
mc.intr_enable is only used when there is global interrupt
control to be set. Removed mc_gp10b.c as mc_gp10b_intr_enable
is now removed. Removed following functions - mc_gv100_intr_enable,
mc_gv11b_intr_enable & intr_tu104_enable. Removed intr_pmu_unit_config
as we can use the generic unit interrupt control function.

JIRA NVGPU-4336

Change-Id: Ibd296d4a60fda6ba930f18f518ee56ab3f9dacad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196178
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
daf5475f50 gpu: nvgpu: split ecc support per GPU HW unit 
To enable ecc interrupts early during nvgpu_finalize_poweron, ecc
support has to be enabled early. ecc support was being initialized
together for GR, LTC, PMU, FB units late in the poweron sequence.

Move the ecc init for each unit to respective unit's init functions.
And separate out the hal ecc functions from GR ecc unit to
respective hal units.

JIRA NVGPU-4336

Change-Id: I2c42fb6ba3192dece00be61411c64a56ce16740a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2239153
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 2020-12-15 14:10:29 -06:00
vinodg
89518f3740 gpu: nvgpu: compile out unused code in gr unit 
Compile out code not used in safety for gr subunit.
The code is used only with dgpu support.

Jira NVGPU-3968

Change-Id: I7be5b06c6eed5a6d382016f1ccb5dbec63928294
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247146
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 2020-12-15 14:10:29 -06:00
Peter Daifuku
fa8ca3fb19 gpu: nvgpu: re-enable elpg after golden img init 
Typically, the PMU init thread will finish up long
before the golden context image has been initialized,
which means that ELPG hasn't truly been enabled at that
point.

Create a new function, nvgpu_pmu_reenable_pg(), which
checks if elpg had been enabled (non-zero refcnt), and
if so, disables then re-enables it.

Call this function from nvgpu_gr_obj_ctx_alloc() after
the golden context image has been initialized to ensure
that elpg is truly enabled.

Bug 200543218

Change-Id: I0e7c4f64434c5e356829581950edce61cc88882a
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245768
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:29 -06:00
Philip Elcan
7de9f2c331 gpu: nvgpu: unit: init: add more testing for hal init 
Expand coverage for the hal init unit test to include negative testing
and line/branch coverage.

Also add Targets tag for SWUTS.

JIRA NVGPU-927

Change-Id: Ied63756b0d5abaaa03cd9aaa7b6a7fd817a1a967
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245612
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
b69615ef00 gpu: nvgpu: posix: add flag to make gpu version a01 
Add posix flag to allow unit tests to make device version gv11b a01 for
better branch coverage.

JIRA NVGPU-927

Change-Id: I410c4c6befa7b27bb258d743e7f5f9d718d33d47
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245611
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
d9230e4087 gpu: nvgpu: unit: init: add testing for get_litter API 
Add unit testing for gv11b_get_litter_value().

JIRA NVGPU-927

Change-Id: I9ddfbe5780ce1a383818672837f8f052c663cac7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245610
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
a6c4eb4c14 gpu: nvgpu: update test_gk20a_runlist_wait_pending spec 
Update description for test_gk20a_runlist_wait_pending.
Test is now using register IO callbacks instead of a thread to
clear fifo_eng_runlist_r pending bit.

Jira NVGPU-3793

Change-Id: I7ddae3f4574705eb57bd432693da91480c7f09dd
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243621
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:29 -06:00
rmylavarapu
db62de9f00 gpu: nvgpu: volt: Remove volt_policy get status 
Removed volt_policy get status implimentation as in
turing we are using volt_rail get status for reading
voltage which are policy independent.

NVGPU-4372

Change-Id: Id3c91c5eb03c13cdb83eb39decd44bf53ae7f473
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243967
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 2020-12-15 14:10:29 -06:00
rmylavarapu
67e46fb8ee gpu: nvgpu: volt: Remove unsused code in volt_policy 
Removed unused split rail structs and functions which
are no longer valid for turing. Split rail structs are
retained in supersurface boradobj interface structs
as this is needed by PMU. Can be removed once the PMU
code is updated.

NVGPU-4372

Change-Id: Ia22437d250db4b784c99797ee80e534525cc813b
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243944
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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 2020-12-15 14:10:29 -06:00
rmylavarapu
4ea2594876 gpu: nvgpu: volt: Remove unused code in volt_dev 
- Removed unused operation type checks
- Removed unused operation type macros

NVGPU-4372

Change-Id: Ic767ce7241d7940d0cd89922a8699b7db15393ff
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243088
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 2020-12-15 14:10:29 -06:00
rmylavarapu
c83c730c30 gpu: nvgpu: volt: Remove usused code in volt_rail 
- Removed conditional checks for split rails
- Removed macro of split rail

Change-Id: Id14eeabdbbfb4e7adc516a5631eedee7a92427da
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243071
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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 2020-12-15 14:10:29 -06:00
rmylavarapu
4c1618cc52 gpu: nvgpu: volt: Remove unused struct in pmuif/volt.h 
- Removed VF inject structures
- Removed volt msg stuctures
- Removed volt cmd structures

NVGPU-4372

Change-Id: Idd2d59e7ca1adc2edb80b3d5ebdd87f36a956a4c
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243054
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 2020-12-15 14:10:29 -06:00
rmylavarapu
7b97d3f949 gpu: nvgpu: volt: Remove unused code in volt_pmu.c 
-Removed volt cmdhandler
-Removed volt set/get structures
-Removed volt set/get Macros

NVGPU-4372

Change-Id: I0de7698fd1d86e5ca6a8399481b790738b9cbf4c
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243026
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Divya Singhatwaria
15c9355c69 gpu: nvgpu: Add more test scenarios for ACR unit 
Add more test scenarios for nvgpu_acr_bootstrap_hs_acr()
and nvgpu_acr_construct_execute() to cover more
branches and fail scenarios

JIRA NVGPU-4319

Change-Id: Ifae3fdce87c4a42d0fbdb4dff25dfb10537f31d0
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2238098
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 2020-12-15 14:10:29 -06:00
vinodg
df68da0e66 gpu: nvgpu: unit: add tests for common.gr.setup 
Add tests to cover common.gr.setup subunit. This includes
g->ops.gr.setup.alloc_obj_ctx
g->ops.gr.setup.set_preemption_mode
g->ops.gr.setup.free_gr_ctx and
g->ops.gr.setup.free_subctx.

Update register space to include the registers used by
context creation.
Update SWUT files for doxygen.

Jira NVGPU-3968

Change-Id: I3ab539d18584231142a1945d621d015b7ca772de
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2244825
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Lakshmanan M
d6a20e31b3 gpu: nvgpu: tu10x: Add CE diversity gpu characteristic flag 
Tu104 has multiple async-LCE (3), GRCE (2) and PCE (4).
So it is possible to use a different LCE/PCE during redundant
execution. This will allow us to claim very high coverage for
permanent fault.

JIRA NVGPU-4370

Change-Id: Ib39013d8d4f377eb20820db100af57c57592c39d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2243984
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Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Nicolas Benech
eb4349548d gpu: nvgpu: unit: stage vm.init_error_paths subcase 
One subcases in the init_error_paths test case is causing
intermittent failures (free of non malloc'ed memory) due to the
nature of error injection. This patch removes the subcase until
a better way to test the condition is devised.

JIRA NVGPU-4328

Change-Id: Ic463bb1466b93016b9166e6297745d21d4fb0942
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245485
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Petlozu Pravareshwar
1b9e66a284 nvgpu: gpu: Add mssnvlink0 reset control config 
On safety build, MSSNVLINK HV is supporting dynamic update of
Protection table. Hence Guest OS Nvlink driver can't control
mssnvlink0 reset on safety build.

For this purpose, CONFIG_MSSNVLINK0_RST_CONTROL flag is defined and
enabled for the standard build, while it will be disabled for
the safety builds.

Bug 200545652

Change-Id: I4c03250475cc63e5f9ded1bf3ef3c462db46cd44
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2242454
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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 2020-12-15 14:10:29 -06:00