Below MISRA 5.7 violation is reported in common.gr.setup unit
nvgpu/drivers/gpu/nvgpu/common/gr/gr_setup.c:218:
identifier_reuse: Identifier "class" is already used to represent a type.
nvgpu/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h:27:
type_declaration: Declaring a type with identifier "class".
Fix this by changing variable name "class" to "class_num"
Jira NVGPU-3407
Change-Id: I7517995b105c65c2fa78f4959aad9e3f04585f02
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114363
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Some functions are not accessing hardware directly
but are being called using HAL ops: For example
g->ops.pmu.pmu_elpg_statistics,
g->ops.pmu.pmu_pg_init_param,
g->ops.pmu.pmu_pg_supported_engines_list,
g->ops.pmu.pmu_pg_engines_feature_list,
g->ops.pmu.pmu_is_lpwr_feature_supported,
g->ops.pmu.pmu_lpwr_enable_pg,
g->ops.pmu.pmu_lpwr_disable_pg,
g->ops.pmu.pmu_pg_param_post_init,
g->ops.pmu.save_zbc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g,
u32 feature_id);
JIRA NVGPU-3209
Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110963
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.
Bug 2459186
Change-Id: I71daf6fdb1bb67974f6e51e091f868cb08d3b0bf
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111028
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fix misra errors from nvgpu_gr_ctx_prepare_hwpm_mode()
Error: MISRA C-2012 Rule 16.1:
nvgpu/drivers/gpu/nvgpu/common/gr/ctx.c:815:
missing_break: This switch clause does not end with
an unconditional break statement.
nvgpu/drivers/gpu/nvgpu/common/gr/ctx.c:785:
misra_violation: The switch statement is not well formed.
NVGPU-3224
Change-Id: Ica7029fd84f443b8ce3d51a5c5f32bb6a6172040
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112703
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Below 5.7 violations are reported in common.gr.config unit :
nvgpu/drivers/gpu/nvgpu/common/gr/gr_config.c:628:
identifier_reuse: Identifier "sm_info" is already used to represent a type.
Fix them by renaming struct sm_info to struct nvgpu_sm_info
Jira NVGPU-3225
Change-Id: I26f70a4ed2a5a845e0dc9daeb8fb5474e35d42fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110986
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.
Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.
Jira NVGPU-3218
Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.
Bug 2459186
Change-Id: I8080b21d21259e863c099883d6be737e9a869e50
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109286
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().
JIRA NVGPU-2042
Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Removed gr dependency on ecc by moving ecc init/remove support
calls to nvgpu_init. With this, only dependency from ecc to gr
present.
Added following parameter in struct nvgpu_ecc to check/update ecc
initialization status:
bool initialized;
JIRA NVGPU-3212
Change-Id: I04611175cbd959cb8082e63c30214266f5d5b731
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107955
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move remaining chip specific gr hal files to hal.gr.gr unit.
Remove unused headers include from hal files in hal.gr.gr unit
Update gr hal headers include location in the files currently
using these headers.
Jira NVGPU-3219
Change-Id: Ic632020a90ac4b8ac1e0359e979864b42f0ef2c0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105489
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max_ctxsw_ring_buffer_size variable in struct nvgpu_gr is used to store
max ring buffer size which is then referred into linux specific code
We only use macro GK20A_CTXSW_TRACE_MAX_VM_RING_SIZE to initialize
the variable.
And max_ctxsw_ring_buffer_size does not belong to nvgpu_gr struct
anyways
Considering above remove max_ctxsw_ring_buffer_size from nvgpu_gr and
use macro directly in linux specific code
Jira NVGPU-3125
Change-Id: Ibed9901d2bde35633d9ad0df8bd08b414e075bf4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105653
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Currently max_css_buffer_size is incorrectly stored in struct nvgpu_gr
Add a new hal g->ops.css.get_max_buffer_size() to get the size and
remove the variable from struct nvgpu_gr
Jira NVGPU-3125
Change-Id: If78fd86559526b84031051e281a98327a46fc11d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2105652
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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-Currently PG task is created for both iGPU & dGPU as part PMU init
sequence path, but task is not required for dGPU or can be skipped
if ELPG is not supported on iGPU, made changes to create PG task only
if supported else skip it, and made some functions to private as these
are required by PG UNIT only.
-PG instance is allocated & set to default properties as needed if
support is enabled else skip it.
-Made changes in dependent files as required to reflect above changes
JIRA NVGPU-1972
Change-Id: I4efb7f1814a9ad48770acea2173e66f0a4c8a9c1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094840
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cyclestats_snapshot data and lock is right now stored in struct nvgpu_gr
Use case itself is not specific to GR engine but in general it applies
to other units outside of GR too.
Hence it makes sense to move both data and lock to struct gk20a instead
of keeping them in struct nvgpu_gr
Update all cyclestats_snapshot code to refer data/lock from struct gk20a
Remove gr_priv.h header include from cyclestats_snapshot.c
Some of the functions were mistakenly declared in gr_gk20a.h.
Move them to cyclestats_snapshot.h and rename them to form nvgpu_css_*()
Jira NVGPU-1103
Change-Id: I3fb32fe96f0ca6613f4640c8bd227b9e0e02dca3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104848
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Separate out cyclestats handling code into separate unit
common.cyclestats
This unit now exposes new API nvgpu_cyclestats_exec() to perform
cyclestats operation. Call this API from common.gr.intr unit
Extract out all the private data structures from gk20a.h to
cyclestats_priv.h
Rename struct gk20a_cyclestate_buffer_elem to
nvgpu_cyclestate_buffer_elem
Jira NVGPU-1103
Change-Id: Id362675228fe23d03d6d277ff320bcc1066c3c64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104202
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
gr_gk20a.ctx_vars struct right now stores sizes for golden_image, zcull,
pm_ctxsw, and gfxp_preemption_buffer.
but these sizes should be really owned by respective units and should
be assigned to units as soon as they are queried from FECS
Add new structure to nvgpu_gr_falcon to hold sizes that will be queried
from FECS
struct nvgpu_gr_falcon_query_sizes {
u32 golden_image_size;
u32 pm_ctxsw_image_size;
u32 preempt_image_size;
u32 zcull_image_size;
};
gr.falcon unit now queries sizes from FECS and fills this structure.
gr.falcon unit also exposes below APIs to query above sizes
u32 nvgpu_gr_falcon_get_golden_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_pm_ctxsw_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_preempt_image_size(struct nvgpu_gr_falcon *falcon);
u32 nvgpu_gr_falcon_get_zcull_image_size(struct nvgpu_gr_falcon *falcon);
gr.gr unit now calls into gr.falcon unit to initailize sizes, and then
uses above exposed APIs to set sizes into respective units
vGPU will too fill up struct nvgpu_gr_falcon_query_sizes with all the sizes
and then above APIs will be used to set sizes into respective units
All of above means size variables in gr_gk20a.ctx_vars struct are no more
being referred. Delete them.
Jira NVGPU-3112
Change-Id: I8b8e64ee0840c3bdefabc8ee739e53a30791f2b3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103478
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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struct gr_gk20a defines boolean flag golden_image_initialized to
indicate if golden_image is initialized or not
common.gr.obj_ctx also added a flag of its own to check if golden_image
is ready
Add new API nvgpu_gr_obj_ctx_is_golden_image_ready() in
common.gr.obj_ctx unit to get status of golden_image
Use this new API everywhere to check if golden image is ready
Remove g->gr.ctx_vars.golden_image_initialized
Also remove ctx_mutex from struct gr_gk20a
Add new flag golden_image_initialized to struct nvgpu_pmu_pg and set it
when golden image is initialized. This is needed to avoid circular
dependency between GR and PMU
Jira NVGPU-3112
Change-Id: Id391294cede6424e15a9a9de29c40d013b509534
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099400
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Move gr_gk20a_handle_fecs_error from gr_gk20a.c to
nvgpu_gr_intr_handle_fecs_error in common.gr.intr unit
Move gr_gp10b_handle_fecs_error and gr_gv11b_handle_fecs_error
to hal.gr.intr unit
JIRA NVGPU-3016
Change-Id: I5b7c48ebfd7b13f497980c4d0b64d718649154bd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103741
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Move gr_gp10b_handle_sm_exception from gr_gp10b to
gp10b_gr_intr_handle_sm_exception in hal.gr.intr unit
Move gr_gk20a_handle_sm_exception from gr_gk20a to
nvgpu_gr_intr_handle_sm_exception in common.gr.intr
Move nvgpu_report_gr_sm_exception to common.gr.intr
JIRA NVGPU-3016
Change-Id: I545ddca052122f87685f35f515831841a246dab3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103736
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Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:
int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
int nvgpu_gr_halt_pipe(struct gk20a *g);
HALs also moved accordingly and updated code to reflect this.
Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;
JIRA NVGPU-3168
Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
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Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo
Remove fifo.get_preempt_timeout
Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel
Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal
Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc
JIRA NVGPU-3144
Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
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gfxp_wfi_timeout_count/unit fields were stored in gr_gk20a.ctx_vars
struct so that any user could configure them through sysfs nodes
But the sysfs nodes are legacy and not being actively used by anyone.
Hence delete the sysfs nodes to configure these fields.
Since the gfxp timeout unit/count can now be statically programmed,
make following changes
- remove g->ops.gr.init_gfxp_wfi_timeout_count() hal
- remove g->ops.gr.get_max_gfxp_wfi_timeout_count() hal
- update g->ops.gr.init.preemption_state() hals to configure the values
using macros instead of caller passing the values
- update g->ops.gr.init.gfxp_wfi_timeout() hals to configure the values
using macros instead of caller passing the values
Finally, we don't need to store gfxp_wfi_timeout_count/unit fields
anymore, hence delete them from gr_gk20a.ctx_vars
Jira NVGPU-3112
Change-Id: Idbe5ab3053228dd177aca253545aac36d38ca8ad
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Debug boolean flag dump_ctxsw_stats_on_channel_close is right now stored
in gr_gk20a.ctx_vars struct
This flag logically is property of gr.ctx units since it indicates
whether each context should dump ctxsw stats on channel/context close
Move this flag to struct nvgpu_gr_ctx_desc and remove it from
gr_gk20a.ctx_vars
Expose below API from gr.ctx unit to check if flag is set
nvgpu_gr_ctx_desc_dump_ctxsw_stats_on_channel_close()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of this variable from platform
specific probe functions
Jira NVGPU-3112
Change-Id: Id675e047237f82e9b8198a42082e99c95824578f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099399
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Debug boolean flags force_preemption_gfxp and force_preemption_cilp are
right now stored in gr_gk20a.ctx_vars struct
These flags logically are property of gr.ctx units since they indicate
whether each context should be forced to gfxp/cilp preemption mode by
default
Move these flags to struct nvgpu_gr_ctx_desc and remove them from
gr_gk20a.ctx_vars
Expose below APIs from gr.ctx unit to check if flags are set
nvgpu_gr_ctx_desc_force_preemption_gfxp()
nvgpu_gr_ctx_desc_force_preemption_cilp()
Move debugfs creation code to create corresponding debugfs to
gr_gk20a_debugfs_init() and change debugfs type from "u32" to "file"
Struct gr.gr_ctx_desc is created only during first poweron.
Return error if this struct is not available.
Remove unnecessary initialization of these variables from platform
specific probe functions
Jira NVGPU-3112
Change-Id: I8b2de27f0c71dd2ea5abcf94221c2e15c80073ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099398
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.
Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c
Call gr free before the gk20a free call in nvgpu_free_gk20a.
Rename struct gr_gk20a to struct nvgpu_gr
JIRA NVGPU-3132
Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception
Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx
JIRA NVGPU-1891
Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
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Add a new MM HAL directory to contain all MM related HAL units.
As part of this change add cache unit to the MM HAL. This contains
several related fixes:
1. Move the cache code in gk20a/mm_gk20a.c and gv11b/mm_gv11b.c to
the new cache HAL. Update makefiles and header includes to take
this into account. Also rename gk20a_{read,write}l() to their
nvgpu_ variants.
2. Update the MM gops: move the cache related functions to the new
cache HAL and update all calls to this HAL to reflect the new
name.
3. Update some direct calls to gk20a MM cache ops to pass through
the HAL instead.
4. Update the unit tests for various MM related things to use the
new MM HAL locations.
This change accomplishes two architecture design goals. Firstly it
removes a multiple HW include from mm_gk20a.c (the flush HW header).
Secondly it moves code from the gk20a/ and gv11b/ directories into
more proper locations under hal/.
JIRA NVGPU-2042
Change-Id: I91e4bdca4341be4dbb46fabd72622b917769f4a6
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095749
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Move zcull size initialization to hal.gr.zcull unit.
This removes zcull dependency on falcon unit
Add new variable zcull_image_size to gr_gk20a.ctx_vars struct
Pass the size to nvgpu_gr_zcull_init()/vgpu_gr_init_gr_zcull() as
parameter to initialize zcull info
Jira NVGPU-3112
Change-Id: I54d966073dad658b4aad3a529f44c0478208b10c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098507
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Add new API nvgpu_gr_hwpm_map_get_size() in gr.hwpm_map unit to get
size of hwpm_map.
Use this API to get size and allocate each pm_ctx
Move nvgpu_gr_hwpm_map_init() call to gr.gr unit in gr_init_setup_sw()
instead of calling it from gr.falcon unit
Add nvgpu_gr_hwpm_map_init() to vGPU initialization to initialize
hwpm_map size on vGPU
Jira NVGPU-3112
Change-Id: Ifc669dcc9ecae273cea6978f5639f312cd451019
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096160
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