Add new HAL unit common.hal.gr.init with below source files
hal/gr/init/gr_init_gm20b.c
hal/gr/init/gr_init_gm20b.h
In gr_gk20a_init_golden_ctx_image() we force FE power mode on and also
disable it. Extract out this sequence into new unit and expose new HAL
operation that takes a boolean flag to enable/disable power mode
g->ops.gr.init.fe_pwr_mode_force_on()
Use new HAL operation in gr_gk20a_init_golden_ctx_image()
Set this HAL for all the chips
Jira NVGPU-2961
Change-Id: I1dd35d94fda5e5296af67c0abc944e200fb752ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070607
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Semantics of the engine bootloader bootstrap are to set falcon mailbox0
register to non-zero value and verify that it is cleared to ascertain
successful completion of bootstrap.
Read was done in the engine bl_bootstrap related functions. Hence move
the write as well to those functions.
JIRA NVGPU-1993
Change-Id: I6d04148fbf1d517f0af8b4cfc2ee144d38704647
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034511
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To validate the imem & dmem port being accessed by nvgpu, allowed ports
need to be known from hwcfg1 register. Update the hw header with these
to use for checking the valid ports in later patch.
JIRA NVGPU-1993
Change-Id: I1146a85d452d02fefcc75065a0cd546fff688fd2
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030622
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Rename gr_reset_mutex to engines_reset_mutex and acquire it
before initiating recovery. Recovery running in parallel with
engine reset is not recommended.
On hitting engine reset, h/w drops the ctxsw_status to INVALID in
fifo_engine_status register. Also while the engine is held in reset
h/w passes busy/idle straight through. fifo_engine_status registers
are correct in that there is no context switch outstanding
as the CTXSW is aborted when reset is asserted.
Use deferred_reset_mutex to protect deferred_reset_pending variable
If deferred_reset_pending is true then acquire engines_reset_mutex
and call gk20a_fifo_deferred_reset.
gk20a_fifo_deferred_reset would also check the value of
deferred_reset_pending before initiating reset process
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: I47de669a6203e0b2e9a8237ec4e4747339b9837c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2022373
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set gr.initialized to false in the beginning of gk20a_gr_reset() and
set it to true at the end of successful execution of gk20a_gr_reset.
Use gk20a_gr_wait_initialized() to enable/disable cg/pg
functions to make sure engine is out of reset and initialized.
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: Ic7b0b71382c6d852a625c603dad8609c43b7f20f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030827
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if fecs is sent stop_ctxsw method, elpg entry/exit cannot happen
and may timeout. It could manifest as different error signatures
depending on when stop_ctxsw fecs method gets sent with respect
to pmu elpg sequence. It could come as pmu halt or abort or
maybe ext error too.
If ctxsw failed to disable, do not read engine info and just abort tsg.
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: I5f3ba07663bcafd3f0083d44c603420b0ccf6945
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2014914
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For handle_sched_error, change err to info print for failing eng
id returned as -1 i.e. FIFO_INVAL_ENGINE_ID as no engine is found
busy doing ctxsw. May be ctxsw already finished for the context
for which ctxsw timeout intr was triggered.
Possible Causes:
a)
On hitting engine reset, h/w drops the ctxsw_status to INVALID in
fifo_engine_status register. Also while the engine is held in reset
h/w passes busy/idle straight through. fifo_engine_status registers
are correct in that there is no context switch outstanding
as the CTXSW is aborted when reset is asserted.
This is just a side effect of how gv100 and earlier versions of
ctxsw_timeout behave.
With gv10b and later, h/w snaps the context at the point of error
so that s/w can see the tsg_id which caused the HW timeout.
b)
If engines are not busy and ctxsw state is valid then intr occurred
in the past and if the ctxsw state has moved on to VALID from LOAD
or SAVE, it means that whatever timed out eventually finished
anyways. The problem with this is that s/w cannot conclude which
context caused the problem as maybe more switches occurred before
intr is handled.
Bug 2092051
Bug 2429295
Bug 2484211
Bug 1890287
Change-Id: Ia79bee6e860fb179ee39024c963671d4f8245227
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030866
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ACR HS ucode self-load & bootstrap functionality was part of FB
unit to support FB mem-unlock HS ucode & this needs to access
some ACR structs which will be part of ACR private headers &
adding constraints to implement ACR unit private header support.
JIRA NVGPU-2907
Change-Id: I6c6c7504ffe55426b377e9bcf911d4005813bb31
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069724
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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struct wpr_carveout_info is used to fetch WPR info by passing
as parameter to FB HAL, changed to pass multiple params to get
WPR base & size individually from FB HAL which removes dependency
between ACR & FB.
JIRA NVGPU-2907
Change-Id: I03af1a5358fcab5dc8237899d16a0b51a6779b1f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069617
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Currenlty struct hs_acr passed to engine falcon bootstrap function
to pass falcon info to the falcon unit to execute the ACR HS bin
using engine falcon, as engine already cached the falcon info as
part its structure so removed struct hs_acr parameter pass.
JIRA NVGPU-2907
Change-Id: I0b647b2763c52e97de0c17cfdd273486138ee404
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069593
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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The functions gk20a_dump_eng_status and gv11b_dump_eng_status belongs
to engine_status HAL unit.
1) The corresponding declaration and definitions of the above functions
are moved from fifo_{arch} files to engine_status_{arch} files.
2) The corresponding HAL pointer .dump_eng_status is moved from
fifo to engine_status HAL unit.
3) gv11b_dump_eng_status is now based to gv100b_dump_eng_status
4) Small changes in the files for ENGINE_STATUS such as correction of
HEADER DEFINES etc
Jira NVGPU-1315
Change-Id: I7fc06eab97206bc3b78c6f5c7aa30fa2c034961c
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033632
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The corresponding HAL pointer for gk20a_fifo_wait_engine_idle is not
being invoked anywhere and hence they are removed from the code.
The function gk20a_fifo_wait_engine_idle belongs to engine unit and is
only called in a non-safe build, hence its moved to engine unit and is
restricted by a non-safe build flag NVGPU_ENGINE
Also, gk20a_fifo_wait_engine_idle is renamed to nvgpu_engine_wait_for_idle
Jira NVGPU-1315
Change-Id: Ie550c7e46a4284dfe368859d828b1994df34185f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033631
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The following functions belong to engine unit and are moved
gk20a_fifo_enable_engine_activity
gk20a_fifo_enable_all_engine_activity
gk20a_fifo_disable_engine_activity
gk20a_fifo_disable_all_engine_activity
These are renamed by replacing gk20a_fifo with nvgpu_engine as prefix.
These functions are only invoked by linux build and not required for
safety build and hence they are defined when
-DNVGPU_ENGINE is enabled.
Jira NVGPU-1315
Change-Id: I39d820879bb55b40e754526c657d794930a4b6a1
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032606
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common.fifo.engine unit has both safe as well as non-safe functions.
The build flag NVGPU_ENGINE is used to restrict the use of
non-safe functions of the engine unit in safety builds.
Jira NVGPU-1315
Change-Id: Ic363ad547e07136024a254c078fdf0194fafc265
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2032605
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is_fault_engine_subid_gpc HAL pointer belongs to engine HAL unit instead of
fifo. This patch moves the HAL pointer to a newly constructed engine
HAL unit.
The following new files are added under HAL/fifo/
engines_gm20b.h
engines_gm20b.c
engines_gv11b.h
engines_gv11b.c
Jira NVGPU-1315
Change-Id: If28686bf7350563b06b13348a9fe3ef0099c35b2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2031659
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Pre-volta, cbc config is part of hw ltc and from volta onwards this is
moved to hw fb. Because of this, cbc_init functions are present in both
cbc unit and fb unit. Pre-volta uses cbc_init from cbc unit and from
volta onwards it uses cbc_init from fb unit.
With this patch, unified two cbc_init functions to cbc unit and created
new fb hal for cbc_configure. cbc unit uses fb hal for cbc_config and
fb unit is independent of cbc unit.
JIRA NVGPU-2897
Change-Id: Ib62f0b08547b031bcb5011c837e43c74931a22fe
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030906
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Create Compression Bit Cache(CBC) unit to have comptags
cache related functionality in one place. In this patch
Moved following gpu ops from ltc to cbc and renamed accordingly:
void (*init)(struct gk20a *g, struct gr_gk20a *gr);
u64 (*get_base_divisor)(struct gk20a *g);
int (*alloc_comptags)(struct gk20a *g, struct gr_gk20a *gr);
int (*ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max);
u32 (*fix_config)(struct gk20a *g, int base);
To avoid ambiguity renamed function pointer from
init_comptags to alloc_comptags.
Moved following function from ltc.h to cbc.h:
nvgpu_ltc_alloc_cbc -> nvgpu_cbc_alloc
Also changed file name that implemented
nvgpu_cbc_alloc functionality from
os/ltc.c -> os/linux-cbc.c
JIRA NVGPU-2897
Change-Id: Ide32a98567e9a3f0a784d62221a6f484f8343e53
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030194
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In case of FBPA we need to consider mask of active FBPAs on dGPUs.
For that we have GR unit HAL g->ops.gr.add_ctxsw_reg_pm_fbpa()
Generic support to consider active mask of unit need not be in a HAL,
move it to common code in add_ctxsw_buffer_map_entries_subunits() itself
This API now supports providing active_unit_mask as its parameter
In case we don't need to consider unit mask caller will simply pass
~U32(0U) to indicate all units are active
In case of FBPA, add a new HAL g->ops.gr.hwpm_pm.get_active_fbpa_mask()
which gets mask of active FBPAs, and pass this value to common API
add_ctxsw_buffer_map_entries_subunits()
Jira NVGPU-2895
Change-Id: I0d208ce53abcd36929c25a4d248868d6eaa5c70d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069472
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Create a new HAL unit hal.gr.hwpm_map that provides chip specific
support to common.gr.hwpm_map unit
We currently have common.gr HAL g->ops.gr.add_ctxsw_reg_perf_pma()
to handle chip specific alignment of perf_pma list
We only adjust the offset of list and remaining code is same
Hence delete above HAL, and add new HAL under hal.gr.hwpm_map
g->ops.gr.hwpm_map.align_regs_perf_pma() which returns correct
alignment if HAL is defined
Remove gr_gv100_add_ctxsw_reg_perf_pma() and
gr_gk20a_add_ctxsw_reg_perf_pma() APIs since they are no longer used
Simplify perf_pma parsing by fixing alignment with new HAL and then
directly calling add_ctxsw_buffer_map_entries()
Jira NVGPU-2895
Change-Id: I1852db846e1f5441e482028c79a3f39c5142b0c2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069471
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In gr_gv100_get_active_fpba_mask(), we directly access top_* register
from hw_top_gv100.h h/w header to read FBPA count.
Add a new HAL in TOP unit to return max FBPA count
g->ops.top.get_max_fbpas_count()
Use this HAL in gr_gv100.c to get FBPA count and remove direct access
of top_* register, and also remove hw_top_gv100.h header include
Jira NVGPU-2895
Change-Id: Idfba553b24d7d6abf124a84b1490987e8cbf1985
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069470
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Currently, in nvgpu_aperture_mask_raw function, if NVGPU_MM_HONORS_APERTURE
flag is disabled, invalid or junk aperture input is changed to APERTURE_VIDMEM
instead of raising a warning.To resolve this bug, need to check if input
aperture is APERTURE_INVALID or undefined.
This patch adds APERTURE_MAX_ENUM to nvgpu_aperture structure which
gives upperbound of nvgpu_aperture types. This patch also adds condition in
nvgpu_aperture_mask_raw function to check for invalid or undefined aperture
input. For invalid inputs, function will BUG().
Jira NVGPU-2933
Change-Id: Ic9d260250e3083d693f025c6e32657f6a863aafb
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034281
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Move the code involved in dealing with minion into a separate unit
called "nvlink_minion". This unit includes minion HW access, ucode
handling, exposing state of minion and also dealing with minion
interrupts. The interfaces to this unit are partially exposed using
g->ops.nvlink.minion ops and rest are part of nvlink_minion.h public
header.
JIRA NVGPU-2860
Change-Id: Iea9288ea5f0b26688540b1eb8ab64afd756941a4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030103
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gk20a_ctxsw_trace_init() is defined in linux specific code, but it is
right now being called from common functions gk20a_finalize_poweron()
and vgpu_finalize_poweron_common() in common code
Move this call to linux specific common function
nvgpu_finalize_poweron_linux() instead
Jira NVGPU-1880
Change-Id: I2548683f1a0378194ff5dd84c94936ccf0f9d17b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069474
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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Loading of ctx/method init values from NET image is done in GR boot
sequence and also in golden image creation
Doing this during GR boot creation is unnecessary since those writes
are anyways part of golden image itself
Hence remove those method loads from gk20a_init_gr_setup_hw()
Also remove g->ops.gr.commit_global_timeslice() call since that too
is covered during golden image creation
Since above code is removed disabling and restoring fe_go_idle timeout
is also not needed
Jira NVGPU-1885
Change-Id: Ic6eb4bea7ceb36bb1420f58446785cefe25066df
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034042
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Add new power/clock gating functions that can be called by
other units.
New clock_gating functions will reside in cg.c under
common/power_features/cg unit.
New power gating functions will reside in pg.c under
common/power_features/pg unit.
Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.
Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.
JIRA NVGPU-2014
Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
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These tests implement the pd_cache requirement verification tests for
all pd_cache requirements and test specifications. They cover:
o PD GPU address computation
o PD offset computation
o Init
o Multiple inits
o Cleanup*
[*] the cleanup needs some more POSIX memory API support: we need a way
to make sure that all outstanding allocations are freed.
JIRA NVGPU-1323
Change-Id: If6398ad09c9d38f5ac2fdad057bb933f88224599
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2034273
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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