gv11b_mm_l2_flush was not checking error codes from the various
functions it was calling. MISRA Rule-17.7 requires the return value
of all functions to be used. This patch now checks return values and
propagates the error upstream.
JIRA NVGPU-677
Change-Id: I9005c6d3a406f9665d318014d21a1da34f87ca30
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998809
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Add new hal to log the mme exception register information. Support
added for Turing only. On mme exception interrupt, read the
mme_hww_esr register and log the error based on esr register bits.
JIRA NVGPU-1241
Change-Id: Ied3db0cc8fe6e2a82ecafc9964875e2686ca0d72
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2005807
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MISRA Rule 10.1 states that operands shall not be of an inappopriate
essential type. For example, shift and bitwise operations should only
be performed on operands of essentially unsigned type.
This patch modifies gr exception handling to no longer use bitwise OR
when generating return status values.
Instead, the first non-zero status value is saved off and returned.
This has the added benefit of not potentially ORing together errno
values and generating an undefined status code.
JIRA NVGPU-650
Change-Id: If725a560c122d2cbf12e79b58161402da2023b5b
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1999098
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Move regops (gk20a/regops_gk20a.c) to separate unit common/regops/regops.c
Move corresponding header (gk20a/regops_gk20a.h) to include/nvgpu/regops.h
Move rest of the platform HAL files to common/regops/ as well
Fix all the header includes to include new public header
Remove *_apply_smpc_war() declarations from headers. Corresponding
functions were cleaned up already, and declarations were left somehow
Jira NVGPU-620
Change-Id: I8b8065b9c91f69809bdeb1b4caecdc7582c8a992
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1998723
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gk20a_remove_gr_support() is freeing the local_golden_image and
local_golden_image->context. But there are instances where
local_golden_image is not allocated since freeing an
unallocated golden context image accesses the contents of
local_golden_image causes a fault.
Check golden_image_initialized flag before freeing
local_golden_image->context.
Jira NVGPU-1648
Bug 2461665
Change-Id: I19235d2ec9d77ba4ef00257f43436448f5f70b25
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1997665
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We use below APIs to update patch context
gr_gk20a_ctx_patch_write_begin()
gr_gk20a_ctx_patch_write_end()
gr_gk20a_ctx_patch_write()
Since patch context is owned by gr/ctx unit, move these APIs
to this unit and rename them to
nvgpu_gr_ctx_patch_write_begin()
nvgpu_gr_ctx_patch_write_end()
nvgpu_gr_ctx_patch_write()
Jira NVGPU-1527
Change-Id: Iee19c7a71d074763d3dcb9b1997cb2a3159d5299
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989214
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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We currently load and create new graphics context image in
gr_gk20a_load_golden_ctx_image()
This API will first load local golden image in new context
image and then initialize context appropriately by calling
g->ops.gr.ctxsw_prog() HALs
Move this sequence to gr/ctx unit and rename the API as
nvgpu_gr_ctx_load_golden_ctx_image()
Note that call to g->ops.gr.update_ctxsw_preemption_mode()
is moved out of this API and called directly from
gk20a_alloc_obj_ctx()
Jira NVGPU-1527
Change-Id: Id5a5b2cd2c0704fbefe536d581a37a60ec185ea9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1989157
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Currently all the global contex buffers are mapped into each graphics
context. Move all the mapping/unmapping support to gr/ctx unit since
all the mappings are owned by context itself
Add nvgpu_gr_ctx_map_global_ctx_buffers() that maps all the global
context buffers into given gr_ctx
Add nvgpu_gr_ctx_get_global_ctx_va() that returns VA of the mapping
for requested index
Remove g->ops.gr.map_global_ctx_buffers() since it is no longer
required. Also remove below APIs
gr_gk20a_map_global_ctx_buffers()
gr_gk20a_unmap_global_ctx_buffers()
gr_tu104_map_global_ctx_buffers()
Remove global_ctx_buffer_size from nvgpu_gr_ctx since it is no
longer used
Jira NVGPU-1527
Change-Id: Ic185c03757706171db0f5a925e13a118ebbdeb48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987739
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Add new unit common/gr/ctx.c to manage GR context
This unit provides interfaces to allocate/free/map/unmap GR context,
patch context, pm context, ctxsw {preempt/spill/betacb/pagepool/rtvcb}
buffers.
It also provides APIs to set size of above buffers
Add new header file include/nvgpu/gr/ctx.h to declare all the interfaces.
Move nvgpu_gr_ctx, patch_desc, pm_ctx_desc, zcull_ctx_desc structures
to this unit
Add new structure nvgpu_gr_ctx_desc to hold context description
parameters. For now we add sizes of all the buffers here.
Add this structure to gr_gk20a for global reference
Remove gr_gp10b_alloc_buffer() since it is no longer used
Rename g->ops.gr.alloc_gfxp_rtv_cb() to g->ops.gr.init_gfxp_rtv_cb()
since this HAL now only sets the size of rtvcb ctxsw buffer
Remove gr->ctx_vars.buffer_size and gr->ctx_vars.buffer_total_size
since they were redundant. We already have gr->ctx_vars.golden_image_size
to denote golden image size
Jira NVGPU-1527
Change-Id: I8847b347f80235209dd5e28d979e79984ab85408
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1987702
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Local golden image is copy of global GR context buffer hence move its
ownership to global context unit
Add new structure nvgpu_gr_global_ctx_local_golden_image to hold all meta
data for local golden image and move it to struct gr_gk20a
Expose and use new APIs to initialize/deinitialize and load local golden image
Jira NVGPU-1625
Change-Id: Ieb68e52c205ca0ecd27f8bf4bb31922a01e7ae54
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1984952
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MISRA rule 10.1 mandates that the correct data types are used as
operands of operators. For example, only unsigned integers can be used
as operands of bitwise operators.
This patch fixes rule 10.1 vioaltions for gk20a.
JIRA NVGPU-777
JIRA NVGPU-1006
Change-Id: I965eae017350156c6692fd585292b7a54e4190d8
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971010
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Current code creats golden image using dedicated gr_ctx called
GOLDEN_CTX. But on RM server it's no easy to create a GOLDEN_CTX since
virtual addresses are managed by guest OSes. There's no special reason
why we have to use a separate gr_ctx for golden image. This patch moves
it to use current channel gr_ctx. And the function will be re-useable
by RM server.
Jira GVSCI-191
Change-Id: I9920703e61f7e1d8b3ad6612811e47a3815d0c0f
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983702
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OS specific implementation of fecs trace bind_channel function
needs to handle special case for vserver to retrieve vmid from
channel id. Native code should be independent of server code.
Modify struct fecs_trace member function bind_channel to pass
vmid parameter enabling retrieving and passing vmid from server
code.
Jira GVSCI-44
Change-Id: I96223376f2068e2cbf60a9c9b35ff564a65e5dc3
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970693
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With intention to make falcon header free of private data we are making
all falcon struct members (pmu.flcn, sec2.flcn, fecs_flcn, gpccs_flcn,
nvdec_flcn, minion_flcn, gsp_flcn) in the gk20a, pointers to struct
nvgpu_falcon. Falcon structures are allocated/deallocated by
falcon_sw_init & _free respectively.
While at it, remove duplicate gk20a.pmu_flcn and gk20a.sec2_flcn,
refactor flcn_id assignment and introduce falcon_hal_sw_free.
JIRA NVGPU-1594
Change-Id: I222086cf28215ea8ecf9a6166284d5cc506bb0c5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1968242
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Add new unit common/gr/global_ctx.c to manage GR global context buffers
This unit provides interfaces to allocate/free/map/unmap all the global
context buffers. It also provides APIs to get/set size of the buffers,
and to get memory handle of the buffers
Use interfaces exposed by this unit instead of directly accessing global
context buffers in common code
Add new header file include/nvgpu/gr/global_ctx.h to declare all the
interfaces.
Rename "struct gr_ctx_buffer_desc" to "struct nvgpu_gr_global_ctx_buffer_desc"
which holds all data for each global context
Remove void *priv since it is no longer used
Add size to the desc structure to store the requested size
Remove global_ctx_buffer_size from struct nvgpu_gr_ctx since it is no longer
used for any real purpose
Jira NVGPU-1625
Change-Id: I3feaf47bc2fdf192f36b136f2ef80a49d1782c5d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1977884
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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In gk20a_gr_handle_fecs_error(), we right now check the error code in
mailbox to identify if we hit timestamp buffer full error interrupt
This error code right now is hard coded to 0x26
But on Turing ucode this error code is set to 0x32
Add new HAL g->ops.fecs_trace.get_buffer_full_mailbox_val() to get
correct error code per platform and use this in
gk20a_gr_handle_fecs_error()
Bug 200471541
Bug 2469604
Change-Id: I7325354b39d35b1c8b218e554814316d22950469
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978144
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g->ops.gr.alloc_gr_ctx HAL right now allocates graphics context and
also initializes preemption mode for various platforms
Separate out a new HAL g->ops.gr.init_ctxsw_preemption_mode that
initializes preemption mode and call it from gk20a_alloc_obj_ctx()
after context is created
g->ops.gr.alloc_gr_ctx now only allocates the context as the name
suggests
Jira NVGPU-1527
Change-Id: I8a44672d5ab2ebfe315e6334115265e4ee4f24f0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972254
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g->ops.gr.enable_cde_in_fecs and g->ops.gr.update_boosted_ctx
are no longer required since we can directly call
g->ops.gr.ctxsw_prog.set_cde_enabled and
g->ops.gr.ctxsw_prog.set_pmu_options_boost_clock_frequencies
respectively
remove those functions and the ops
Jira NVGPU-1526
Change-Id: Idb0ad5f634e78aac44ec325ba2b7f59c612b29e8
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972184
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GPCCS falcon base address was being set without invoking hal api. Remove
FALCON_GPCCS_BASE. This patch defines gpu_ops.gr.gpccs_falcon_base_addr
hal api to get this base address.
JIRA NVGPU-1587
Change-Id: Icfa7a26d1bb2d67c81f05a43f6ce906f59706b3d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969431
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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FECS falcon base address was being set without invoking hal api. Remove
FALCON_FECS_BASE. This patch defines gpu_ops.gr.fecs_falcon_base_addr hal
api to get this base address.
JIRA NVGPU-1587
Change-Id: I9c8e60be4ee81a154020c982893725a12ebb72ef
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969430
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Add separate new unit gr/ctxsw_prog that provides interface to access
h/w header files hw_ctxsw_prog_*.h
Add below chip specific files that access above h/w unit and provide
interface through g->ops.gr.ctxsw_prog.*() HAL for rest of the units
common/gr/ctxsw_prog/ctxsw_prog_gm20b.c
common/gr/ctxsw_prog/ctxsw_prog_gp10b.c
common/gr/ctxsw_prog/ctxsw_prog_gv11b.c
Remove all the h/w header includes from rest of the units and code.
Remove direct calls to h/w headers ctxsw_prog_*() and use HALs
g->ops.gr.ctxsw_prog.*() instead
In gr_gk20a_find_priv_offset_in_ext_buffer(), h/w header
ctxsw_prog_extended_num_smpc_quadrants_v() is only defined on gk20a
And since we don't support gk20a remove corresponding code
Add missing h/w header ctxsw_prog_main_image_pm_mode_ctxsw_f() for
some chips
Add new h/w header ctxsw_prog_gpccs_header_stride_v()
Jira NVGPU-1526
Change-Id: I170f5c0da26ada833f94f5479ff299c0db56a732
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966111
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If enabled, fecs trace updating happens from ucode
side even when there is no fecs trace dumper application
to consume it. Due to this, trace buffer will get
eventually full and ucode will trigger ctxsw_intr0.
Reset fecs_trace buffer to handle timestamp buffer full
ctxsw_intr0.
Bug 2361571
Bug 200472922
Change-Id: Ia26a17635fc6bd6e8663b8af983acc91839ecfcd
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965370
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ctxsw_intr0 is triggered by ucode even if it
is not enabled by driver. Add handling
for processing ctxsw_intr0. fecs mailbox(6)
is used to report fecs/gpccs misc error codes.
Also dump falcon stats for unhandled fecs intr.
Bug 2361571
Bug 200472922
Change-Id: Iefb3c0d46ad1d08db07fd3c08cff91a77835908c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1966984
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MISRA Rule 10.3 states that the value of an expression shall not
be assigned to an object with a narrower essential type or of a
different esseential type category.
For example, assigning an unsigned 32bit value (u32) to a signed
32bit value (int) is not permitted.
This patch modifies the gr_gk20a_init_golden_ctx_image() and
gk20a_init_sw_bundle() routines to use an int (instead of u32)
for return status handling making them consistent with the other
gr routines used in this part of the gr object allocation path.
JIRA NVGPU-647
Change-Id: I53c47d9a169bd0d4cdbce107bd4ad8e7978ae01d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1965735
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
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Add gk20a_channel_from_id() to retrieve a channel, given a raw channel
ID, with a reference taken (or NULL if the channel was dead). This makes
it harder to mistakenly use a channel that's dead and thus uncovers bugs
sooner. Convert code to use the new lookup when applicable; work remains
to convert complex uses where a ref should have been taken but hasn't.
The channel ID is also validated against FIFO_INVAL_CHANNEL_ID; NULL is
returned for such IDs. This is often useful and does not hurt when
unnecessary.
However, this does not prevent the case where a channel would be closed
and reopened again when someone would hold a stale channel number. In
all such conditions the caller should hold a reference already.
The only conditions where a channel can be safely looked up by an id and
used without taking a ref are when initializing or deinitializing the
list of channels.
Jira NVGPU-1460
Change-Id: I0a30968d17c1e0784d315a676bbe69c03a73481c
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1955400
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MISRA Rule 21.15 prohibits use of memcpy() with incompatible ptrs to
qualified/unqualified types.
To circumvent this issue we've introduced a new MISRA-compliant
nvgpu_memcpy() function.
This change switches over non-offending memcpy() uses in gr/pmu/volt
code to nvgpu_memcpy() with appropriate casts applied to maintain
consistency within the nvgpu source base.
Also fixed a Rule 8.3 violation in vfe_var.c by sync'ing the param
names between declarations of the devinit_get_vfe_var_table()
routine.
JIRA NVGPU-849
Change-Id: I004b461988bd3a26212b6fbf660ee7fa742ea1ba
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1952984
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The return type of the function pointer *calc_global_ctx_buffer_size()
is changed from int to u32 and all its implementations.
The arg type of size in *set_big_page_size() is changed from int to
u32 and all it implementations. These changes are necessary because
size should be an unsigned value.
JIRA NVGPU-992
Change-Id: I3e4cd1d83749777aa8588a44a48772e26f190c4d
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1950503
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Adeel Raza <araza@nvidia.com>
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Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.
Also pass the channel vm and vpr flag instead of the whole channel as
only those are needed.
Jira NVGPU-1149
Change-Id: Ic0921ccaf65f208105b25f08f8d7b581a56b40fe
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925431
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Simplify object ownership by passing the gr_ctx around directly instead
of reading from tsg via a channel; the caller holds the gr_ctx already.
Also pass the channel vm instead of the whole channel.
Jira NVGPU-1149
Change-Id: Id9d65841f09459e7acfc8c4ce4c6de7db054dbd8
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1925427
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