Add nvgpu macro for pthread API pthread_cleanup_pop(0). The argument
zero would mean that the thread cancellation cleanup handler which is
pushed onto the thread's stack using pthread_cleanup_push() will not
get executed.
JIRA NVGPU-5110
Change-Id: I89a45ccccd8709685f487513bf99d622a82ed891
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307977
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Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
qnx unit test access ucode from /proc/boot/gv11b. QNX Unit test face
issues like permission, platform dependency etc when test tries to
access ucode from /proc/boot. To fix issue updating qnx firmware unit
to read ucode from firmware/gv11b in case of unit test. Patch also
updates firmware access path for posix as well.
Jira NVGPU-3582
Bug 2693908
Change-Id: I1b28c8475b6bc4fe5ec3d6a525cb3af152feb887
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306278
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Some of the APIs that access debugger register are not protected
from ELPG. This might trigger PRI access timeouts for corresponding
registers if GR engine is power gated.
Add nvgpu_pg_elpg_protected_call() to protect against ELPG.
Bug 2820066
Change-Id: I467ea28aaea1c0e36c2d6aabce6a2daea6ee9911
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306383
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Previously, nvgpu_sw_quiesce_remove_support() stopped the quiesce
thread abruptly with nvgpu_thread_stop(), which could mean the thread
was killed while still waiting on the cond. Then when the cond was
destroyed, there may be an error since the underlying implementation may
think there is still a thread waiting (such as the Posix
implementation).
Change nvgpu_sw_quiesce_remove_support() to use
nvgpu_thread_stop_graceful() and signal the cond in the callback after
the thread is marked to be stopped. The quiesce thread will then wake up
from the cond wait and see the thread should stop.
JIRA NVGPU-4987
Change-Id: I29322d7867acc33a91092016c540e00bb1ae945a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306024
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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Linux kernel has a default 32-bit segmentation boundary for
any device that doesn't explicitly configure it. When nvgpu
tries to allocate a larger memory > 4GB, iommu_dma_map_sg()
function in the kernel will take this boundary into account
and add an internal padding to the allocated IOVA space:
|<---IOVA space 1--->|<---padding--->|<---IOVA space 2--->|
When DMA reads/writes the memory using this discountinued
IOVA space, it may end up with accessing the padding part,
instead of the IOVA space 2.
So this patch adds dma_set_seg_boundary() to nvgpu driver,
by maximizing the segmentation boundary up to DMA_BIT_MASK
to ensure a continued IOVA space.
Bug 200558567
Change-Id: I979d56681dddca56f1b02fce83dc81147a6b0d82
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304150
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Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:
SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI
Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.
Bug 2834141
Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
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MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change eliminates such a violation in the posix implementation
of nvgpu_thread_cleanup_pop().
Jira NVGPU-3178
Change-Id: I2ad363b4d60c321fa20b23c167d783bebaceb7d3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In gm20b_channel_bind an nvgpu_smp_wmb() was used presumably to
prevent MMIO writes from being re-ordered after the memory write
to 'ch->bound'. If that was to happen, then unbind routine could
observe the channel as bound and issue concurrent MMIO writes
to unbind the channel. Assuming, the barrier was to prevent
such race, it should have been an nvgpu_wmb(), since
nvgpu_smp_wmb() is for inner shareable domain only.
However, the race possibility between unbind called from close
path and bind from ALLOC_GPFIFO should be ruled out because
close will wait for any active devctl/ioctl to finish before
proceeding.
The race possibility between unbind called from
suspend_all_serviceable_ch path and bind from ALLOC_GPFIFO should
be ruled out because ALLOC_GPFIFO has power refcount at the start
of devctl/ioctl and suspend_all_serviceable_ch is called from
prepare_poweroff path which ensure that power refcount is 0.
Removed nvgpu_smp_wmb().
Jira NVGPU-4927
Change-Id: Ic4f072df364926c10be84e42b83394c13fc97fdc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298959
Reviewed-by: Automatic_Commit_Validation_User
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In the upstream kernel ACCESS_ONCE is now deprecated with reason as
given in the following related commit:
commit 381f20fceba8e ("security: use READ_ONCE instead of deprecated
ACCESS_ONCE")
ACCESS_ONCE() does not work reliably on non-scalar types. For
example gcc 4.6 and 4.7 might remove the volatile tag for such
accesses during the SRA (scalar replacement of aggregates) step.
Replace usages of ACCESS_ONCE with READ_ONCE and WRITE_ONCE in nvgpu.
Bug 2834141
Change-Id: I9904c49e1a4d7b17ed2fe54360051d08595a2982
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294096
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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Implmented functions to load and execute PUB which
is the safety POR.
PUB has following functionality:
1) Lower PLM
2) Reset PMU
3) FBPA register access to devtools
Secure Boot and Runtime (SBR) microcode comprises of
single PLM Update Binary (PUB) which will execute on
SEC2 Engine Falcon. NVGPU shall load and execute PUB
and wait for falcon halt. On successful halt NVGPU
shall proceed with ns ucode loading on respective
falcons.
NVGPU-4549
Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330
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Current clk unit has multiple header files under include folder.
This has combination of public struct which is accessed outside the
unit and private struct which is accessed within clk unit.
This patch segregates them based on their accessibility.
All private items are moved into ucode_clk_inf.h from include which only
clk can access.
All public items are moved into include/clk.h which other units can
access and removed the clk_xxx.h files
NVGPU-4689
Change-Id: I469270ae539e09a3f6fe6187207791732407863e
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298220
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This is fixing the following misra violation
MISRA 5.1 :
Declaration with identical names.
The first 31 characters of identifiers
"nvgpu_nvhost_syncpt_unit_interface_get_aperture" and
"nvgpu_nvhost_syncpt_unit_interface_get_byte_offset" are identical.
JIRA NVGPU-4811
Change-Id: Ib862c4acd53cf748b47c1edffa91b5f033c08953
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298136
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Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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