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Author SHA1 Message Date
Deepak Nibade
d7971e7444 gpu: nvgpu: add DGPU config for RTV circular buffer 
RTV circular context buffer is only supported on TU104 dGPU as of
now. Hence compile out corresponding #define and code from safety build.

Jira NVGPU-4373

Change-Id: I46a3efc92fb247fa08efb925447c248b2a4b9a57
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255768
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Vedashree Vidwans
4f45ec7d5f gpu: nvgpu: unit: mm: flush_gk20a_fusa unit test 
This unit test covers most of the nvgpu.hal.mm.cache.flush_gk20a_fusa
module lines and almost all branches.

Jira NVGPU-2218

Change-Id: I1c090a301a7d1fddb675248287e7d4c7b9da0538
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248084
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
0c3a963275 gpu: nvgpu: update on gr.ecc subunit code 
Change a check from CONFIG_NVGPU_NON_FUSA to CONFIG_NVGPU_DGPU
as the gpccount is more than 1 for DGPU and this code need to be
executed for DGPU.

Jira NVGPU-4460

Change-Id: I806c926cd787c787ac8a04f998602edcae5419b8
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257036
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
01039aec35 gpu: nvgpu: disable unused compute sw method for safety 
Add missing check with CONFIG_NVGPU_HAL_NON_FUSA in tu10x
code for NVC0C0_SET_SHADER_EXCEPTIONS.

Jira NVGPU-4454

Change-Id: Id8f0560c5061f7c017c84361059007d936dc53b5
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257034
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
23bbce1102 gpu: nvgpu: unit: add tests for gv11b fifo HAL 
Add unit tests for the following HALs:
- gv11b_init_fifo_reset_enable_hw
- gv11b_init_fifo_setup_hw
- gv11b_fifo_mmu_fault_id_to_pbdma_id
- gv11b_fifo_intr_0_enable
- gv11b_fifo_handle_sched_error
- gv11b_fifo_intr_0_isr
- gv11b_fifo_intr_set_recover_mask
- gv11b_fifo_intr_unset_recover_mask

Jira NVGPU-4386

Change-Id: I888aca62e8eb8223a1def693a5ed51500baa37fc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256265
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
4c43d83032 gpu: nvgpu: unit: add tests for gk20a fifo HAL 
Add unit tests for the following HALs:
- gk20a_fifo_init_pbdma_map
- gk20a_fifo_get_runlist_timeslice
- gk20a_fifo_get_pb_timeslice
- gk20a_fifo_intr_1_enable
- gk20a_fifo_intr_1_isr
- gk20a_fifo_intr_handle_chsw_error
- gk20a_fifo_intr_handle_runlist_event
- gk20a_fifo_pbdma_isr

Jira NVGPU-4386

Change-Id: Iab518e3bc3f8fabdfb32172db8de300dd4142a53
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256264
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
a7656276ae gpu: nvgpu: recover ctxsw timeout only for kernel submit 
Context switch timeout is checked only when
CONFIG_NVGPU_KERNEL_MODE_SUBMIT is defined. Hence move
context switch timeout recovery case to the same #ifdef,
to avoid dead code in safety build.

Jira NVGPU-3400

Change-Id: I23176b3bd5cd6fd1346c7aabd327dcc4f340c9ac
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254331
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Tested-by: Sagar Kadamati <skadamati@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
5a17ccb83f gpu: nvgpu: unit: test coverage for gr.ecc unit 
Add more test for line/branch coverages in gr.ecc
common and fusa code.
Max gpc_count is one for gv11b, add a checking under
CONFIG_NVGPU_NON_FUSA to avoid unwanted error handling.

Jira NVGPU-4460

Change-Id: Ifac53394ebe58698b81e1e108731ccc36d624ff3
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256451
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
22dea4ca3b gpu: nvgpu: disable unused compute sw method in safety build. 
NVC0C0_SET_SHADER_EXCEPTIONS is never used by CUDA software. Hence disable that
feature with CONFIG_NVGPU_HAL_NON_FUSA checking for safety build.

Jira NVGPU-4454

Change-Id: If71b97bf8b2a6a8f8d0c7206b8e801094b5b1b7c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256345
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Philip Elcan
76adb91f60 gpu: nvgpu: unit: add CE unit test 
Add unit test for the common.ce unit and the gv11b CE FUSA HALs.

JIRA NVGPU-930

Change-Id: Idee75a1a5b53d397047edbead0db68ae999ce640
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255473
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 2020-12-15 14:10:29 -06:00
dinesh
9de3872c5a gpu: nvgpu: Add qnx message posix fault injection 
This is adding fault injections for some qnx message passing
functions.

JIRA NVGPU-4409

Change-Id: I84c01c4f191efea549f72dd9b8402a2f88c0fd2f
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254462
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
42feb5e21f gpu: nvgpu: unit: update valid classes for safety 
VOLTA_A class is not a valid class for safety. So moved
this class from valid class list to invlaid class list.

JIRA NVGPU-4314

Change-Id: Iea2f655628aaf31f9067a705919869174facfc91
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255325
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Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Seshendra Gadagottu
ad3cf4e79a gpu: nvgpu: disable graphics class support for safety build 
Disabled graphics class support for safety build.

JIRA NVGPU-4314

Change-Id: I72ea732263f1777cb19fffa0c0128deeb435efa6
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2233581
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 2020-12-15 14:10:29 -06:00
Philip Elcan
3d202fcceb gpu: nvgpu: unit: ltc: add test for flush_ltc HAL 
Add test for gm20b_flush_ltc HAL.

JIRA NVGPU-2219

Change-Id: Idf1e658ac06207b74dbec0ebd2234adc458282be
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255350
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 2020-12-15 14:10:29 -06:00
Philip Elcan
882cf68562 gpu: nvgpu: unit: add fault injection for timer init 
Add fault injection handling for the nvgpu_timeout_init() API.

JIRA NVGPU-2219

Change-Id: I0c3ba06d3726e87d1097e695698124ffabc68ab9
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255353
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
feeb978c91 gpu: nvgpu: unit: define required pbdma HAL tests 
Update JSON file with list of required pbdma HAL tests.

Jira NVGPU-3694

Change-Id: I9b6487a124ebac5de8d7d04999dcf76b4163a61d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254417
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
24210bdbc9 gpu: nvgpu: unit: add tests for gp10b pbdma HAL 
Add unit tests for the following HALs:
- gp10b_pbdma_get_signature
- gp10b_pbdma_get_fc_runlist_timeslice
- gp10b_pbdma_get_config_auth_level_privileged

Jira NVGPU-3694

Change-Id: I672acc76490db358951b31c1231fb8542852dfee
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253635
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
7b1f5a327f gpu: nvgpu: unit: add tests for gm20b pbdma HAL 
Add tests for the following HALs:
- gm20b_pbdma_acquire_val
- gm20b_pbdma_handle_intr
- gm20b_pbdma_read_data
- gm20b_pbdma_reset_header
- gm20b_pbdma_device_fatal_0_intr_descs
- gm20b_pbdma_restartable_0_intr_descs
- gm20b_pbdma_format_gpfifo_entry
- gm20b_pbdma_get_gp_base
- gm20b_pbdma_get_gp_base_hi
- gm20b_pbdma_get_fc_subdevice
- gm20b_pbdma_get_userd_aperture_mask
- gm20b_pbdma_get_userd_addr
- gm20b_pbdma_get_userd_hi_addr

Jira NVGPU-3694

Change-Id: I3d97f2e70d6c364d673a4f231ff1a3fad349c14e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253634
GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
ecab3ddbce gpu: nvgpu: unit: add tests for gv11b pbdma HAL 
Add tests for the following HALs:
- gv11b_pbdma_setup_hw
- gv11b_pbdma_intr_enable
- gv11b_pbdma_handle_intr_0
- gv11b_pbdma_handle_intr_1
- gv11b_pbdma_channel_fatal_0_intr_descs
- gv11b_pbdma_get_fc_pb_header
- gv11b_pbdma_get_fc_target
- gv11b_pbdma_set_channel_info_veid
- gv11b_pbdma_config_userd_writeback_enable

Jira NVGPU-3694

Change-Id: Ieea746e07cae4a3c1b5289674d93654edf7de941
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253633
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
59c740cf6a gpu: nvgpu: fix SWUTS path for common.pbdma 
Fix SWUTS reference for common.pbdma.
Fix #ifdef for include file.

Jira NVGPU-3490

Change-Id: I115b3cd8efd14ee6f50efd725c244c80cb8c2bea
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253632
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
9191461a6a gpu: nvgpu: rename set_channel_info_veid parameter 
gops_pbdma.set_channel_info_veid takes a subctx_id (i.e. veid),
not a channel_id.
Renamed parameter to subctx_id.

Jira NVGPU-3694

Change-Id: If64d06b1041fd42b6a0fcaf6bbb30e156235fa54
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253631
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 2020-12-15 14:10:29 -06:00
Thomas Fleury
64b0794ab8 gpu: nvgpu: fix precision for acquire_val 
In gm20b_pbdma_acquire_val, use a single multiply operation to
convert to ns and apply 80% factor, for improved precision.

Jira NVGPU-3694

Change-Id: I5be3c5455ba53eccfadbb8c8678f28d0cf36e867
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253630
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:10:29 -06:00
Lakshmanan M
a52ee77837 gpu: nvgpu: Add SM diversity gpu characteristic flag 
To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute
on different hardware resources.
This feature requires a change in software to make it possible
to modify the virtual SM id to TPC mapping across mission and
redundant contexts.

This CL adds only SM diversity flags which are exposed to
its clients through ioctl/devctl interfaces.
Actual virtual SM id to TPC mapping implementation
will be part of upcoming patch sets.

Added NvGpu CFLAGS to identify the safety build
"CONFIG_NVGPU_BUILD_CONFIGURATION_IS_SAFETY"

JIRA NVGPU-4133

Change-Id: I5a18256780e6726e399e39c1c8d155d2ef07d7bd
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2250461
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 2020-12-15 14:10:29 -06:00
Sagar Kamble
b32470e3ae gpu: nvgpu: unit: falcon: add test for copy_to_imem|dmem from unaligned offsets 
Add test case for verifying that copy to imem and dmem from unaligned
buffer succeeds.

JIRA NVGPU-2214

Change-Id: I4b0e6b184de5f23713bfbb5a8493cb06667c2d12
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254166
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
055fe1c9fe gpu: nvgpu: unit: branch coverage for fecs interrupts 
Add more test to handle various branches of fecs ecc errors
based on interrupts.

Jira NVGPU-4453

Change-Id: Icb74b347eb86d8f683fc332698fc1b8d75fc059b
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255621
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:10:29 -06:00
vinodg
9cd4357f4e gpu: nvgpu: gr.falcon unit test update 
Remove the code used to verify the nonsecure gpccs path
on initialize ctxsw ucode. For Safety secure path is enabled
by default.

Jira NVGPU-4453

Change-Id: I55aae29f56a9909d6c9966582a5d56f85b684a12
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
b0862a168c gpu: nvgpu: compile out nonsecure code in gr.falcon 
For Safety code NVGPU_SEC_SECUREGPCCS bit will be set by default.

Compile out the code called for nonsecure gpccs under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT checking.
This includes:
Hals for load_ctxsw_ucode_header and  load_ctxsw_ucode_boot.
nvgpu_gr_falcon_load_gpccs_with_bootloader and static functions
called from this function.

Jira NVGPU-4453

Change-Id: I56e6d585a26fcf593059a5157de07b77e3b9f00d
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255490
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
c56fd287e9 gpu: nvgpu: unit: fix group name for gr subunits 
Fix the SWUTS group name for gr-config and gr-intr units.

Jira NVGPU-4454

Change-Id: I3ebc46e252d90d585dacfaa18e4cbafca3cb46b5
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2255457
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
a54df13168 gpu: nvgpu: More line coverage test for gr.falcon 
Add line coverage test to cover kmem and dma allocation
failure in gr.falcon unit test

Jira NVGPU-4453

Change-Id: I8d594cacb9af3672c27a631cc7357f863993f466
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254705
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
63de725df9 gpu: nvgpu: unit: add tests for usermode gv11b HAL 
Add unit tests for the following usermode HALs:
- gv11b_usermode_base
- gv11b_usermode_bus_base
- gv11b_usermode_doorbell_token
- gv11b_usermode_ring_doorbell

Jira NVGPU-4389

Change-Id: I7fdad23b0482c1437d309e8eeab239aad1fb5c99
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254548
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
4e9c117848 gpu: nvgpu: unit: add tests for userd gk20a HAL 
Add unit test for the following HAL:
- gk20a_userd_entry_size

Jira NVGPU-4389

Change-Id: I8da4fcc3c3e3aadf69e7cf1ae26fba6f2701a557
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
2846c26c1e gpu: nvgpu: unit: enable engine tests on target 
Add the following tests to target makefile:
- engine
- engine/gm20b
- engine/gp10b
- engine/gv100
- engine/gv11b

Fix build issues for unit tests on QNX safety.
Update export files to fix link issues.
Update list of required tests in JSON file.

Jira NVGPU-3695

Change-Id: I373c6c8575ed4cbf6c5597502f2ca6ec2f078ca4
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253506
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
e211535142 gpu: nvgpu: unit: add tests for gm20b engine HAL 
Add unit test for the following HAL:
- gm20b_read_engine_status_info

Jira NVGPU-3695

Change-Id: I8752e3ac83fb647704ad5547d650574d2b5a95c7
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253505
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
94056dedf5 gpu: nvgpu: unit: add tests for gp10b engine HAL 
Add unit test for the following HAL:
- gp10b_engine_init_ce_info

Jira NVGPU-3695

Change-Id: Id63818b9b2478408f84489cf70c496f4a5645a47
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253504
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
2c83d780b0 gpu: nvgpu: unit: add tests for gv11b engine HAL 
Add unit test for the following HAL:
- gv11b_is_fault_engine_subid_gpc

Jira NVGPU-3695

Change-Id: I968fe6d189f311c9b9627f6b59998ef3cbd0b3f5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253503
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
71b7e85b50 gpu: nvgpu: unit: add tests for gv100 engine HAL 
Add unit tests for the following HALs:
- gv100_read_engine_status_info
- gv100_dump_engine_status

Jira NVGPU-3695

Change-Id: I66ba608802431d0f7ac2471d9ce726817f32c73e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253502
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Deepak Nibade
d58e14e4d0 gpu: nvgpu: unit: add negative tests for common.gr.fs_state 
Add negative tests that inject memory allocation failures and verify
error handling path in common.gr.fs_state unit.

Jira NVGPU-4373

Change-Id: If8774a60ffc951bd2c9978196268c20e10188026
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247846
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Deepak Nibade
04adc71304 gpu: nvgpu: add assert on number of SMs 
HAL gops.gr.config.init_sm_id_table() initializes SM count in struct
nvgpu_gr_config. It is almost impossible that SM count is detected as
zero.

Hence remove the error check and add an assert instead.

This also helps with code coverage tests since it is difficult to
simulate error condition of having zero SMs detected.

Also, HAL gops.gr.config.init_sm_id_table() should always be defined
for each platform. Hence remove unnecessary check.

Jira NVGPU-4373

Change-Id: Ibd9b301b28d5bd2952367346a8f12fabcee2abd9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247845
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Deepak Nibade
4554b4654a gpu: nvgpu: make gops.gr.init.fs_state return void 
This HAL function does not return any real error at all.
So just change the return type to void.

In case of vGPU, this function only calls another HAL
gops.gr.config.init_sm_id_table(). So unset gops.gr.init.fs_state()
for vGPU, and call gops.gr.config.init_sm_id_table() directly.

Jira NVGPU-4373

Change-Id: I06a80520e9be50a0703608a79187c553b33aa582
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247844
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Deepak Nibade
a5cc0d9976 gpu: nvgpu: compile out user provided tpc_fs_mask in safety 
User can update tpc_fs_mask either through sysfs or from Device tree.
Both the use cases are not supported in safety.

Hence compile out corresponding support with CONFIG_NVGPU_NON_FUSA
compile time config

Jira NVGPU-4373

Change-Id: I1269509409e2c980bd41364cf460e818d8c13267
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247843
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
8a26aa5916 gpu: nvgpu: rearrange code for gr.falcon unit 
gr_falcon_sec2_or_ls_pmu_bootstrap function is valid only
with CONFIG_NVGPU_DGPU or CONFIG_NVGPU_LS_PMU setting.

Rearrange code in gr_falcon_recovery_bootstrap and
gr_falcon_coldboot_bootstrap to avoid extra error checking.

Jira NVGPU-4453

Change-Id: I1fcba852610214a2647f324be1f182db57835cff
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254704
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Thomas Fleury
9bb6c332cf gpu: nvgpu: unit: make force_ctx_reload test required 
Add test_gm20b_channel_force_ctx_reload to list of required
tests in JSON file.

Jira NVGPU-4384

Change-Id: I010308e03c71a46a7cfb2369cf233b219b27ae55
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254649
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Sagar Kamble
a8866825d2 gpu: nvgpu: fix the doxygen comments due to ECC and MC refactoring changes 
nvgpu_mc_log_pending_intrs is debugging related function hence compile
out that and related functionality under CONFIG_NVGPU_NON_FUSA.
nvgpu_mc_intr_enable is applicable for older chips hence compile out
under CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA.
Update BUS, CE, ECC, FIFO, MC, PRIV_RING, GR, LTC, FB, PMU units'
doxygen comments based on recent ECC and MC refactoring.

JIRA NVGPU-4439

Change-Id: I337318683d6311b9c2b5748f2fb07dff29a6584f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2252853
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Scott Long
bf49a248be gpu: nvgpu: MISRA 4.4 fix to regops 
MIRA Advisory Rule 4.4 states that sections of code
should not be commented out.

This change removes the following unused regop type from
our regops support:

  /*#define NVGPU_DBG_REG_OP_TYPE_FB  (0x00000020)*/

Jira NVGPU-3178

Change-Id: I2a65c50aabf6b51072dd6fc1e344d543e3359525
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2245762
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
3fd253f896 gpu: nvgpu: add more test coverage to gr.ecc unit 
Add test coverage to free gr.ecc allocation.

Jira NVGPU-4460

Change-Id: I2fcd08adb23e444331020af8590eb698a3fc6d7c
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254560
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Philip Elcan
dcb19f578a gpu: nvgpu: unit: ltc: increase line/branch coverage 
This increases the line and branch coverage for nvgpu.common.ltc unit
test.

Add testing for nvgpu.common.hal.ltc for gv11b.

Also, add Targets tag for SWUTS/traceability.

JIRA NVGPU-2219

Change-Id: Ic0e3772b6348ba7ce43fd869567467bc13b8943c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248093
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Philip Elcan
b8c25a5a55 gpu: nvgpu: unit: init: add quiesce testing 
Add testing of quiesce functionality to init unit test.

JIRA NVGPU-3981

Change-Id: Idc64179bc8d532bea385e705d96fb4b376d15cd9
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2247154
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
234a82fc9a gpu: nvgpu: Add more tests for common.gr.falcon subunit 
Add more test coverage for common.gr.falcon subunit.
Rearrange few tests that use nvgpu_gr_falcon_init_ctxsw to a single test.
Support alloc failure for nvgpu_gr_falcon_init_support.

Add Doxygen for common.gr.falcon subunit.

Jira NVGPU-4453
Jira NVGPU-4381

Change-Id: I8fa9059c2c5c6e30af7ea8a2321ba3e19164dc98
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253770
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
Debarshi Dutta
4cc1fa1a0b gpu: nvgpu: construct initial utf for sync unit. 
This patch constructs the initial setup for sync unit.
There are three simple tests currently. The first test inits the
environment necessary such as regspace init, hal init. The second
step simply fails the creation of the sync and the last test is meant
as a deinit step.

JIRA NVGPU-913

Change-Id: I1db72d9833c3c4bc3c3903a7d81cce06e9983509
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2248493
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00
vinodg
bb942331e8 gpu: nvgpu: compile out unused code in gr.falcon unit 
NVGPU_GR_FALCON_METHOD_HALT_PIPELINE section is used only
with CONFIG_NVGPU_ENGINE_RESET setting.

Jira NVGPU-4453

Change-Id: Ia33e370486ebcd2052b7ec9d530503f93e798cbf
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2253865
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:10:29 -06:00