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2947 Commits

Author SHA1 Message Date
Deepak Nibade
49ad421542 gpu: nvgpu: allocate object context for graphics classes in safety 
Since graphics classes are enabled in safety, allow creating object
context also for graphics classes.

Jira NVGPU-6463

Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Change-Id: I4aff3f70ce0871093ce39b49edff06648cd0f692
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521175
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-05-05 06:26:32 -07:00
Ramesh Mylavarapu
a9a7e4f018 gpu: nvgpu: allocate wpr reserve space for NVRISCV pmu 
Falcon image is cleanly partitioned between a code and
data section where we don't need extra reserved space.
NVRISCV image has no clear partition for code and data
section, so we need reserved wpr space for runtime use.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I80fa89fc10d0a0fd2fb8b74bae499b66d5563e00
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2509553
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-05-04 18:04:30 -07:00
Ramesh Mylavarapu
a0b1b3f2be gpu: nvgpu: add priv lockdown release check for NVRISCV pmu 
IRQ register access will cause priv errors if they
are accessed before priv lockdown is released.
This change adds a polling loop to check priv lockdown
before proceeding further while booting NVRISCV pmu.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I44b8ce4c59b5a9f20901e5ce08610d17725da779
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512351
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-05-04 18:04:25 -07:00
Ramesh Mylavarapu
4d3a935b1a gpu: nvgpu: enable lazy bootstrap support for NVRISCV pmu 
Lazy bootstrap is a secure iGPU feature where LS falcons(FECS and
GPCCS) are bootstrapped by LSPMU in both cold boot and recovery boot.
As there is no ACR running after boot, we need LSPMU to bootstrap LS
falcons to support recovery.
In absence of LSPMU, ACR will bootstrap LS falcons but recovery is
not supported.
This CL will enable Low secure falcon manager(lsfm) to support
Lazy bootstrap feature. This will allow nvgpu to send cmds
to lspmu to bootstrap LS falcons.

Bug 200709761

Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I65d17cf5e07a45c040a9bb75f75cf18eb509cd4f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506162
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-05-04 18:04:19 -07:00
smadhavan
5dacead521 nvgpu: gpu: adds support for ACR dbg/prod. 
ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.

ACR ucode binaries are also renamed with "nv_" prefix to conform
to release naming conventions.

Bug 2672836

Change-Id: I48818f018f903c0d03642c12485d60e392121eb6
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492587
Reviewed-by: Andrey Jivsov <ajivsov@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-05-04 10:05:52 -07:00
Sagar Kamble
07d8a39647 gpu: nvgpu: wait for stalling interrupts to complete during TSG unbind preempt 
Some of the engine stalling interrupts can block the context save off
the engine if not handled during fifo.preempt_tsg. They need to be
handled while polling for engine ctxsw status.

Bug 200711183

Change-Id: I7418a9e0354013b81fbefd8c0cab5068404fc44e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521971
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-05-03 20:40:05 -07:00
Sagar Kamble
6672914980 gpu: nvgpu: create timed wait functions for stall and nonstall interrupts completion 
In order to process stalling interrupts during TSG unbind, we need a API
to wait for the stalling interrupts to complete within certain duration.

Prepare these APIs for stalling and non-stalling interrupts.

Bug 200711183

Change-Id: I0b7a64c0f3761bbd0ca0843aea28a591ed23739f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521970
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-05-03 20:40:00 -07:00
Sagar Kamble
89ec2afbd4 gpu: nvgpu: fix tsg unbind failure paths 
nvgpu_tsg_unbind_channel_common failure handling missed
channel.clear & nvgpu_tsg_set_mmu_debug_mode calls.

Bug 200711183

Change-Id: I19fd53be55db9df725b7cf467b2673e4cd29deb5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521972
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-05-03 03:25:07 -07:00
Seshendra Gadagottu
a54e34fd74 gpu: nvgpu: prod programming for elcg ce unit 
As part of nvgpu_ce_init_support, prod programming of
elcg ce unit is done using following function:
void nvgpu_cg_elcg_ce_load_enable(struct gk20a *g);

Also, nvgpu_cg_elcg_set_elcg_enabled extended to include
elcg_ce_load_gating_prod programming.

Jira NVGPU-6026

Change-Id: I00f29f877b5ac4dc9d3438930b674327dece1150
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512495
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-30 15:55:29 -07:00
Sagar Kamble
44c4611fda gpu: nvgpu: update pd clear condition to address IOMMU prefetch issue 
IOMMU fault is observed with 64KB PAGE_SIZE. This is due to IOMMU
prefetching stale/invalid pd entries. IOMMU can prefetch more
than 4K worth of entries.

Clear pd when NVGPU_PD_CACHE_SIZE is more than 4K.

Bug 200719161

Change-Id: Iac2a9bcfbcfaa36840da1fa85594520a6fd4eaaf
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521912
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-30 11:07:48 -07:00
Lakshmanan M
c041ad5b4b gpu: nvgpu: split nvgpu power on sequence into 2 stages 
1) nvgpu poweron sequence split into two stages:
    - nvgpu_early_init() - Initializes the sub units
      which are required to be initialized before the grgmr init.
      For creating dev node, grmgr init and its dependency unit
      needs to move to early stage of GPU power on.
      After successful nvgpu_early_init() sequence,
      NvGpu can indetify the number of MIG instance required
      for each physical GPU.
    - nvgpu_finalize_poweron() - Initializes the sub units which
      can be initialized at the later stage of GPU power on sequence.

    - grmgr init depends on the following HAL sub units,
      * device - To get the device caps.
      * priv_ring - To get the gpc count and other
        MIG config programming.
      * fb - MIG config programming.
      * ltc - MIG config programming.
      * bios, bus, ecc and clk - dependent module of
        priv_ring/fb/ltc.

2) g->ops.xve.reset_gpu() should be called before GPU sub unit
   initialization. Hence, added g->ops.xve.reset_gpu() HAL in the
   early stage of dGPU power on sequence.

3) Increased xve_reset timeout from 100ms to 200ms.

4) Added nvgpu_assert() for gpc_count, gpc_mask and
   max_veid_count_per_tsg for identify the GPU boot
   device probe failure during nvgpu_init_gr_manager().

JIRA NVGPU-6633

Change-Id: I5d43bf711198e6b3f8eebcec3027ba17c15fc692
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521894
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-29 14:23:48 -07:00
Sagar Kamble
668bd75c1a gpu: nvgpu: use deferred_fault_engines for resetting engines during unbind 
Engine reset is skipped if channel is disassociated from the tsg.
During unbind, tsg is disassociated before calling deferred
engine reset. Hence any deferred resets don't work
actually.

Engines to be reset is already set in the variable
deferred_fault_engines. Use it.

Bug 200711183

Change-Id: I0c2bdcad1770e0ccd001c208a9ac0cf499a374e1
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521974
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-04-29 10:54:47 -07:00
Debarshi Dutta
0d5bcdf28b gpu: nvgpu: disable access to regs in MIG mode 
The following registers belong to GR but are not a part of
Sys-Compute Pipe.

gr_pd_num_tpc_per_gpc_r
gr_ds_num_tpc_per_gpc_r

Jira NVGPU-6699

Change-Id: I350b0ea429f98845db4a31168a8dfb9211706c7a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2521784
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-04-29 10:54:37 -07:00
Richard Zhao
ab6d4fa543 gpu: nvgpu: create common sim reg accessors 
sim reg accessors is common after it moved to use os abstract layer reg
accessors.

Bug 2999617

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I1c0ff7ca1724cde09dd845c077763709ea2ef915
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517383
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-04-28 19:15:31 -07:00
Vedashree Vidwans
86cb03d2f1 gpu: nvgpu: Replace WAR keyword with "fix" 
Replace/remove "WAR" keyword in the comments in nvgpu driver with "fix".
Rename below functions and corresponding gops to replace "war" word with
"errata" word:
- g.pdb_cache_war_mem
- ramin.init_pdb_cache_war
- ramin.deinit_pdb_cache_war
- tu104_ramin_init_pdb_cache_war
- tu104_ramin_deinit_pdb_cache_war
- fb.apply_pdb_cache_war
- tu104_fb_apply_pdb_cache_war
- nvgpu_init_mm_pdb_cache_war
- nvlink.set_sw_war
- gv100_nvlink_set_sw_war

Jira NVGPU-6680

Change-Id: Ieaad2441fac87e4544eddbca3624b82076b2ee73
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515700
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-28 19:14:49 -07:00
Vedashree Vidwans
aba26fa082 gpu: nvgpu: handle chip specific erratas 
Currently, there are few chip specific erratas present in nvgpu code.
For better traceability of the erratas and corresponding fixes,
introduce flags to indicate existing erratas on a chip. These flags
decide if a corresponding solution is applied to the chip(s).

This patch introduces below functions to handle errata flags:
- nvgpu_init_errata_flags
- nvgpu_set_errata
- nvgpu_is_errata_present
- nvgpu_print_errata_flags
- nvgpu_free_errata_flags

nvgpu_print_errata_flags: print below details of erratas present in chip
1. errata flag name
2. chip where the errata was first discovered
3. short description of the errata

Flags corresponding to erratas present in a chip are set during chip hal
init sequence.

JIRA NVGPU-6510

Change-Id: Id5a8fb627222ac0a585aba071af052950f4de965
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2498095
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-28 19:14:44 -07:00
Debarshi Dutta
ca4db3fef3 gpu: nvgpu: disable access to regs in MIG mode 
The following registers belong to GR but are not a part of
Sys-Compute Pipe.

gr_gpcs_tpcs_pe_vaf_r
gr_gpcs_tpcs_pes_vsc_vpc_r
gr_pd_ab_dist_cfg0_r

There was a check added for gr_pd_ab_dist_cfg0_r earlier,
however, the entire function needs to be disabled in runtime

Change-Id: I535d639261a080d0fd4db4a44312746420eca66a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2518204
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-26 03:37:28 -07:00
Lakshmanan M
3f8c562004 gpu: nvgpu: Add nvgpu_early_poweron() support 
1) NvGpu dev node needs to be created in gpu power on
early stage to avoid latency introduced by udevd.
For creating dev node, device and grmgr init
needs to move to early stage of GPU power on.
After grmgr init, NvGpu can identify the number of MIG
instance required for each physical GPU.
For that, added a new API nvgpu_early_poweron() to handle
early init which is required for before dev node creation.

2) Removed fifo dependency in nvgpu_init_gr_manager()

3) Used get_max_subctx_count() directly to query
the veid/subctx count.

JIRA NVGPU-6633

Change-Id: Ib9d7c3e184c71237b0da9305515ccd8ceda1d5ad
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517173
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-04-22 15:00:54 -07:00
Deepak Nibade
c08719cb0b gpu: nvgpu: move graphics specific HALs to fusa files 
All graphics code is under CONFIG_NVGPU_GRAPHICS and all the HALs are
in non-fusa files. In order to support graphics in safety,
CONFIG_NVGPU_GRAPHICS needs to be enabled. But since most of the HALs
are in non-fusa files, this causes huge compilation problem.

Fix this by moving all graphics specific HALs used on gv11b to fusa
files. Graphics specific HALs not used on gv11b remain in non-fusa files
and need not be protected with GRAPHICS config.

Protect call to nvgpu_pmu_save_zbc() also with config
CONFIG_NVGPU_POWER_PG, since it is implemented under that config.

Delete hal/ltc/ltc_gv11b.c since sole function in this file is moved to
fusa file.

Enable nvgpu_writel_loop() in safety build since it is needed for now.
This will be revisited later once requirements are clearer.

Move below CTXSW methods under CONFIG_NVGPU_NON_FUSA for now. Safety
CTXSW ucode does not support these methods. These too will be revisited
later once requirements are clearer.
NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE

Jira NVGPU-6460

Change-Id: Ia095a04a9ba67126068aa7193f491ea27477f882
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2513675
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-04-22 14:59:38 -07:00
Seshendra Gadagottu
21e1328ea1 gpu: nvgpu: add fb gops for set_atomic_mode 
Separated set_atomic_mode functionality from
init_fs_state/enable_nvlink and created new
fb gops for set_atomic_mode.

In gpu init sequence, set_atomic_mode is
called after acr_construct_execute to take care
of design changes required for nvgpu-next
architectures.

Updated fb_gv11b_init_test to use set_atomic_mode
gops along with init_fs_state.

Bug 3268664

Change-Id: I1ab9eb21cc4cce77f3325c4e8821a75b6e85fba2
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2508095
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-04-22 14:58:36 -07:00
Sami Kiminki
3aceed2db1 gpu: nvgpu: add changes for nvgpu-next 
- Add new UAPI IOCTLs.
- Add nvgpu-next gops in fb and gr.
- Initialize and teardown vab during mm_support

Bug 2999621

Change-Id: Icc241f1a234bfee3fd20dc69b42c92e0af6d445c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447064
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-04-22 07:35:34 -07:00
Richard Zhao
cfc1281223 gpu: nvgpu: vgpu: remove gp10b support 
gp10b vgpu won't be supported on future releases.

- removed gp10b vgpu hal code
- removed vgpu bar1 related code
- removed gp10b vgpu linux platform code

Jira GVSCI-10202

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ic1bfeb12c854df3808a0c7e67f5c52bc1e80ab2d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517273
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-04-21 06:06:22 -07:00
absalam
3ec369d60a gpu: nvgpu: Disable Clock Arbitor for TU104 
This patch is to disable the clock arbitor for TU104.
TU104 is not a POR for Drive 6.0 so disabling it to easy migration
of clk arb for GA100.
As a first step all the NVRM Clock tests will be skipped by setting
NVGPU_SUPPORT_CLOCK_CONTROLS to false for TU104.
Then clk arbitor will be rewritten for GA100 and enabled back.
This patch implements by adding a new flag NVGPU_CLK_ARB_ENABLED which
holds the status of clk arbitor for each platform and disables them for
TU104

Bug 200699763

Change-Id: I51cd5c7821bdc0b48080c17a70735925b278ddf5
Signed-off-by: absalam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515086
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-20 07:47:38 -07:00
Richard Zhao
643eb158a3 gpu: nvgpu: move mapped regs to gk20a 
- moved reg fields to gk20a
- added os abstract register accessor in nvgpu/io.h
- defined linux register access abstract implementation
- hook up with posix. posix implementation of the register accessor uses
  the high 4 bit of address to identify register apertures then call the
  according callbacks.

It helps to unify code across OSes.

Bug 2999617

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ifcb737e4b4d5b1d8bae310ae50b1ce0aa04f750c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497937
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-04-19 19:45:24 -07:00
Debarshi Dutta
0a25376965 gpu: nvgpu: disable access to PE unit when MIG is enabled 
PE unit belongs to GR pipeline but not compute.
Hence disabled access to the PE register in the GR Boot flow
to prevent following PRIV error when SMC mode is enabled.

PRI timeout: ADR 0x00503018 READ  DATA 0x00000000
FECS_ERRCODE 0xbadf1100
[Error Type]: decode error

Jira NVGPU-6699

Change-Id: Ia6f58258611a010252c7ead46b1b48cbf1b64001
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2514894
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2021-04-19 16:19:09 -07:00
Sagar Kamble
ff706e5456 gpu: nvgpu: handle ctx_reload when force unbinding the channel 
When force closing the channel, NEXT and CTX_RELOAD bits might be set.
Currently CTX_RELOAD bit is ignored. However, due to this, the channel
created after the erroneous unbind encounters FECS fault.

If the channel is unbound while it is running, fifo unbind error
happens and can lead to unspecified behavior.

By moving CTX_RELOAD to other channel in the TSG, the channel can be
unbound safely. In other cases, if the channel is truly running
something when it is being unbound it should either get
preempted or be handled through engine reset.

Bug 200701444

Change-Id: Iba956544dcaa1144c6064247257c64cbe9a29ae6
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515083
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2021-04-15 16:21:44 -07:00
Lakshmanan M
7de19b0956 gpu: nvgpu: Add api to get the physical gpc mask 
1) Added a utility api to query the physical gpc mask for a
gpu instance.
2) Expose physical gpc mask during MIG case (par with legacy case).

JIRA NVGPU-5650

Change-Id: I7efb031ac6539d8859b265f42d269233a3a421bf
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510854
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-07 20:16:38 -07:00
Seshendra Gadagottu
f17d0c1c70 gpu: nvgpu: call prod programming hals for slcg ringstation units 
Added following helper function to program slcg prod values for
all priv_ring units:
static void nvgpu_cg_slcg_priring_load_prod(struct gk20a *g, bool enable);

Added slcg prod value programming hals for ringstation units in above
helper function.

Jira NVGPU-6026

Change-Id: I3aedb3428ee17f27ef4fc407da18ab6a3880dda7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2501059
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-07 09:22:04 -07:00
Mayur Poojary
6277d57936 gpu: nvgpu: Add new api for setting longer timeslice on dbg node 
Add new ioctl api for setting longer timeslice and get timeslice
inside 'dbg' dev node.
Update ioctl gpu_get_characteristic to pass the max timeslice value
Add debugfs to access and change the max timeslice value

Bug 1842244

Change-Id: I7e80f59162cf5d90496f9752fc128f5fa8dcc7d2
Signed-off-by: Mayur Poojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471569
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-04-06 04:37:38 -07:00
Antony Clince Alex
2d5d8e882f gpu: nvgpu: fix ce interrupt mask update 
The CE interrupt mask update should not be skipped if the driver doesn't
implement stall or non-stall interrupt handlers. At present, the mask update is
skipped if either is not implemented causing the other to remain disabled which
is not correct.

Update nvgpu_ce_engine_interrupt_mask to always return engine interrupt mask.

Bug 200709761

Change-Id: I503338e3f4d53c1e0b85b0974d862f7b88545ef2
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506292
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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 2021-03-29 19:02:16 -07:00
Divya Singhatwaria
6ffadc0e32 gpu: nvgpu: Remove hard coded constants from ACR 
During code inspection use of some hard coded
constants was found in some parts of the code.
Some constants are replaced by macros and some
are declared using const keyword.

JIRA NVGPU-6260

Change-Id: I95112dfcac7c8b996789a68e7ddf78b16713a823
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485727
(cherry picked from commit b7e554267d9ef94ae5ac4529f4758127b97d3ba5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2492451
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Andrey Jivsov <ajivsov@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2021-03-27 04:57:37 -07:00
Vedashree Vidwans
e445b57b04 gpu: nvgpu: Move interrupt ISR code to common 
This is one of the steps in restructuring of interrupt code.
- Move ISR logic to common code. This will allow us to add mixed ASIL
error handling levels.
- Modify nonstall ISR to use threaded interrupts. Bottom half of
nonstall ISR will run nonstall operations instead of adding work to
workqueues.
- Remove nonstall workqueue implementation.

JIRA NVGPU-6351

Change-Id: I5f891b0de4b0c34f6ac05522a5da08dc36221aa6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2467713
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 2021-03-25 02:34:57 -07:00
Sagar Kamble
ecfd675d9b gpu: nvgpu: free pmu variables allocated in early_init on error in rtos_init 
On error in pmu_rtos_init, pmu state was freed partly. That lead to
invalid access on subsequent nvgpu poweron. Free all pmu state in
such case.

Bug 200575409

Change-Id: I11166b55dbe00a225e811425d21500c3143a354c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2503577
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-03-24 14:47:44 -07:00
Divya Singhatwaria
4d02580df0 gpu: nvgpu: remove ZBC save/restore by PMU 
- ZBC save/restore registers are removed in GP10B PMU ucode.
- These registers are saved/restored from CTXSW ucode during
  ELPG entry/exit.
- Accessing the ZBC registers will cause PMU EXTERR error.
- To resolve this, ZBC functionality is removed from GP10B
  feature list in PMU ucode.
- From NvGPU driver, set NVGPU_PMU_ZBC_SAVE bit to false
  for GP10B
- Updated the GP10B PMU app version for the ucode:
  https://git-master.nvidia.com/r/c/tegra/kernel-firmware-t18x/+/2476260

P4 CL link related to this PMU ucode change:
https://p4sw-swarm.nvidia.com/changes/29594520

Bug 3233071
Bug 200696431

Change-Id: If3f1707b79699e7e2e65367418b25ac71b09cf0b
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
(cherry picked from commit 9170f2b77c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500641
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-03-24 03:36:40 -07:00
Antony Clince Alex
7f4e39aaf4 gpu: nvgpu: update pma stream teardown sequence 
On nvgpu-next chips additional steps are required for pma stream teardown.
Introduce wrapper function: NVGPU_NEXT_PROFILER_QUIESCE to perform this.

Jira NVGPU-5689

Change-Id: Iafdb9c6091b468b51295827467078d24e47d5e1f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491755
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-23 04:39:20 -07:00
Vedashree Vidwans
8ebe7ca314 gpu: nvgpu: resolve GCC 9.3 toolchain errors 
Using updated GCC 9.3 toolchain results into build failure with string
functions. The updated toolchain requires strncat API to be independent
of source string length.
Update strncat used in nvgpu_worker_init_name to use destination length
only.

Bug 3270814

Change-Id: Ie50a2bed2dc09a5e34d14012e1ba878ef4ff176f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2500503
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Aidan Ha <aha@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-22 02:23:48 -07:00
Divya Singhatwaria
cc34df76f9 gpu: nvgpu: Add support for ELPG_MS feature 
- To enable ELPG_MS feature, add identifier for
  MS_LTC engine.
- The identifier is then passed
  as pg_engine_id to enable the MS_LTC engine.
- Add enable flag NVGPU_ELPG_MS_ENABLED for
  enabling/disabling ELPG_MS feature at init.

JIRA NVGPU-6430

Change-Id: Ie1f477918332d85ec98b3bd4d05b8e773d74eab8
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480750
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2021-03-18 15:29:06 -07:00
ajesh
e10f201602 gpu: nvgpu: add checks as part of BVEC analysis 
Add checks in common.utils unit as part of BVEC analysis.
The check in enabled.c makes sure that unauthorized memory access
is not performed and string.c is modified with a check to avoid
a possible invocation of BUG.

Jira NVGPU-6268

Change-Id: I672c9c54a2d7b61219dee1b249b9e1345381a965
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2494951
(cherry picked from commit 464e101b23b0143ff2e26e07659e34d1678dbf9d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497647
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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 2021-03-17 18:23:42 -07:00
Sagar Kadamati
9e13fd900d nvgpu: gpu: update runlist in vserver 
On QNX, Setting runlist is not happening till runlist submit. On Linux,
Setting runlist is happening at the time of channel open. due to
implimentations, which effect's channel configuration.

We need runlist for channel configuration from now.

Adding runlist parameter for below calls
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX

Bug 200701789

Change-Id: Ibd3262b43e38f54c76c4ae67ce683eccf4460cdc
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485256
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-16 06:07:30 -07:00
Sumit Gupta
e5491327fa gpu: nvgpu: fix mutex wrong acquire 
Wrong acquire/release sequence.

 DEBUG_LOCKS_WARN_ON(rt_mutex_owner(lock) != current)
 ....
 CPU: 4 PID: 5404 Comm: cyclictest.sh Not tainted 4.9.201-rt134-tegra #1
 Hardware name: Jetson-AGX (DT)
 ....
 Call trace:
 [<ffffff800810e4f8>] debug_rt_mutex_unlock+0x58/0x68
 [<ffffff8008f34d0c>] rt_mutex_unlock+0x4c/0xb0
 [<ffffff8008f36ea8>] _mutex_unlock+0x20/0x2c
 [<ffffff8000f69d80>] nvgpu_cg_elcg_set_elcg_enabled+0x78/0xf0 [nvgpu]
 [<ffffff8000f7bd44>] nvgpu_intr_nonstall_cb+0x21bc/0x22f0 [nvgpu]
 [<ffffff800875b304>] dev_attr_store+0x44/0x60
 [<ffffff80082dca44>] sysfs_kf_write+0x5c/0x78
 [<ffffff80082dbd28>] kernfs_fop_write+0xc0/0x1d8
 [<ffffff8008245b60>] __vfs_write+0x48/0x128
 [<ffffff8008246b3c>] vfs_write+0xac/0x1b8
 [<ffffff800824808c>] SyS_write+0x5c/0xc8

Bug 3227296

Suggested-by: Bibek Basu <bbasu@nvidia.com>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Change-Id: I932a23700539422c07de045dde516c52dd8348cf
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2472903
(cherry picked from commit 535e9b1dd7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2487498
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-03-15 14:40:19 -07:00
Prateek sethi
fe03443161 gpu: nvgpu: replace hardcoded subscript with macro 
size of syncpt_name is hardcoded. Patch replaces hardcoded value with
macro.

Jira NVGPU-6371

Change-Id: I7a025f8f3687e104f61e0305096ac9e48d245a48
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485732
(cherry picked from commit 6e373be0c5377b7c251787caa79934db9a389e70)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2493073
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2021-03-09 04:46:44 -08:00
shashank singh
1d86da257b gpu: nvgpu: fix some assertion/nvgpu_safe* APIs call in devctl path 
Fix following issues in devctl processing path
- Remove assertion for kind>=0. It is already checked in function
  nvgpu_vm_do_map.
- Check for possible overflow of map_addr and mapping size without using
  nvgpu_safe* API for NVGPU_AS_DEVCTL_MAP_BUFFER_EX and
  NVGPU_AS_DEVCTL_ALLOC_SPACE devctl.

Jira NVGPU-6496

Change-Id: I569c89d50900100f57bc9727fd032d6cd2c331e4
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2487550
(cherry picked from commit 6d340d7e73ba8e031f50679991d259daa682a006)
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 2021-03-05 19:39:57 -08:00
shashank singh
b91f57d933 gpu: nvgpu: remove assert in devctl processing path 
Asserting in the path of devctl processing is not safe here because
incompr_kind can be passed out of range by a malicious app and it will
cause nvgpu-rm to crash. Instead return error in case of out of range
value.

Jira NVGPU-6496

Change-Id: I9c3264776110f606a67f27ce7b01fdce82aa3021
Signed-off-by: shashank singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485752
(cherry picked from commit 689054d65fff2c61b9f1d413eef4a44a5f27fc54)
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 2021-03-05 19:39:46 -08:00
ajesh
0030dc3eb4 gpu: nvgpu: fix MISRA violations in Posix unit 
Fix violations of MISRA rule 5.4 in Posix unit.

JIRA NVGPU-6534

Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184
(cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5)
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 2021-03-04 00:37:15 -08:00
Lakshmanan M
1438689a89 gpu: nvgpu: Add api to query the availability of multi GR support 
* Added a new api(nvgpu_gr_is_multi_gr_enabled()) to query the
  availability of multi GR support when MIG is enabled.

JIRA NVGPU-5650

Change-Id: I3f8c29db966afb8d72021a093e009492f134ec9d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488399
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 2021-02-25 14:42:22 -08:00
Alex Waterman
5bf229dcd5 gpu: nvgpu: Rename runlist_id to id 
Rename the runlist_id field in struct nvgpu_runlist to just id.
The runlist part is redundant given that this id is already in
'struct nvgpu_runlist'.

Change-Id: Ie2ea98f65d75e5e46430734bd7a7f6d6267c7577
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470306
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 2021-02-19 15:16:46 -08:00
Alex Waterman
bd1b395b5c gpu: nvgpu: Update runlist_id in TSG 
Update the runlist_id field in struct tsg to now be a pointer to
the relevant runlist. This further cleans up the rampant use of
runlist_ids throughout the driver.

Change-Id: I3dce990f198d534a80caa9ca95982255dcf104ad
Signed-off-by: Alex Waterman <alexw@nvidia.com>
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 2021-02-19 15:16:41 -08:00
Deepak Nibade
a1cbe60bc0 gpu: nvgpu: fix common.gr doxygen typos 
Jira NVGPU-6180

Change-Id: I499634aa407404474a6d3d7d3dfc6271eda21007
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2473441
(cherry picked from commit bdfb68b965b76b216e3a9782ef7f0d1f6cda2df0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478885
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 2021-02-02 23:34:32 -08:00
Deepak Nibade
bb43f11a61 gpu: nvgpu: update common.gr doxygen 
Add below updates to common.gr doxygen:

- Add doxygen comments for APIs that are mentioned in RM SWAD and in
  RM-common.gr traceability document.
- Comment about valid ranges for input parameters of bunch of functions.
- Add nvgpu_assert() to ensure correct value is passed as input
  parameter to number of functions.
- Add references to relevant functions with @see.
- Update Targets field for unit tests to cover newly doxygenated
  functions.
- Update unit test test_gr_init_hal_pd_skip_table_gpc to take care of
  new asserts added into some APIs.

Jira NVGPU-6180

Change-Id: Ie889bed96b6428b1fd86dcf30b322944464e9d12
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2469397
(cherry picked from commit 5d7d7e9ce1c4efe836ab842d7962a3aee4e8972f)
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 2021-02-02 23:34:27 -08:00
Deepak Nibade
27b321e1a9 gpu: nvgpu: fix header guards in common.gr unit 
Fix header guard names as per convention for below common.gr headers :
common/gr/gr_falcon_priv.h
common/gr/zbc_priv.h
include/nvgpu/gr/ctx.h

Jira NVGPU-5005

Change-Id: I68947ea3e8f4ddbcd43be8d8717eb8ddcc6f5bcb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470072
(cherry picked from commit eb044acbafc6d9f735e066d9c7497156f1df13c7)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478884
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 2021-02-02 23:34:21 -08:00