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8023 Commits

Author SHA1 Message Date
Alex Waterman
1f28443889 gpu: nvgpu: Disable platform debug spew by default 
Disable the somewhat non-useful syncpoint debug spew in the nvgpu
debug spew. The GPU has it's own snapshot view of syncpoints so
visibility into other syncpoint data is often not very helpful.

However, there are plausibly times where this would be necessary.
For example debugging a sync issue between the GPU and some other
SoC engine. Therefore, the syncpoint debug spew can be enabled
again at runtime if necessary.

JIRA NVGPU-5541

Change-Id: I7028e2d6027e41835b2fed4f2bbb366c16b99967
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349185
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
8778aa531d gpu: nvgpu: netlist: correct info for generic regions 
There is an issue with reading u32 data for generic regions.
The u8 pointer dereference copying only u8 data instead of
u32 data. Legacy code is not using this data, so the issue
is not caught earlier. Now using nvgpu_memcpy to copy all
bytes of u32 data.

Bug 2986531

Change-Id: Ib23c76cd1ce77e3a2f882940b11703391a11f99d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2348593
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
f0de6fa54a gpu: nvgpu: sec2: update sec2 interfaces 
update sec2 rtos interfaces to support next dgpu sec2 ucode.

JIRA NVGPU-5468

Change-Id: I534a6eded8a9525dc09e5f57e46bef36f1a4e81b
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352103
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
1c40ebe9b1 gpu: nvgpu: handle pbus and priv intr first 
Handle pbus and priv intr before handling other stall
interrupts. These should be treated as high priority
interrupts.

JIRA NVGPU-25
Bug 200603566

Change-Id: I707119c8751a5621958777ffb64300db28426dfb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2350773
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 2020-12-15 14:13:28 -06:00
ajesh
ce4e7a6859 gpu: nvgpu: remove redundant error prints 
Remove OS API return error prints from posix files as the BUG
function prints the function and line number which causes the
error.

Jira NVGPU-4987

Change-Id: Ie6d6f781241ac5e837f2732fbb1cc1ddc4d971d4
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2337390
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
16fb7654a5 gpu: nvgpu: isolate channel watchdog unit 
Move the definition of struct nvgpu_channel_wdt to watchdog.c. Adjust
users of it to access it via an unified interface instead of poking
directly at the channel internals.

Jira NVGPU-5494

Change-Id: Ie11826e6732a8b98e72c4f81dd06bd7e49848121
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345935
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
21e02878f4 gpu: nvgpu: move wdt code out of channel.c 
Cut and paste the existing channel watchdog functions to another file
for better isolation of units.

Jira NVGPU-5494

Change-Id: Id437f0939e69a4a8b495eaee164c4d7a9f283fa9
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345934
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
22987182a3 gpu: nvgpu: make ltc ecc intr handle func global 
LTC interrupt handle functions are reused in nvgpu-next. So, make listed
ltc intr functions global.
- gv11b_ltc_intr_init_counters
- gv11b_ltc_intr_handle_rstg_ecc_interrupts
- gv11b_ltc_intr_handle_tstg_ecc_interrupts
- gv11b_ltc_intr_handle_dstg_ecc_interrupts

Jira NVGPU-5094

Change-Id: I33a21ef7585314e31398dd165e1c7399ed27a7c3
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2337896
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2d94863cae gpu: nvgpu: move is_tpc_addr and get_tpc_num to common 
gr.is_tpc_addr() and gr.get_tpc_num() are chip agnostic hals. Move these
hals to common code.

Jira NVGPU-5504

Change-Id: I50fa7ac876c8667de42df1830bd412b412538508
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349272
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 2020-12-15 14:13:28 -06:00
Sami Kiminki
23cda4f4a9 gpu: nvgpu: add PDI for TU104 (Linux) 
Add reporting for the per-device identifier (PDI) in the Linux GPU
characteristics. Implement PDI read for TU104.

Bug 2957580

Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Change-Id: I6ac0e4f74378564d82955b431d4c1fd6c0daeb13
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2346933
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Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Richard Zhao
8d68e687f0 gpu: nvgpu: linux: check whether hal initialized for gr_default_attrib_cb_size 
On access debugfs node gr_default_attrib_cb_size, the hal might not have
been initialized.

Bug 2848790

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I0a70f1377d2001802092a8eccec5ec144a58c79b
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349299
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Richard Zhao
6d922dd9b7 gpu: nvgpu: vgpu: remove debugfs node dump_ctxsw_stats_on_channel_close 
It could cause kernel debug since vgpu cannot dump gr_ctx content.
Also set .dump_ctxsw_stats null in vgpu hal.

Bug 2848790

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia9ec99d464be72e2be26df25c572e671e10c18a5
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349295
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Richard Zhao
cef1780e05 gpu: nvgpu: vgpu: remove ce_app support 
Kernel oops on dump ce_app debugfs nodes. ce_app is only used by dGPU
which vgpu does not support currently. This patch removes hal setup and
debugfs setup for ce_app.

Bug 2848790

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ia60a06a27b2d2ceda96ca567cda9e9a01e023c4b
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349294
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 2020-12-15 14:13:28 -06:00
Richard Zhao
246b5fcf4d gpu: nvgpu: debugfs: only create railgate_residency if not is_virtual 
Dump railgate_residency causes kernel crash since vgpu does not control
railgate_residency. So create railgate_residency only on native driver.

Bug 2848790

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I08d65e1c1c5bf813f0c47d5bffad5a01ea62adf8
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349293
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 2020-12-15 14:13:28 -06:00
Alex Waterman
6b1302f23c gpu: nvgpu: Reduce linux debug log spew 
Currently when nvgpu prints debug information for something like an MMU
fault the result includes a lot of usless boiler plate logging spew. In
some cases this can be helpful in identifying where the log message came
from in the nvgpu code base. However, for debug spews from faults, the
viewer of that info does not care which function printed the log (for
example).

Instead having a fast and readable debug dump is more valuable. So to
that end, add a special debug dump printing function that does not use
the normal log format. Instead, it prints only a breif prefix to use as
a grep search query. The new print out is listed below.

Since often the kernel logs are impressively long and obtuse, having a
clear debug search string can be helpful. With this log format, one can
simply do:

  $ grep __$CHIP__ kernel.log

And find any debug logs for the desired chip.

New log format - collected on a gv11b under L4T running
`nvgpu_submit_mmu_fault':

[   32.005793] nvgpu: 17000000.gv11b      gv11b_fb_mmu_fault_info_dump:311  [ERR]  [MMU FAULT] mmu engine id:  32, ch id:  511, fault addr: 0x1000, fault addr aperture: 0, fault type: invalid pde, access type: virt read,
[   32.006137] nvgpu: 17000000.gv11b      gv11b_fb_mmu_fault_info_dump:320  [ERR]  [MMU FAULT] protected mode: 0, client type: hub, client id:  host, gpc id if client type is gpc: 0,
[   32.006417] nvgpu: 17000000.gv11b                nvgpu_rc_mmu_fault:296  [ERR]  mmu fault id=0 id_type=1 act_eng_bitmask=00000000
[   32.007125] __gv11b__ Channel Status - chip gv11b
[   32.007128] __gv11b__ ---------------------------
[   32.007241] __gv11b__ 511-gv11b, TSG: 0, pid 955, refs: 2, deterministic:
[   32.007364] __gv11b__ channel status:  in use pending busy
[   32.007509] __gv11b__ RAMFC : TOP: 8000000000001000 PUT: 0000000000001030 GET: 0000000000001000 FETCH: 0000600000001000HEADER: 60400000 COUNT: 00000000SEMAPHORE: addr 0000000000000000payload 0000000000000000 execute 00000000
[   32.007601] __gv11b__
[   32.008696] __gv11b__
[   32.008700] __gv11b__ PBDMA Status - chip gv11b
[   32.008894] __gv11b__ -------------------------
[   32.013477] __gv11b__ pbdma 0:
[   32.017840] __gv11b__   id: -1 - [channel] next_id: - -1 [channel] | status: invalid
[   32.020992] __gv11b__   PBDMA_PUT 0000000000001030 PBDMA_GET 0000000000001000
[   32.029037] __gv11b__   GP_PUT    00000001  GP_GET  00000001  FETCH   00000001 HEADER 60400000
[   32.036386] __gv11b__   HDR       00000000  SHADOW0 00001000  SHADOW1 80003000
[   32.044787] __gv11b__ pbdma 1:
[   32.051964] __gv11b__   id: -1 - [channel] next_id: - -1 [channel] | status: invalid
[   32.055099] __gv11b__   PBDMA_PUT 0000000042003200 PBDMA_GET 00000050728bc914
[   32.062997] __gv11b__   GP_PUT    00000000  GP_GET  2080a000  FETCH   00000000 HEADER e1850010
[   32.070424] __gv11b__   HDR       00110000  SHADOW0 02000000  SHADOW1 10000004
[   32.078652] __gv11b__ pbdma 2:
[   32.085913] __gv11b__   id: -1 - [channel] next_id: - -1 [channel] | status: invalid
[   32.088973] __gv11b__   PBDMA_PUT 00000021040c0004 PBDMA_GET 0000000140020000
[   32.096502] __gv11b__   GP_PUT    00000000  GP_GET  8080a440  FETCH   00000000 HEADER 61400040
[   32.103679] __gv11b__   HDR       14000010  SHADOW0 00000000  SHADOW1 00000400
[   32.112336] __gv11b__
[   32.119860] __gv11b__ gv11b eng 0:
[   32.122119] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.125807] __gv11b__
[   32.135954] __gv11b__ gv11b eng 1:
[   32.135958] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.139457] __gv11b__
[   32.149945] __gv11b__ gv11b eng 2:
[   32.149950] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.153543] __gv11b__
[   32.163598] __gv11b__ gv11b eng 3:
[   32.163601] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.167278] __gv11b__
[   32.177076] __gv11b__
[   32.186145] nvgpu: 17000000.gv11b       nvgpu_tsg_set_ctx_mmu_error:492  [ERR]  TSG 0 generated a mmu fault
[   32.189443] nvgpu: 17000000.gv11b     nvgpu_set_err_notifier_locked:140  [ERR]  error notifier set to 31 for ch 511

JIRA NVGPU-5541

Change-Id: Iad60adfab5198ee11dd2ec595f2422ea541b7a2a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349166
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Alex Waterman
5d06a59bc5 gpu: nvgpu: Cleanup uart and debugfs debug prints 
The gk20a_debug_dump() function implicitly adds a newline since it
uses nvgpu_err() under the hood (for uart destined prints). For the
seq_file destined writes it does not so there is an annoying inconsistency.

Remove the newline that many of the gk20a_debug_dump() calls add and add
the newline to the (now) seq_printf() call. This reduces the length of
debug dump logs and speeds them up - UART is _very_ slow after all.

Also cleanup some formatting issues in the various debug prints I
happened to notice.

JIRA NVGPU-5541

Change-Id: Iabf853d5c50214794fc4cbb602dfffabeb877132
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2347956
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Richard Zhao
f2d424d452 gpu: nvgpu: vgpu: init rwsem deterministic_busy 
Uninitialized rwsem raised warnings on enabling spinlock debug.

Bug 2880934

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I74828b291c518f1fd987806682118041af41e080
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2346408
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aparna Das <aparnad@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Richard Zhao
b3766f352c gpu: nvgpu: call hal callback when set fecs_trace default filter 
vgpu depends on the hal callback to notify server the filter changes.

Bug 200469911

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ibc9221de853ebe813609f897b46584f5cf88cbce
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2343613
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
bc4cef7a43 gpu: nvgpu: offset for exterraddr and exterrstat reg 
Compute the offsets for falcon_falcon_exterraddr_r()
and falcon_falcon_exterrstat_r() registers by applying
the mask 0xFFF

JIRA NVGPU-4834

Change-Id: I7cef6f82e7802bea9133f3c95c891de22ef10d07
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2347674
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Sami Kiminki
bac1bf6061 gpu: nvgpu: expose support for SM-TTU (Linux) 
Add NVGPU_SUPPORT_SM_TTU capability and map it to
NVGPU_GPU_FLAGS_SUPPORT_SM_TTU characteristics flag.

JIRA NVGPU-5482
Bug 2811407

Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Change-Id: Ie06034199bb54835cbb763cfbddae555b2933ac2
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2344213
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Riku Salminen <rsalminen@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
50dcfe1637 gpu: nvgpu: update fb unit ecc init, handling 
The ecc init, handling for the fb unit is refactored to improve reusability
for nvgpu-next.

The following changes have been done:
- fb.ecc:
  This is a new subunit within fb and contains the following functions:
  - init: Moved from fb.fb_ecc_init.
  - free: Moved from fb.fb_ecc_free.
  - l2tlb_error_mask: Fetch bit mask for corrected, uncorrected errors supported
    by the unit.
- fb.intr:
  This unit has been updated to include the following ecc interrupt, error
  handlers:
  - handle_ecc: Top level interrupt handler for fb ecc errors.
  - handle_ecc_l2tlb: Handle errors within l2tlb memory.
  - handle_ecc_hubtlb: Handle errors within hubtlb memory.
  - handle_ecc_fillunit: Handle errors within fillunit memory

Jira: NVGPU-5032

Change-Id: I1a26c1823eb992e0e0175250b969f1186dff6e62
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333271
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Abdul Salam
d339d9ed33 gpu: nvgpu: segregate clk_mon from clk unit. 
As a part of refactoring this CL removes clk_mon unit from
clk unit.
Clk_mon is used for monitoring of clk and it is an independent unit.
This patch does the following.
*Move the clk_mon struct from clk.h to clk_mon_tu104.h
*create a new clk_mon gpu_ops and assign clk_mon specific ops there.
*Move all the function to clk_mon_tu104.c
*Update the yaml file

NVGPU-4689

Change-Id: Ia72bf28a93ce9a7936c277076f365c4b6593b032
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336230
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d5b14a389e gpu: nvgpu: do not writel_check zbc broadcast regs 
Use nvgpu_writel() instead of nvgpu_writel_check() for writing the zbc
color, depth and stencil values in L2 ZBC registers. Checking that the
read value equals is not sensible for broadcast registers, and in these
cases it's not necessary to read back the regs to synchronize memory.

Bug 2976632

Change-Id: Id40e7d0f435bae5a395b5553c186fc50302f7dea
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345877
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 2020-12-15 14:13:28 -06:00
mkumbar
91af7efd23 gpu: nvgpu: enable ACR support for NEXT dGPU 
-Enabled ACR support for NEXT dGPU
-Blob creation & boot strap of LSPMU support skipped by ACR
 by checking flag "support_ls_pmu", lspmu support is not
 required until PSTATE support is enabled.

JIRA NVGPU-5461

Change-Id: I5a4c688926ca1c55aeb4cbbb9668c55bb35f9119
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2344582
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
2077df9b1a gpu: nvgpu: use set_syncpt only with nvhost 
nvgpu_channel_set_syncpt() is not useful if nvhost and thus syncpts are
missing and semaphores are used for synchronization. Require
CONFIG_TEGRA_GK20A_NVHOST to be set for the set_syncpt hal.

Jira NVGPU-5496

Change-Id: Ief8b4a0fb29af631817aba55c04181b1a360ce56
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
10239a9084 gpu: nvgpu: delete idle check in cde completion 
With an exclusively owned context and a channel per cde job, new cde
jobs are never launched on an active channel. A context is allocated,
then used with one job, and then released to the free pool when the
completion callback occurs. There is no need to check for an empty job
list, so delete the check to avoid a dependency to channel joblist
internals from cde code.

Long back in the history the cde contexts were reused before going idle
but the dynamic allocation has existed for years now and each
context/channel pair is isolated.

Jira NVGPU-5492

Change-Id: I9047ef4cd029996ba58fec42ddd55bb52cf0d6a6
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2343243
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
b6bf13290e gpu: nvgpu: alloc correct prealloc buffer sizes 
The trivial ringbuffer implementation in channel job list and priv cmd
buffers acts such that the buffer is full when the number of inserted
entries in it is one less than allocation size, similarly to the
hardware gpfifo. Take this into account when allocating the job tracking
resources: previously the allocation has been off-by-one too small.

Jira NVGPU-5492

Change-Id: If7bfd4919daa5b0328394ca289d5692c0d2b4f5f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342129
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 2020-12-15 14:13:28 -06:00
mkumbar
9c2a0ce72d gpu: nvgpu: enable falcon sw init for NEXT dGPU 
Enable GSP, SEC2, NVDEC, PMU, FECS & GPCCS engines Falcon s/w
support for NEXT dGPU.

JIRA NVGPU-5464

Change-Id: I5398d4b0331c4ff59e00d0dd1857baa84db609d2
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339669
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d916e85171 gpu: nvgpu: incr sync once submit is ready to go 
Split out the max value increment and syncpt interrupt registration out
of nvgpu_channel_sync_incr*(). This API is called in the submit path to
prepare buffers and tracking resources, but later on in the submit path
errors can still occur so that the increment wouldn't happen (unless
artificially forced by sw).

The increment and irq registration cannot easily be undone and it makes
more sense to do these at the moment when the prepared job is finally
ready, so add a new nvgpu_channel_sync_mark_progress() API to be called
later in the submit path to signal that progress shall eventually happen
on the sync. Without this, the max value would stay too large after an
unsuccessful submit until the channel gets closed.

The sync object (syncpt or semaphore) is always exclusively owned by the
channel that allocated it, so nonatomically reading the max value first
in sync_incr() and incrementing it later in mark_progress() is racefree;
all submits per channel are serialized.

Change the channel syncpoint to client managed from host managed so that
nvhost-exported sync fences behave correctly with the temporary state
where the fence threshold is over the max value. Ideally we'd always
track nvgpu-owned syncpts' max values internally, but this is enough for
now.

Jira NVGPU-5491

Change-Id: Idf0bda7ac93d7f2f114cdeb497fe6b5369d21c95
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340465
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
dbbe6b67be gpu: nvgpu: add wrapping_add_u32 
Add nvgpu_wrapping_add_u32() to perform static analysis safe arithmetic
where unsigned wraparound is expected. nvgpu_safe_add_u32() expects that
the result does not wrap, so it cannot be used in such cases.

Jira NVGPU-5491

Change-Id: I68f550fbc62601a9045f8e405e925ad8dac90872
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342585
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 2020-12-15 14:13:28 -06:00
Richard Zhao
f73d035983 gpu: nvgpu: vgpu: add vgpu_css_init 
Added vgpu_css_init to setup ivm at init time.

Background:
vgpu_css_reserve_mempool was called at runtime in many places without any lock.
To avoid racing, the patch moves it to init time and rename it to vgpu_css_init.

Bug 200598546

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I4c7794ee7151fc604643f94700d5b986472b2e71
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336905
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
9d7bf6c902 gpu: nvgpu: make os fence impl headers GPL 
The Android and dmabuf os fence implementations are Linux-specific.
Change the copyright banner of the matching header files to be GPLv2 as
it should have been; they're used only in Linux code.

Jira NVGPU-5353

Change-Id: Ifd365672ba5c797de82e18a2d0e7bf69459451be
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342000
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 2020-12-15 14:13:28 -06:00
Peter Daifuku
f0f126d7cc gpu: nvgpu: posix: fix GPL dependencies in bitmap 
Fix up GPL issues in posix version of bitops.

Bug 2919200

Change-Id: I57fdb035b811f47e119cca2278431d3701717d89
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
681077d578 gpu: nvgpu: volta+: convert SM broadcast to SM unicast 
Starting volta, multiple SMs are supported. Ctxsw regops
require SM broadcast registers to be converted to unicast registers.

Bug 2960720
JIRA NVGPU-5502

Change-Id: Id6e87fcc993587317bcd9b6958233e39d6b41fa7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
98886cd28e gpu: nvgpu: volta+: add litter value for SM UNIQUE_BASE & SHARED_BASE 
Starting volta, multiple SMs are supported. In order to convert
SM broadcast registers to unicast registers, sm_unique_base
and sm_shared_base are required.

Bug 2960720
JIRA NVGPU-5502

Change-Id: Ie9ebc0ab814cf551801f6cac1298a791d184f894
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a039261724 gpu: nvgpu: add gr.process_context_buffer_priv_segment gops 
1. Add below gr gops to process context buffer's priv segment.
int (*process_context_buffer_priv_segment)(struct gk20a *g,
					 enum ctxsw_addr_type addr_type,
					 u32 pri_addr,
					 u32 gpc_num, u32 num_tpcs,
					 u32 num_ppcs, u32 ppc_mask,
					 u32 *priv_offset);
Update all chips to use gr_gk20a_process_context_buffer_priv_segment()
as new gr hal.
2. Add and use ppc, tpc and etpc count functions to retrieve total count.

Bug 2960720
JIRA NVGPU-5502

Change-Id: I6cec36c323ff49ded853cd5cbfd9e0a28602b8ed
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
a629b48013 gpu: nvgpu: split channel sema wakeup function 
Extract the functionality to post semaphore signals to one channel into
a separate function for readability.

Jira NVGPU-5491

Change-Id: Ib5e8d34f42a64c253b3b3b8cb9e2c5dd2656fd1f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
23d6b36101 gpu: nvgpu: add dma_fence semaphore support 
Support exporting and importing semaphore-based synchronization with the
stable dma-fence API. The "Android" sync fence API used until now is
deprecated.

The Android sync framework is still kept as the default.

Jira NVGPU-5353

Change-Id: I9e57947adeb4d2ef5d59135ed7d008553c44f97c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Bitan Biswas
7d6645d7af gpu: nvgpu: fuse and chip revision updates for k5.4 
1. use fuse.h instead of chip-id.h in k5.4.
2. chip revision checks for TEGRA210_REVISION_A04p and
   TEGRA194_REVISION_A01 are replaced with chip id
   check and revision check for TEGRA_REVISION_A04p
   and TEGRA_REVISION_A01.

Bug 200591811
Bug 200602747

Change-Id: I3383b691e400265723214e81ac193fd1cc1946e3
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
3bd0430aa8 gpu: nvgpu: for nvgpu-next do not reset grce engines twice 
NVGPU_ENGINE_GRCE engines are getting reset twice, once in
nvgpu_init_prepare_hw() and other time in nvgpu_ce_init_support().

To avoid this, remove NVGPU_ENGINE_GRCE engines reset from
nvgpu_init_prepare_hw.

JIRA NVGPU-5288

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Ic03dbff0a74e973ba423abfa004e49bdd8e451f7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336450
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d44ed9d3a8 gpu: nvgpu: rollback gpfifo on error 
Submitting new work may fail in the middle of writing the gpfifo
entries. Undo the increments on the gp_put shadow pointer in case of
error to avoid submitting wrong data during the next submit.

Jira NVGPU-5491

Change-Id: I064eaac8773b24da0a56db79ac6bfd07c008da03
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340464
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
f388b1f596 gpu: nvgpu: simplify cmdbuf construction in submit 
Split out the wait cmd and incr cmd setup work in submit path to
separate functions to minimize cyclomatic complexity and to increase
readability.

Jira NVGPU-5491

Change-Id: I7dfabd2de287ae10aaae9fb8d4d85d752db8631c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Dinesh
b79bee9cea gpu: nvgpu: CCM reduction for vidmem clear 
This is added to make a common function  nvgpu_vidmem_clear_fence_wait
that can be used by multiple callers. This helps to reduce CCM and
code duplication in vidmem unit.

JIRA NVGPU-990

Change-Id: I3a7090588abda68900849443f6a8fa1bfa246bf4
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332691
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 2020-12-15 14:13:28 -06:00
Shashank Singh
701c0efa8d gpu: nvgpu: enable syncpoint shim when nvlink is disabled 
Create an iova for syncpoint shim region in case iommu is enabled and
nvlink is disabled. This iova is then used to created nvgpu mem with
nvgpu_mem_create_from_phys. Which is then used to create gpu mappings.
Instead of creating another variable g->syncpt_mem's priv is used to
store the sgt which needs to be freed on deinit.

Jira NVGPU-5376

Change-Id: I0b5a8320fbbb68031912ae88cfe8c2c3804fb813
Signed-off-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332643
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
3875c0825f gpu: nvgpu: avoid sema/channel dependencies 
Move the per-channel hw semaphore object to be owned by the channel sync
(just like with syncpoints, too). Store just the channel ID in the hw
sema for debug prints to get rid of sema->channel dependencies. Make
nvgpu_semaphore_alloc() take a hw sema instead of a channel.

Fix up some channel-related documentation that has been incorrect.

Jira NVGPU-5353

Change-Id: I04d49da3aac50a4cea32e7393f48e6f85a80ca0d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339931
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 2020-12-15 14:13:28 -06:00
Abdul Salam
97de1ba74d gpu: nvgpu: Use unified struct to store slave freq 
Instead of using multiple struct use a single nvgpu_clk_slave_freq
to store the slave freq of gpcclk.
With this patch single struct can be used by both clk_arb and clk_domain.
This will remove nvgpu_set_fll_clk struct as nvgpu_clk_slave_freq serves
the purpose.

NVGPU-4692

Change-Id: Ie45d63e4376b83e153a9aa75e2c4631c6dad857b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339213
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 2020-12-15 14:13:28 -06:00
rmylavarapu
700bd83b41 gpu: nvgpu: Rename/clean boardobj unit 
-Removed unwanded boardobj includes
-Renamed functions as struct as per usage

NVGPU-4484

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I792a4b64075d5e87f911c1073717dbe7107227a1
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335991
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
rmylavarapu
8e545ef04b gpu: nvgpu: Fix boardobj allocation size 
In current implementation we are allocating boardobj
in nvgpu_boardobj_construct_super for all units and assigning
that pointer to boardobj type, as the size differe for different
units assigning the boardobj pointer to a common type will
give violations. Fixing them by allocating mem a head
and later call construct_super for elements initialization.

NVGPU-4484

Change-Id: I9b5ed1a6d8418fec48a29eee38d55fc7d83fcfab
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335989
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
0115c26f1b gpu: nvgpu: Boardobj lite unit refactor 
As boardobj unit is used only in PMU, the plan is to move
all the boardobj related functions/structures and Macros
to boardobj specific folders. This will remove unnecessary
usage of boardobj outside PMU.

NVGPU-4484

Change-Id: I9f0fda32e6affd1fce218eb0ac638a9dfc8b99c3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335986
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Alex Waterman
5f0fdf085c nvgpu: unit: Add new mock register framework 
Many tests used various incarnations of the mock register framework.
This was based on a dump of gv11b registers. Tests that greatly
benefitted from having generally sane register values all rely
heavily on this framework.

However, every test essentially did their own thing. This was not
efficient and has caused a some issues in cleaning up the device and
host code.

Therefore introduce a much leaner and simplified register framework.
All unit tests now automatically get a good subset of the gv11b
registers auto-populated. As part of this also populate the HAL with
a nvgpu_detect_chip() call. Many tests can now _probably_ have all
their HAL init (except dummy HAL stuff) deleted. But this does
require a few fixups here and there to set HALs to NULL where tests
expect HALs to be NULL by default.

Where necessary HALs are cleared with a memset to prevent unwanted
code from executing.

Overall, this imposes a far smaller burden on tests to initialize
their environments.

Something to consider for the future, though, is how to handle
supporting multiple chips in the unit test world.

JIRA NVGPU-5422

Change-Id: Icf1a63f728e9c5671ee0fdb726c235ffbd2843e2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335334
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 2020-12-15 14:13:28 -06:00