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-GA10B PMU IRQ registers are not accessible when NVRISCV PRIV lockdown is engaged, so need to skip modifying/configuring IRQ registers. -Add new GA10B PMU HAL for PMU IRQ support. -GA10B PMU IRQ HAL checks for PRIV lockdown and if enabled then just enable PMU interrupt from MC, if not enabled then follows legacy chip method to configure the PMU interrupt. Bug 200780546 Change-Id: Idecf460a58b0e334f9ca2301ce8ee33b760b73c0 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2603245 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>