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Fix MISRA violations for Rule 10.6 and 10.8 in gr.init unit Assigning composite expression of width 32 to a target of width 64. Cast from 32 bit width to a wider 64 bit type. Jira NVGPU-3390 Jira NVGPU-3391 Change-Id: Id06fa9c90ae6cea1a7251b7834aca3f2c2f76e53 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2116154 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>