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Rule 10.x necessitates operands to have essential type; left and right operands are required to be of same width and type. Rule 12.2 requires right hand operand of shift operator to be within range 0 to 1 less than width of left hand operand. Rule 20.7 requires macro parameters to be enclosed in parentheses. This patch fixes above listed MISRA rule violations in nvgpu/hal/fifo/ramin_gv11b_fusa.c. Jira NVGPU-3821 Change-Id: I2d85cf8c4599e6d6f7bab1a2c3ce161d4ec93826 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2153720 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>