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Bhadram Varka
b704cd863a xpcs: SW override method for UPHY Rx lane bringup 
Bug 5087758

Change-Id: Icd75b08b4644016db21e74a5188e515b387b0899
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3399512
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Revanth Kumar Uppala <ruppala@nvidia.com>
rel-38_eng_2025-10-06 jetson_38.2.2 jetson_38.2.1 jetson_38.2 		2025-07-14 16:57:35 -07:00
Revanth Kumar Uppala
6f0373c303 xpcs: Revert RX EQ training changes 
Revert RX EQ training changes done via SW override method
This will be taken care along with UPHY RX lane bringup through
SW override method

Bug 5087758

Change-Id: If5d0cf86b60324782aa430f55e759e934e77ba35
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3399510
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-07-14 16:57:31 -07:00
Igor Mitsyanko
fddedb16a8 Merge branch 'dev/cam-coe' of ssh://git-mirror-santaclara.nvidia.com:12001/kernel/nvethernetrm into rel-38 
Jira L4T-7360

Change-Id: I9a88ed32f9f806e837fa15acc1269e92135ccabb
Signed-off-by: Anubhav Rai <arai@nvidia.com>
Signed-off-by: Igor Mitsyanko <imitsyanko@nvidia.com>
 2025-06-21 23:57:35 +00:00
Igor Mitsyanko
949b3e962e macsec: cleanup for release 
Cleanup code to prepare for rel-38 release branch integration.

Change-Id: I2aff4cd730a6a2ad1e17f58fed4e37023ffd4391
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3390116
Tested-by: Igor Mitsyanko <imitsyanko@nvidia.com>
Reviewed-by: Igor Mitsyanko <imitsyanko@nvidia.com>
 2025-06-21 01:09:30 -07:00
Srinivas Ramachandran
b41d40ece9 Revert "coe: Disable seq num check in macsec for COE" 
This reverts commit b8fe432eea.

Reason for revert: HSB FW has been updated to include resetting the frame number for every SOF. This has been verified with Eagle AIO modules with HSB FW FPGA version=0x2505 datecode=0xf1a72011

CT26X-1921

Change-Id: I67f83a2d7de93187276266689d34d68f8c551f7e
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3381926
 2025-06-17 14:49:16 -07:00
Revanth Kumar Uppala
8a43cf10fb osi: Add RX_EQ training via SW override method 
Add RX_EQ training after mgbe link up to overcome insertion loss

Bug 5277708
Bug 5017313

Change-Id: I19270c68cc570b3320c1db24298439cfbf412170
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
(cherry picked from commit ac35e507b220de89de9d856e2ba0cdae59656b1f)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3383664
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-06-11 11:59:47 -07:00
Igor Mitsyanko
9aa28e802d osi: coe: do not use CoE channels 
The MGBE driver logic should not use Camera Over Ethernet DMA channels
for normal Rx/Tx.

Track which channels are CoE channels separately from normal channels.

In some cases MTL queue number is used in place of DMA channel, as it is
assumed by a driver that DMA channel maps 1:1 to MTL queue number. Fix
such cases to make sure CoE channels are not selected for Tx by a driver
and are not part of RSS or multicasting.

Change-Id: I18da9a3e51168c9e3c95278beb179b44e8647f36
Signed-off-by: Igor Mitsyanko <imitsyanko@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3330334
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-06-06 12:55:18 -07:00
Igor Mitsyanko
10cedf73e6 Merge branch 'dev-main' of ssh://git-mirror-santaclara.nvidia.com:12001/kernel/nvethernetrm into HEAD 
Change-Id: I5c60e0cd71a67f7ef2c89ab50d56c8212c373af3
Signed-off-by: Igor Mitsyanko <imitsyanko@nvidia.com>
 2025-06-04 15:04:40 -07:00
Narayan Reddy
53c6e3ffc4 osi: core: use appropriate sleep function 
issue: on some setups link partner is not connected
and hence the sw retries for the link with a delay of
100msec for every retry. In case of HVRTOS udelay is a
busy loop and it starves other tasks on the CPU.

Fix: Use udelay for small wait checks, and usleep
for larger delays.

Bug 5278971

Change-Id: If2c29475dbd552a8da549668460385f9402e612b
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3371471
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2025-05-31 10:04:53 -07:00
Aniruddha Paul
c46dc5ac44 osi-dma: Set IOC for PTP packets for use_tx_descs INTR policy 
Set IOC for every Tx PTP packets. This will be set only
on PTP packets when the interrupt policy is based on
descriptor count but not on packet count.

PTP for a single doamin maximum number of pakets allowed:
logAnnounceInterval: −3 (Sync every 1/8 sec)
logSyncInterval: Min: −7 (Sync every 1/128 sec)
logMinPdelayReqInterval:−7 (Pdelay_Req every 1/128 sec)

At max we can have 128 Tx PTP packets per second/Domain.
We can tolerate 128 interrupts per second.

The standard 802.1AS supports only one domain number "0".
The default values for 802.1AS std: 0, -3, 0 respectively.

Bug 4993045

Change-Id: I5b598b8ee1a06f265cf241a719d5fba4c4df6f1f
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3340046
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-05-26 12:23:02 -07:00
Rakibul Hassan
2f5af56d03 Merge remote-tracking branch 'origin/dev-main' into dev/cam-coe 
Change-Id: Ia0e305f3fe5204dda23ed40c676874106b1eab4d
 2025-05-07 01:02:27 +00:00
Mahesh Patil
df0be09573 osi: Enable BASE-R FEC support for 25G 
Bug 4674473

Change-Id: Ic4a0f67158449094a9489afbe8de8d2efc0fdf99
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3316844
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-05-01 17:37:42 -07:00
Aniruddha Paul
c13a414c34 osi-dma: Fix pktid for both Orin and Thor 
Add pktid increment macro and and also fix
thor macro GET_TX_TS_PKTID_T264 to get the
pktid.

Bug 4993045

Change-Id: Ibe58f4353d358e9449374f5bf72990e6021bfc5e
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3333051
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2025-04-29 12:45:23 -07:00
Bibhay Ranjan
7d5ed69635 osi: core: add support to program phy registers 
This new function will be called from the dt
parsing and loading the phy based configuration
at different states of phy.
The API works transparent to the phy and hence
requires register programming directly instead
irrespective of direct/indirect addressing.

for eg. if a read needs 2 register access using
indirect addressing, both the reads have to be
done by dt.

Bug 4912541

Change-Id: Idadd6ddef7b6251511d1ce2f6bfa6d482e8d5e94
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3264576
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-04-28 19:51:03 -07:00
Rakesh Goyal
82e1005aec osi: core: common: update HADV value 
Issue: HADV values were not correct
Fix: HW suggested new HADV values.
program same based on speed.

Bug 4787164
Bug 4310565

Change-Id: Ic659967e0e342c1b52de1ca067af900eaebf8e86
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3303958
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-04-28 08:12:23 -07:00
Hareesh Kesireddy
5ef244ecca osi: dma: fix doxygen for mgbe_get_rx_hwstamp() 
- Fixed doxygen comments for mgbe_get_rx_hwstamp().

Bug 5199635

Change-Id: I63cc63a36cfb3692c1d34647bb5620743f3303fa
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3345385
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-04-26 17:20:30 -07:00
Hareesh Kesireddy
b394b50ed4 osi: dma: mgbe: drop ctxt desc for TSD 
Issue description:
- For announce / managament / signaling ptp packets,
  MGBE populates context descriptor with Timestamp dropped status (TSD).
  It leads to 10us busy loop in rx path for every such packet.
- Also, it results into forwarding context descriptor to OSD
  through receive callback, leads to error spew from OSD.

Fix description:
- Removed busy loop when TSD is set in mgbe context descriptor.
- Consume context descriptor in OSI DMA itself when packet
  context descriptor found to be available (CDA).

Bug 5199635

Change-Id: I92785c5c434256d072405c4dd616486f64de2ff6
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3338247
(cherry picked from commit 1f165baec2635ffae05661306bd2a6ebba339601)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3344960
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-04-26 17:20:25 -07:00
Narayan Reddy
58bbd73ad6 osi: core: move hsi configuration to nvethernetrm 
issue: during sc7 fsm timeout hsi errors are
observed.

fix: disable hsi configuration during suspend and
re enable it during resume, to accomadate this
added enabling of hsi in core_init and disabling of
hsi in core_deinit, since these are called during
resume and suspend too.

Bug 5133679

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: Idb19e5283e66574571705691332916eb877bbf0d
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3340254
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
 2025-04-23 14:59:01 -07:00
Narayan Reddy
3e4f343b27 osi: core: correct programming of MAC_FPE_CTS 
Issue: upon code review, identified that currently
values are read from MTL_FPE_CTS register and modifying
as per requirement and programming it to MAC_FPE_CTS register
which is incorrect.

Fix: Read the values of MAC_FPE_CTS register, modify them
as per requirement and programming it back to MAC_FPE_CTS
register

Bug 5163057

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: Ibdb48684ea396f175490e61cf097a8a186d52670
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3341918
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-04-22 17:58:35 -07:00
Bhadram Varka
ddab1dc9b4 mgbe: Ensure UPHY is up before reporting link OK 
Issue:
1) During switch reset, MGBE MAC generates a Local Link Fault
   common interrupt.
2) The interrupt routine triggers restart_lane_bring_up(),
   which schedules the link monitor timer inside the Ethernet
   Server.
3) As part of this routine, link status change interrupts
   (e.g., Local Fault, Remote Fault, Link OK) are disabled to
   avoid spurious triggers.
4) Meanwhile, if a PTP Tx packet is sitting in the MTL TX
   FIFO, it triggers a common interrupt.
5) The ISR for this common interrupt reads the status
   register. Since the Link OK flag is set, the server
   assumes the link is up.
6) This schedules the link monitor timer again (as in step 2).
7) Since the Link OK flag is already set, the monitor timer
   exits without calling OSI_CMD_SET_SPEED (which is
   responsible for UPHY lane bring-up).
8) As a result, when the switch reset is released, the UPHY
   lane is not brought up, and the Ethernet link remains
   broken.

Fix:
Check UPHY link status before giving link up.

Bug 5206852

Change-Id: I98c49f710e2570480583c40255cda912af6ab1b5
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3339051
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-04-22 11:33:34 -07:00
Bhadram Varka
280bf8b16d osi: core: use MDC CR passed from OSD 
o Use MDC CR value, which is passed from OSD
o Set CRS for MGBE to generate higher MDC frequencies
o Remove OSI_CMD_MDC_CONFIG related code which is no
longer required.

Bug 5147775

Change-Id: I4763d6ccaee7f5cc078a3542c069d8052d6c3637
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3336068
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-04-19 16:27:29 -07:00
Sanath Kumar Gampa
9ffb4bb396 osi:dma: Fix below Cert errors 
CERT INT30-C
CERT INT08-C

Jira NET-2907

Change-Id: I4d08f3e3142a2721b9bfb0de1b21fc44dbaafcc7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3314573
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2025-04-17 23:22:24 -07:00
Narayan Reddy
c8e1bd95a2 osi: core: mgbe: add hsi support for t26x 
Added hsi support for below HSIs

T264-MGBE_HSIv2-1
T264-MGBE_HSIv2-2
T264-MGBE_HSIv2-38
T264-MGBE_HSIv2-6
T264-MGBE_HSIv2-7
T264-MGBE_HSIv2-8
T264-MGBE_HSIv2-59
T264-MGBE_HSIv2-60
T264-MGBE_HSIv2-72
T264-MGBE_HSIv2-78

JIRA NET-1948
Bug 4778785

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: Id0f64470134e8b98962911a95c69eeb6d69a41cf
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3260086
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
 2025-04-17 23:12:56 -07:00
Narayan Reddy
c6e5d88ef2 osi: core: eqos: add hsi support for t26x 
Added hsi support for below HSIs

T264-EQOS_HSIv2-1
T264-EQOS_HSIv2-31
T264-EQOS_HSIv2-2
T264-EQOS_HSIv2-34
T264-EQOS_HSIv2-35
T264-EQOS_HSIv2-59
T264-EQOS_HSIv2-33

JIRA NET-1946
Bug 4778785

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I95c94fac3053860fb7d6d23dec2c79330c3083b5
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3259508
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-04-17 23:12:45 -07:00
Sanath Kumar Gampa
c75b27d803 osi:macsec: Do not create SC as part of init 
If  Secure Channel is created in the controller its corresponding Key
table has to be initialized else we see parity errors for the Key table.

This change will Make sure SC is not created as part of initialization.

Manual cherry-pick of below change as there is change is file structure
https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3323186

Bug 5145470

Change-Id: I129908efc76d244b6ed5466664c9f56acc6981a6
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3334769
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-04-17 03:26:52 -07:00
Mahesh Patil
3a59f31c77 osi: T26x: update delay for UPHY XPCS lane bringup 
- Update delay for 10G required when EQ is enabled.
 - Enable the EQ for 10G.
 - Update delay for eqos.

Bug 4790491

Change-Id: I63146b1a9ab03d5dbcdbc26e4d2a7ec48a15e497
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3270227
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
 2025-04-17 03:19:04 -07:00
Narayan Reddy
b5ed6001a7 osi: core: modify handling of RSS 
1) Modified RSS code to handle the same when
ethernet server is enabled
2) Add support for reading the RSS values
from MGBE HW

Bug 5129765

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I52a11696ee2e338f4ec8206d2aa6cc79283cf1e5
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3323780
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-04-15 07:32:48 -07:00
Bhadram Varka
b86290a392 osi: dma: Fix Tx/Rx ring length configuration 
Issue: DMA Tx/Rx ring length not updating correctly
after changing with ethtool.

The issue was caused by the ring length being read from
the hardware and then logically OR'd with the new ring length value. This resulted in the ring length being set to the value configured during boot, as the hardware was not reset in this process.
Instead of reading the value from the hardware and logically OR'ing it with the new value, directly set the ring length value to the hardware.

Fix:
Instead of reading the value from the hardware and logically OR'ing
it with the new value, directly set the ring length value to the hardware.

Bug 5158977

Change-Id: I23dc3f18f21c884feea9845e439fbf2783d68bcb
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3323922
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-04-08 17:24:29 -07:00
Aniruddha Paul
58162348f1 mgbe: Read the MGBE wrap common status instead of enable reg 
For MGBE common interrupt we are accounting HSI errors even
though there are no HSI error like correctable errors and
uncorrectable errors. This is due to accounting of enable
bits instead of status bit.

Bug 5199430
Bug 4993045

Change-Id: I2c361b2065bfcd038ff3199eacad5eaeb2ebaf1b
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3330482
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-04-05 02:50:14 -07:00
Igor Mitsyanko
2308110b4a Merge branch 'dev-main' of ssh://git-mirror-santaclara.nvidia.com:12001/kernel/nvethernetrm into HEAD 
Change-Id: Ib389d3b10f2c840dcaffde011c052f388e224fde
 2025-04-04 19:59:35 +00:00
Aniruddha Paul
2c82811fa7 nvethernetrm: Fix Doxygen warning and errors 
Fix Doxygen errors and warnings for NvethernetCL
and NvethernetRM and Macsec Units

Jira NET-2934

Change-Id: Ibbbfe93f3cf418f77c4eb917eafd2a0c194fdacb
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3314210
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-03-22 11:16:00 -07:00
Igor Mitsyanko
ce686da6d3 Merge branch 'dev-main' of ssh://git-mirror-santaclara.nvidia.com:12001/kernel/nvethernetrm into HEAD 
Change-Id: I94ffcc398cd0f1ffd0e091ac111ade6b093d1a7f
 2025-03-18 22:20:50 +00:00
Sanath Kumar Gampa
34a44e231d osi: Fix Static anaysis issues in NvEthernet 
JIRA NET-2044

Change-Id: Ifa82224cf3448c3f57ac5f56f3f5f062c9e1a331
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3274038
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-03-11 06:42:14 -07:00
Igor Mitsyanko
7c79f9d11d mask MACSEC Rx IRQ 
Signed-off-by: Igor Mitsyanko <imitsyanko@nvidia.com>
Change-Id: Ic992955fdf5b0adba45db4bdff5f09ed93c2cae3
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3316134
 2025-03-10 19:47:55 -07:00
Narayan Reddy
955911e111 eqos: remove duplicate null check 
1) Remove duplicate null check
2) Remove unused code of eqos padctrl settings

Bug 4449611

Change-Id: I5437f655181d0e9a102100d3d6deb6a1aa53ca7f
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3117233
(cherry picked from commit ebf57640e2b7dd79ef95228280f1c165b9c2b789)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3134313
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
 2025-03-10 08:08:31 -07:00
Narayan Reddy
cc7a258b43 osi: core: add skip AN support for USXGMII mode 
provide an option to skip/allow AN in USXGMII
mode

Bug 4932519

Change-Id: I917a091dde498e7edcb7f504550437e39e3e0146
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3303212
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-03-09 15:02:27 -07:00
Narayan Reddy
57ebd08cbc osi: core: increase delay for 25G 
Issue:
data transfers on 25G interface is not working

Fix
This seems a regression caused by the change 1e8dfaf where
updated retry_delay for 25G is not being used. Later this
part of code is being removed to fix QNX SDP7.1 compiler error
with the change 248fb63. In short existing delay of 1usec is
not sufficient for25G, so increase the same to support 25G

Bug 5015243

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I5892b428add6435130af94a4b2560dd3df73107c
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3307461
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2025-03-07 07:02:00 -08:00
Sanath Kumar Gampa
144d7dc226 osi:dma: Fix top-25 Static Analysis issues 
Fixed below rules:
CERT INT32-C
CERT INT30-C
CERT INT08-C
CERT EXP39-C

Jira NET-2045

Change-Id: I1cf3ea2d2f037f70821eaabc737235ce8a592b15
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3275403
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-02-27 17:03:46 -08:00
Sanath Kumar Gampa
db9b81458e nvethernetrm: Fix top-25 MISRA issues 
Fixed below rules:
CERT STR31-C
CERT INT32-C
CERT INT30-C
CERT INT08-C
CERT ARR30-C
CERT EXP39-C
OVERFLOW_BEFORE_WIDEN

Jira NET-2045

Change-Id: I2f86e110747a6a4e21b1bf80af2e7a98ad51f3db
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3275363
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-02-27 17:03:36 -08:00
Igor Mitsyanko
d1faf8f1d1 Merge branch 'dev-main' of ssh://git-mirror-santaclara:12001/kernel/nvethernetrm into cam-coe 
Change-Id: I620775583da9168daade9bd5ceb74b846e0a944e
 2025-02-26 23:28:30 +00:00
Bhadram Varka
a0448dd10f dma: EQOS: WAR to address data corruption issue 
Issue:
During stress testing of the GPU/DLA, the Ethernet software reads the Rx
buffer because the DMA descriptor OWN bit is cleared (SW owned).

However, the write to the system memory is still in progress. As a
result, incomplete packets are read by the software and passed to the
network stack, leading to errors related to checksums.

WAR:
1. Get SW processing descriptor physical address.
2. Get HW processing descriptor physical address.
3. If both are equal then get the DMA debug status from the HW.
4. Process the packet only if RPSX value is not 5/6/7.

Also this change removes the code which sets the DSPW for EQOS.

Bug 3788208
Bug 4486046

Change-Id: I33a8a1762e2c6cf8ede8c7abade577e76c3baec7
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3123288
(cherry picked from commit 6d481466b64c66d74207f32079e8b0edac51bc66)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3256432
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-02-21 20:15:56 -08:00
Srinivas Ramachandran
b8fe432eea coe: Disable seq num check in macsec for COE 
HSB does not use proper seq. num currently. Every
SOF is supposed to start with seq 0 in COE header. BUt HSB
preserves last value incorrectly. This is resulting in
frame errors being reported by macsec.

Till HSB FPGA can be updated, disable seq. check for GTC.

JIRA CT26X-1895

Change-Id: I654fbe6faab187ea416b38d01c30694ce1df0ee2
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3305644
 2025-02-18 21:36:14 -08:00
Srinivas Ramachandran
b5a2453a26 COE: disable macsec controlled port check for VF 
By default, don't enable controlled port on the VF
mac. COE logic requires macsec controller enabled, but
does not need secure channel for the VF MAC.

JIRA CT26X-1917

Change-Id: I05d18adfdb1c243d05ab04463ddf33015b785acd
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3303545
Tested-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-02-17 22:30:30 -08:00
Mohan Thadikamalla
13f613008a common: Exclude internal functions from ICDs 
Issue:
Internal functions were included
in the NVETHERNETRM_PIF and NVETHERNETCL_PIF
ICD Doxygen compilation.

Fix:
Exclude internal function documentation
from NVETHERNETRM_PIF and NVETHERNETCL_PIF ICDs

Jira NET-2169
Jira NET-2170

Change-Id: I62ee0ff32efe0c9698fd32ce36ee35da408b40c0
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3294123
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-02-14 02:43:04 -08:00
Igor Mitsyanko
b11e300f39 Merge branch 'dev-main' of ssh://git-mirror-santaclara:12001/kernel/nvethernetrm into cam-coe 
Change-Id: I0991d9039e2411098146c8052db04c3bee369cc7
 2025-02-13 06:03:58 +00:00
Srinivas Ramachandran
d808e1a3cb nvethernetrm: Add support for COE in MGBE 
Bug 4748432

Change-Id: Ia37c54d162c6bd480fe3e875bfc50dbe5de02928
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3298865
Reviewed-by: Igor Mitsyanko <imitsyanko@nvidia.com>
 2025-02-12 14:42:26 -08:00
Sanath Kumar Gampa
4864073566 nvethernetrm: update the License for the osi files 
Bug 5068365

Change-Id: Ib25276760ec49685a918354c31364f23093f9558
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3297947
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-02-08 20:08:22 -08:00
Aniruddha Paul
dbd51a2eb0 nvethernetrm: Add PBL notes for Doxygen 
Added notes for PBL and its relation to MTU

Bug 4961507

Change-Id: I1bfcd10b5868b880f4ba7f1ae8e38dbac690c75d
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3280253
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-02-01 18:11:22 -08:00
Mahesh Patil
e250e2722d nvethernetrm: Limit lane bring up error print 
Bug 4990818

Change-Id: I8d088a450ab25433ded5f7ad7cb0d3b56af0b9f1
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3280530
Reviewed-by: Anders Ma <andersm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3279684
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-01-29 22:54:32 -08:00
Mahesh Patil
a47f2c893d osi: Enable BASE-R FEC before lane bringup 
Bug 4674473

Change-Id: I1aa204b104a33361fe21bf6b37586e018304de0f
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3225338
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-01-29 22:42:02 -08:00