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593 Commits

Author SHA1 Message Date
Igor Mitsyanko
fddedb16a8 Merge branch 'dev/cam-coe' of ssh://git-mirror-santaclara.nvidia.com:12001/kernel/nvethernetrm into rel-38 
Jira L4T-7360

Change-Id: I9a88ed32f9f806e837fa15acc1269e92135ccabb
Signed-off-by: Anubhav Rai <arai@nvidia.com>
Signed-off-by: Igor Mitsyanko <imitsyanko@nvidia.com>
 2025-06-21 23:57:35 +00:00
Revanth Kumar Uppala
8a43cf10fb osi: Add RX_EQ training via SW override method 
Add RX_EQ training after mgbe link up to overcome insertion loss

Bug 5277708
Bug 5017313

Change-Id: I19270c68cc570b3320c1db24298439cfbf412170
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
(cherry picked from commit ac35e507b220de89de9d856e2ba0cdae59656b1f)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3383664
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-06-11 11:59:47 -07:00
Igor Mitsyanko
9aa28e802d osi: coe: do not use CoE channels 
The MGBE driver logic should not use Camera Over Ethernet DMA channels
for normal Rx/Tx.

Track which channels are CoE channels separately from normal channels.

In some cases MTL queue number is used in place of DMA channel, as it is
assumed by a driver that DMA channel maps 1:1 to MTL queue number. Fix
such cases to make sure CoE channels are not selected for Tx by a driver
and are not part of RSS or multicasting.

Change-Id: I18da9a3e51168c9e3c95278beb179b44e8647f36
Signed-off-by: Igor Mitsyanko <imitsyanko@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3330334
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-06-06 12:55:18 -07:00
Rakibul Hassan
2f5af56d03 Merge remote-tracking branch 'origin/dev-main' into dev/cam-coe 
Change-Id: Ia0e305f3fe5204dda23ed40c676874106b1eab4d
 2025-05-07 01:02:27 +00:00
Bibhay Ranjan
7d5ed69635 osi: core: add support to program phy registers 
This new function will be called from the dt
parsing and loading the phy based configuration
at different states of phy.
The API works transparent to the phy and hence
requires register programming directly instead
irrespective of direct/indirect addressing.

for eg. if a read needs 2 register access using
indirect addressing, both the reads have to be
done by dt.

Bug 4912541

Change-Id: Idadd6ddef7b6251511d1ce2f6bfa6d482e8d5e94
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3264576
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-04-28 19:51:03 -07:00
Bhadram Varka
280bf8b16d osi: core: use MDC CR passed from OSD 
o Use MDC CR value, which is passed from OSD
o Set CRS for MGBE to generate higher MDC frequencies
o Remove OSI_CMD_MDC_CONFIG related code which is no
longer required.

Bug 5147775

Change-Id: I4763d6ccaee7f5cc078a3542c069d8052d6c3637
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3336068
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-04-19 16:27:29 -07:00
Narayan Reddy
c8e1bd95a2 osi: core: mgbe: add hsi support for t26x 
Added hsi support for below HSIs

T264-MGBE_HSIv2-1
T264-MGBE_HSIv2-2
T264-MGBE_HSIv2-38
T264-MGBE_HSIv2-6
T264-MGBE_HSIv2-7
T264-MGBE_HSIv2-8
T264-MGBE_HSIv2-59
T264-MGBE_HSIv2-60
T264-MGBE_HSIv2-72
T264-MGBE_HSIv2-78

JIRA NET-1948
Bug 4778785

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: Id0f64470134e8b98962911a95c69eeb6d69a41cf
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3260086
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
 2025-04-17 23:12:56 -07:00
Narayan Reddy
c6e5d88ef2 osi: core: eqos: add hsi support for t26x 
Added hsi support for below HSIs

T264-EQOS_HSIv2-1
T264-EQOS_HSIv2-31
T264-EQOS_HSIv2-2
T264-EQOS_HSIv2-34
T264-EQOS_HSIv2-35
T264-EQOS_HSIv2-59
T264-EQOS_HSIv2-33

JIRA NET-1946
Bug 4778785

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I95c94fac3053860fb7d6d23dec2c79330c3083b5
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3259508
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2025-04-17 23:12:45 -07:00
Sanath Kumar Gampa
c75b27d803 osi:macsec: Do not create SC as part of init 
If  Secure Channel is created in the controller its corresponding Key
table has to be initialized else we see parity errors for the Key table.

This change will Make sure SC is not created as part of initialization.

Manual cherry-pick of below change as there is change is file structure
https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3323186

Bug 5145470

Change-Id: I129908efc76d244b6ed5466664c9f56acc6981a6
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3334769
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-04-17 03:26:52 -07:00
Narayan Reddy
b5ed6001a7 osi: core: modify handling of RSS 
1) Modified RSS code to handle the same when
ethernet server is enabled
2) Add support for reading the RSS values
from MGBE HW

Bug 5129765

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I52a11696ee2e338f4ec8206d2aa6cc79283cf1e5
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3323780
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-04-15 07:32:48 -07:00
Igor Mitsyanko
ce686da6d3 Merge branch 'dev-main' of ssh://git-mirror-santaclara.nvidia.com:12001/kernel/nvethernetrm into HEAD 
Change-Id: I94ffcc398cd0f1ffd0e091ac111ade6b093d1a7f
 2025-03-18 22:20:50 +00:00
Sanath Kumar Gampa
34a44e231d osi: Fix Static anaysis issues in NvEthernet 
JIRA NET-2044

Change-Id: Ifa82224cf3448c3f57ac5f56f3f5f062c9e1a331
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3274038
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
 2025-03-11 06:42:14 -07:00
Narayan Reddy
cc7a258b43 osi: core: add skip AN support for USXGMII mode 
provide an option to skip/allow AN in USXGMII
mode

Bug 4932519

Change-Id: I917a091dde498e7edcb7f504550437e39e3e0146
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3303212
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2025-03-09 15:02:27 -07:00
Sanath Kumar Gampa
db9b81458e nvethernetrm: Fix top-25 MISRA issues 
Fixed below rules:
CERT STR31-C
CERT INT32-C
CERT INT30-C
CERT INT08-C
CERT ARR30-C
CERT EXP39-C
OVERFLOW_BEFORE_WIDEN

Jira NET-2045

Change-Id: I2f86e110747a6a4e21b1bf80af2e7a98ad51f3db
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3275363
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-02-27 17:03:36 -08:00
Igor Mitsyanko
d1faf8f1d1 Merge branch 'dev-main' of ssh://git-mirror-santaclara:12001/kernel/nvethernetrm into cam-coe 
Change-Id: I620775583da9168daade9bd5ceb74b846e0a944e
 2025-02-26 23:28:30 +00:00
Mohan Thadikamalla
13f613008a common: Exclude internal functions from ICDs 
Issue:
Internal functions were included
in the NVETHERNETRM_PIF and NVETHERNETCL_PIF
ICD Doxygen compilation.

Fix:
Exclude internal function documentation
from NVETHERNETRM_PIF and NVETHERNETCL_PIF ICDs

Jira NET-2169
Jira NET-2170

Change-Id: I62ee0ff32efe0c9698fd32ce36ee35da408b40c0
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3294123
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-02-14 02:43:04 -08:00
Igor Mitsyanko
b11e300f39 Merge branch 'dev-main' of ssh://git-mirror-santaclara:12001/kernel/nvethernetrm into cam-coe 
Change-Id: I0991d9039e2411098146c8052db04c3bee369cc7
 2025-02-13 06:03:58 +00:00
Srinivas Ramachandran
d808e1a3cb nvethernetrm: Add support for COE in MGBE 
Bug 4748432

Change-Id: Ia37c54d162c6bd480fe3e875bfc50dbe5de02928
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3298865
Reviewed-by: Igor Mitsyanko <imitsyanko@nvidia.com>
 2025-02-12 14:42:26 -08:00
Sanath Kumar Gampa
4864073566 nvethernetrm: update the License for the osi files 
Bug 5068365

Change-Id: Ib25276760ec49685a918354c31364f23093f9558
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3297947
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-02-08 20:08:22 -08:00
Aniruddha Paul
dbd51a2eb0 nvethernetrm: Add PBL notes for Doxygen 
Added notes for PBL and its relation to MTU

Bug 4961507

Change-Id: I1bfcd10b5868b880f4ba7f1ae8e38dbac690c75d
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3280253
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2025-02-01 18:11:22 -08:00
Mohan Thadikamalla
67f9842d5e common: Fix ICD Doxygen Compilation 
Issue:
The ICD Doxygen compilation failed for the PPS group.

Fix:
Updated the Doxygen @addtogroup comments for
the PPS group to resolve the compilation issue.

Bug 4585654
Bug 5042311
Jira NET-2169

Change-Id: Ifefad8374b269ede6afa12ab781324a98eef3a8a
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3291256
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2025-01-28 20:35:48 -08:00
Bhadram Varka
a3d4368889 osi: frp: Include L4 SRC/DST ports in safety build 
Issue: L4 SRC/DST ports FRP configuration is not
working in safety builds because code is removed
from the safety builds.

Fix: Include L4 SRC/DST ports configuration in
safety builds

This change also fix the typo in the code

Bug 4821670

Change-Id: I575d00f199288fab14cf3744943050af914b1d58
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3258850
(cherry picked from commit db4982965cff2869d806327878ada17002a91763)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3286022
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2025-01-27 09:43:04 -08:00
Harsukhwinder Singh
2078f0d51e osi: core: Replace osd_usleep_range with osd_usleep 
Bug 4921002

Change-Id: Ia12aa1fb94a2b1fbe1afd0e7da3190857479c4f9
Signed-off-by: Harsukhwinder Singh <harsukhwinde@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3268811
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2025-01-22 23:28:47 -08:00
Rakesh Goyal
877664c2ec osi: add support for pps train in digital mode 
Issue: Support for PPS train requested

Fix: Added support for PPS train

Bug 4585654
Bug 5042311

Change-Id: I0f94b8b4a5cb72d0084ae7ac14e1843930f6a1e8
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3215524
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2025-01-22 08:35:13 -08:00
Sanath Kumar Gampa
3b9355578b osi: create new lib for T26x EQoS XPCS programming 
To support N1Auto platformw hich has different XPCS, seperated out the
T26x EQoS xpcs programming

Bug 4997903

Change-Id: I47d75b66b7c3e7a5b7f2ad2abe8452dd3c2e5656
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3268488
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2025-01-20 13:27:49 -08:00
Sanath Kumar Gampa
593c8fc44c nvethernetrm: Add DA to SCI LUT with peer MACID 
Bug 4754899

Change-Id: I5c15770793d2f64fb54b565fd046ad9f9d7cb4bf
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3237499
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-12-15 16:23:47 -08:00
Hareesh Kesireddy
6fa36e885d osi: use udelay in timestamp poll paths 
- Use udelay() for timestamp register poll paths
  to avoid linux crash issues.
- Reduce reg polling time to 10msec instead of 1sec.

Bug 4951493

Change-Id: Id86a05c91f5e54b48912409225e7d7a850b097a3
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3247162
(cherry picked from commit 3ccfb43c977bfdd5e38ed32eafda234e9972d888)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3250080
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
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Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2024-12-04 08:06:12 -08:00
Srinivas Ramachandran
1e8dfafa84 osi: Use osd_usleep vs osd_udelay appropriately 
Issue: osd_udelay is used irrespective of the
       duration of the delay/sleep. In certain
       environments like HVRTOS, udelay is a
       busy loop and it starves other tasks on the CPU.
Fix:   Use udelay only for small tight checks, and use
       usleep for larger delays.

Bug 4676601

Change-Id: I59d9a403f34d46c6e2d17ca6f7e8a277d5283db5
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3176350
(cherry picked from commit c2abe16a34af853f86fcaa4bb91b7036e2a8eb79)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3250083
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
 2024-12-04 08:06:03 -08:00
Mohan Thadikamalla
8b85eca5f2 OSI: Fix giza compilation Issues 
Issue:
Doxygen compilation issues were observed
due to changes associated with 4569357 bug.

Fix:
Updated Doxygen comments in the OSI public
header files to resolve the compilation errors.

Bug 4569357

Change-Id: I4b87a5a498e956678f25f2674e7d84aefac17767
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3257876
Reviewed-by: Aniruddha Paul <anpaul@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-11-28 12:55:14 -08:00
Sanath Kumar Gampa
35eda10b40 osi: Segregate the MACSEC HSI code 
Move MACSEC HSI code to MACSEC h/w specific lib

Bug 4942473

Change-Id: I8f04526f26774736d975fad340de3bfcbbc45dd1
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3243835
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2024-11-28 12:39:46 -08:00
Aniruddha Paul
fc6e9530b6 OSI: Set Tx IOC for every fixed number of descs 
A new field 'use_tx_descs' gets programmed by OSD layer.
Tx ring accounts current desc counts and when the current desc
count increases above use_tx_descs and the last bit is set
in the desc, we set the IOC bit.

Bug 4569357

Change-Id: Ida2c7b84e0096007b874e79e3b7502c997f71980
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3207582
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2024-11-20 21:53:02 -08:00
Aniruddha Paul
22a75ac576 osi: Remove duplicate macros 
The below macros were duplicated in the respective
components of osi/core and osi/dma.
1. MGBE_DMA_CHX_MAX_PBL
2. MGBE_DMA_CHX_PBL_16
3. MGBE_DMA_CHX_PBL_8
4. MGBE_DMA_CHX_PBL_4
5. MGBE_DMA_CHX_PBL_1
6. osi_valid_pbl_value()
7. osi_memset()

Move these common macros and APIs which are used by both
osi/core and osi/dma to include/osi_common.h

This also statically assigns TxPBL=16 for Orin.

Bug 4569357

Change-Id: I390e0ad9c0bfda47a1a7f9dd94cf5f7f45d96b9c
Signed-off-by: Aniruddha Paul <anpaul@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3211481
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-11-20 21:52:52 -08:00
Mohan Thadikamalla
8cf1ea5184 osi: Fix ICD doxygen compilation issues 
Issue:
ICD Doxygen compilation issues have been
observed with Docker version 1.9.0.

Fix:
Update the Doxygen comments in the OSI
public header files to resolve
the Doxygen compilation issues.

Jira NET-1801

Change-Id: I15f305cbdb1bb1a88132498886da353d2bbb714f
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3242062
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-11-07 16:22:45 -08:00
Sanath Kumar Gampa
25a07d7228 osi_core: macsec: Reorg MACSec code for DOS-SHR-10437 
Reorganize MACSec source code to accommodate N1Auto MACSec HW IP OSI
driver.

Separated MACSec hardware-specific code into a different static lib

Bug 4874880

Change-Id: I74e4cca8ba615def283ec938cc94985d32099190
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3214907
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
 2024-10-29 08:12:49 -07:00
Mahesh Patil
8ebeeaafe3 osi: Add osi dma/core release functions 
- Adding osi dma and osi core release function to release resources

Bug 4791340

Change-Id: I031d11ca34a31d2f7c5c8460251509714cba5509
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3214558
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-10-16 19:47:53 -07:00
Mahesh Patil
45f67fb52f osi: Add PCS BASE-R FEC setting 
Adding PCS BASE-R FEC setting using on
sysfs node

Bug 4674473

Change-Id: Icdc2300705d11ce2c96e2c8e1663599a3bb4fadd
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3201974
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
 2024-10-05 04:20:43 -07:00
Mahesh Patil
7afef3637f osi: Enable all MGBE 48 VDMA channels 
Bug 4746911

Change-Id: Ieff8f483df47083722b85ade5d591217c9a27380
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3178611
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-09-07 11:00:30 -07:00
Mahesh Patil
cfdfccb488 osi: FSI EQOS driver bring up 
Bug 4552441

Change-Id: I490f9680cc7a71754a64035fb7c63ba56d0287ba
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3166031
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Michael Hsu <mhsu@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-07-28 21:35:56 -07:00
Sanath Kumar Gampa
ca0db16125 osi: macsec: Update MACSEC_CONTROL1 per h/w 
1) Stop MAC transmit while enabling MACSEC
2) Disallow FPE and MACSEC co-existence
3) Update SOT for T264 MACSEC
4) 10M and 100M speeds are not supported by MACSec

Bug 4588266
Bug 4456073

Change-Id: I3bc598bae8d2786104c2018bac18cc49092adcdd
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3163257
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-07-02 05:08:44 -07:00
Sanath Kumar Gampa
c8272c3000 osi: fix mmc counters issue 
Reduce the ivc message size to lower than 2048 to fix a build error. To
reduce the same macsec mmc counters are updated with lower 4 bytes of
the register values

Bug 4703442

Change-Id: I72e936622ca9740ac1fe28cb19129437d5a67d2c
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3163253
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-07-02 05:07:46 -07:00
Mahesh Patil
c479ba1650 osi: T26x EQOS changes 
1) Added T26X EQOS bring up changes
2) Fixes added during bring up

Bug 4639097

Change-Id: I0036a12ad08d690bb62a655df6f4efd26a0bf585
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3152936
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-06-18 11:37:38 -07:00
Bhadram Varka
12bdb2f1ea osi: core: WAR Werror=frame-larger-than and ivc issue 
Issue:
1. compilation issue:
error: the frame size of 3232 bytes is larger than 2048 bytes
[-Werror=frame-larger-than=]

Because of increase in the value of OSI_MACSEC_SC_INDEX_MAX
it resulted in increase in the size of ivc_msg_common
more than 2048 bytes.

2. IVC communication breaking because IVC buffer size
increased more than 2048 because of #1.

WAR: Revert back to the orin value for OSI_MACSEC_SC_INDEX_MAX

Bug 4687787

Change-Id: I5262cd772acf6b4275cc3f47696f0072b70916e0
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-06-07 13:16:02 +00:00
Mahesh Patil
b236911c75 osi: T26x CAR changes 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3126091

Bug 4228185

Change-Id: Ia9a7eede0230e25366a37dc8ce7f1a4635bd11cf
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:38 +00:00
Mahesh Patil
28b35b22c1 osi: add idle timer window interrupt support 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2963541

Bug 4246781

Change-Id: I89554a105be26958e17878b299aaadb13c39c130
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:32 +00:00
Rakesh Goyal
b3b589004f osi: ptp support for upcoming chip 
Support for PTP and TSN added

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2968052

Bug 4221043

Change-Id: I68287c3961aa194c30ca265dfe646e733fcb52cc
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
275769b28a osi: Allow more than 31 l2 filter index 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3027948

Bug 4297989

Change-Id: I0365f2136b5d7519946113fc728a58ed8fcccab4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Nagaraj Annaiah
23dc94a26a osi: Add FRP and L2 support for t264 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2992833

Bug 4334269

Change-Id: Iceade85fa54b407135ec94b4bb11cc204132efe0
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Sanath Kumar Gampa
cbdac87b2c osi: macsec: Adding support for encryption and confidentiality offset support 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2935716

Bug 4193186

Change-Id: I39669992b11e9ef032ca43f539494d48fd31ed2a
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
c604c5f2f2 osi: Macsec bring up for t264 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2904857

Bug 4122114

Change-Id: I85248181de4898293672a56199044e2deea5729a
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
0bbdb9b46a osi: Add 5-tuple L3L4 fitler match 
Add combined L3 and L4 filters support

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2964434

Bug 4246781

Change-Id: I32c5fcff7068a1c2245936fc435cb433729be6b9
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00