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Author SHA1 Message Date
Rakesh Goyal
a5c2423f63 core: enable m2m_sync for primary and secondary interfaces 
Issue: Ask is to enable Mac-to-Mac tsync
on interface for primary and secondary interface.

Fix: update default value.

Bug 200733666

Change-Id: Ie00e3cf96d0deb75d7c623a63bc0d06ed637ca2c
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2628723
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Sheetal Tigadoli <stigadoli@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
jetson_34.1.1 jetson-r34.1_dp 		2021-12-06 04:35:42 -08:00
Sanath Kumar Gampa
d190c203da osi:macsec:Fix to address sc_an_not_valid counter 
Issue: tx_sc_an_not_valid counter is increasing in
stress tests when there is AN roll over happens

Fix: Program the SCI LUT with vaid AN map and then
enable AN in sc_state LUT

Bug 3422356

Change-Id: I17021d435076ff94367a58a4c74b50124c97d68a
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2623649
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-12-02 07:39:53 -08:00
Bibhay Ranjan
97c73020e2 nveqos:fix MISRA_C-2012_Rule_8.13 and 10.4 issues 
MISRA FIXES
===== DIFF ======
Total misra violation count changed by -21
Rule: MISRA_C-2012_Rule_10.4 Diff: -1
Rule: MISRA_C-2012_Rule_8.13 Diff: -20
Rule: Total Diff: -21

CERT FIXES
===== DIFF ======
Total cert violation count changed by 0

Bug 200770325

Change-Id: Ib6cca8c2eaff5ae8cddd718b2f0c309c6888d4fc
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605632
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-17 12:47:39 -08:00
Sanath Kumar Gampa
c52ad89f9d osi:macsec:lowest pn changes to enable sa 
Enhancement to receive lowest_pn from supplicant
as part of receive AN enable

Bug 3371004

Change-Id: If81f8449f7ebda996c95117e2c84722fdc57c5d0
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2619949
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-11 20:39:08 -08:00
Mohan Thadikamalla
ee1da8d41d osi: xpcs: Remove XPCS lane bring up retry 
Issue:
When the ethernet server got enabled the boot time KPI
increased due to the XPCS lane up retry.

Fix:
Remove retry from OSI and add SET_SPEED ioctl
retry from OSD.

Bug 3414276

Change-Id: I617ab51ee6ddd50b449f78ecc9c858b1d9196b3e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2617516
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-10 00:19:36 -08:00
Rakesh Goyal
81e1442693 nvethernetrm: core: MAC to MAC tsync dynamic support 
Add code to support enable/disable M2M sync using
ioctl.

Bug 200733666

Change-Id: Ifedad7981644c816345f3e10a0b0f8289e032200
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614964
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-02 04:07:38 -07:00
Rakesh Goyal
61be2488de nvethernetrm: MAC to MAC time sync 
- Add code to store role of FD
- Function to return osi_core pointer for
  first role match.
- add code to calculate time offset between
  Primary and Secondary PTP controller HW time.
- calculate frequency adjustment calculation.
- call appropriate HAL function for
  secondary interface.

Bug 200733666

Change-Id: I7a141ea691d80d9f69fd18b28ae0964cb1bf2fb3
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614283
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-02 04:07:33 -07:00
Sanath Kumar Gampa
b8e03a8b43 osi:macsec: changes to send next PN to supplicant 
As part of MKA, supplicant requests for Next PN
used by SecY. Added changes to OSI to send to
send the Next PN for a given SCI and AN.

Bug 3371004

Change-Id: Iaf001ba5e6b5480396e2f774a42927831160a2e5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614365
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-28 01:06:06 -07:00
Bhadram Varka
15aec6d712 osi: dma: check TDES3_ES_BITS for EQOS 
Issue: TDES3_ES_BITS not valid for MGBE which results
wrong error stats in ethtool o/p

Fix: Check TDES3_ES_BITS only for EQOS.

Bug 200779501

Change-Id: Idccc8cca54b2fe6f8ac30ed99f2cc69d093acea9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2609473
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-22 02:09:16 -07:00
Mohan Thadikamalla
31058b6774 osi: core: Add MTU IOCTL support 
Issue:
When the ethernet server got enabled,
the MTU changes are not getting
communicated to the ethernet server.

Fix:
Add new OSI IOCTL and implement HAL
and IVC message for ethernet server.

Bug 3402313

Change-Id: I28bab58c2847d275324e54229ac50459d3059d26
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2610189
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-18 21:43:48 -07:00
Sanath Kumar Gampa
6108b6e8a1 nvethernetrm:Disabled DIC as part of mgbe init 
Issue:seeing 0 Throughput after MACSEC is enabled

Fix: Disable DIC to fix 0 Tput issue

Bug 200770840

Change-Id: I8cceee8fd8509ec484bfbb6063ca4dd8be091fa5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2606457
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-14 12:03:15 -07:00
Sanath Kumar Gampa
2a3bdce7c8 nvethernetrm: MTL_EST CTOV config for MACSEC 
Issue: h/w requirement to change the MTL_EST value
depending on MACSEC

Fix: Change the value in MACSEC enable/disable flow

Bug 200630202

Change-Id: Iefdb14e44841941ab3e8f8c116746b0db6c63ba5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604830
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-14 12:02:52 -07:00
Nagaraj Annaiah
5df5eefe5a osi: core & dma : Increase osi and dma instances 
- Increase OSI and DMA instances to 10 to support
  multiple VF's.
- Copy PTP config to ioctl structure.

Bug 2694285

Change-Id: I558b161c64a5467dc9e7260e58801eb6b1735d50
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605781
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-07 22:39:51 -07:00
Mahesh Patil
0b11badd9d nvethernetrm: Fix err for macro MACSEC_KEY_PROGRAM 
Fix compiler err when macro MACSEC_KEY_PROGRAM enabled
Bug 3389496

Change-Id: Ic95dd8c5b63538f3f246122ddb203a649afc6975
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2601538
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-07 17:52:02 -07:00
Rakesh Goyal
e6a2dd50b4 osi: core: Set QHLBF bit 
As per HW fix, program QHLBF to 1 to get
HLBF error in 1-2 cycle of GCL.

Bug 200778825
Bug 200649072
case: 01085007

Change-Id: I18cfa6ad4eda56e2684abd86b7dc02c7a143c0ef
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2601421
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-07 17:51:50 -07:00
Bhadram Varka
d58825f314 osi: dma: fix SMMU faults with iova address 0x0 
Issue: Transmit buffer address is pupulated in transmit
descriptor only if buffer address is less than UINT_MAX.
If the buffer address equals to UINT_MAX then descriptor
will have value of zero which is filled during transmit
completions. Because of this HW tries to fetch the address
zero which not valid and results in SMMU fault.

Fix: Fill all tdesc0 using with lower 32 bits and tdesc1
with higher 32 bits

Bug 200779695

Change-Id: I3706234d3f8c561f8291ffd63a1b1d63d046d2f2
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604615
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-06 18:17:03 -07:00
Narayan Reddy
4bfff697fe osi: core: mgbe: pass correct argument 
Issue: base pointer is passed instead of osi_core
for mgbe_l3l4_filter_read and mgbe_l3l4_filter_write
as an first argument.

Fix: Pass osi_core pointer instead of base

Bug 200764768

Change-Id: I29ec030b2cab98d49f164d1011ac0f951496aa1c
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2603073
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-06 18:16:11 -07:00
Narayan Reddy
b9be4579b7 osi: core: Enable Transparent Tx LPI Mode 
In this mode, the transmit LPI state-machine
does not move to TX_QUIET state. On detecting Lower-Power Idle
on XGMII/GMII Tx interface, xpcs goes to the TX_SLEEP state and
remains in this state till MAC stops sending LPI.

Bug 200764486

Change-Id: I376ac481e880472d7a11b60931a90d6f9c7a0067
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2598380
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-24 12:31:56 -07:00
Rakesh Goyal
972305578c core: add CMD_PTP_TSC_CAP to capture time 
issue: Requirement is to have a method by which
       TSC-PTP-CAPTURE can be initiated.

fix: Having osi_core ioctl to trigger and capture
     TSC-PTP timestamp using HW logic.
     Caller need to call osi_handle_ioctl with
     command as OSI_CMD_CAP_TSC_PTP,
     osi_core pointer and osi_core_ptp_tsc_data
     structure.

Bug 200736396

Change-Id: I511dc4f490fdef81655a62c18268764741855fe4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2554284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-22 15:39:49 -07:00
Bhadram Varka
a0c20c02f6 osi: mgbe: add handling of tx errors 
handle Tx buffer underflow
handle Tx jabber timeout
handle Tx IP header error
handle Tx Payload checksum error

Bug 200565898

Change-Id: I2de4cd11580251f0387039c1f8f3c39792c1ab65
Signed-off-by: narayanr <narayanr@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2596092
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-21 13:40:58 -07:00
Bhadram Varka
dbaf1ac0ba osi: xpcs: Fix Tx lane bring-up failure 
Issue:
During Tx lane bring up power up will fail if
the lane is already powered up.

Fix:
Don't bring-up Tx lane if its already powered up.

Bug 200766119
Bug 200764018

Change-Id: Idbdffdca7b9c9cccd8b8876fcfe8ea7448a7ed10
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2597604
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-21 07:51:42 -07:00
Rakesh Goyal
2200f3d921 core: update code for TSN 
- Update CTOV recommended value
- Update PTOV recommended value
- Disable PEC filed on preemption disable
- Disable EEST with message to reprogram
  GCL instead of dropping packet on HLBF/HLBS
- Configure code not to drop any packet silently
  on HLBF and HLBS error
- Q2TC mapping with CBS enable

Bug 200763256
Bug 200765943

Change-Id: I7a2581af488e22a23d32ce1819440c21f4748800
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2593162
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-20 11:10:24 -07:00
Rakesh Goyal
fc9e41ca31 dma: check tx_pkt_cx length field 
Validate tx_pkt_cx before updating
hardware

Bug 200765943
Bug 200763256

Change-Id: I44c4b1ec3adfed2b9f871924b3f03a3dd6e2ab2f
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2592513
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-20 11:10:13 -07:00
Rakesh Goyal
a9b03b83a9 core: mgbe: use lock for time stamping 
Using lock for protect critical section between
common interrupt and ioctl call to read
timestamp

Add mmc counters for lock failure during node
addition and deletion.

Bug 200743666

Change-Id: I12a2e57993e91d6ed50ed0efc84d1b60ef736677
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2590099
Tested-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-20 11:09:19 -07:00
Nagaraj Annaiah
801815742d osi: core: macsec: Add macsec fix 
Issue: macsec doesn't work for virtualization.

Fix:
1.Move virtualization checks before address check.
2. Copy PTP config to ioctl structure.

Bug 2694285

Change-Id: I81f47cf23e37a62a3e5b8ecece8ae905ec1a5df3
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587833
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 19:06:59 -07:00
Bhadram Varka
0372ac4f94 osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID based on MAC instance ID through HV window

Bug 200761024

Change-Id: I1a37455647429e917e7558e812fe7e512d646918
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2592482
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 09:18:17 -07:00
Mohan Thadikamalla
c21e65e2a7 osi: eqos: Fix FRP entry update fail 
Issue:
FRP entry update command is getting
failed due to an invalid RXPI check
on EQOS IP.

Fix:
Fix the RXPI check on the FRP
update as per the databook.

Bug 200766666

Change-Id: I4631623ec06bf815c88c5364f5ae599d0e7702dc
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587257
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 05:00:29 -07:00
Rakesh Goyal
6c53499842 core: eqos: handling onestep ipv4 flags 
Issue: OSI_MAC_TCR_CSC not handled in
eqos code

Fix: update time control register with
CSC bit if passed form upper layer.

Bug 200764256

Change-Id: Ifbfab0de4bb81625c4bd023fad67131ee6a43987
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2593818
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Mohan Thadikamalla <mohant@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-14 11:13:45 -07:00
Mahesh Patil
3af55e0c58 nvethernetrm: change MAC ipg as per macsec req 
Change MAC ipg value as macsec IAS requirement when
macsec is used

Bug 3335658

Change-Id: Ie681bb0a66b256c32ac6093114fe29c65bf20a07
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-10 02:10:19 -07:00
Rakesh Goyal
581b8ad758 dma: mgbe: update RWT and RWUT programming for silicon 
Issue: RWT and RWUT programmed for uFPGA

Fix: Update RWIT programming
     Update minimum rx coalescing timer value

Bug 200767374

Change-Id: I09c21764f0c294021c7546f75351c19c34a0b9db
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2589496
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-09 09:22:28 -07:00
Rakesh Goyal
2e176d13c6 core: eqos: Program OVHD value for EQOS 
As per guidelines form HW team, add
recommended OVHD for eqos

Bug 200765943

Change-Id: Ic885ed9681869fd6f13c65407d208f9e30e19e5e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2589995
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-07 16:11:15 -07:00
Mohan Thadikamalla
7d215e6dcb osi: eqos: Fix 4 to 7 RXQ to DMA mapping 
Issue:
DCS test are getting fail due to invalid
RXQ to DMA mapping.

Fix:
Enable DMA mapping for RXQ 4 to 7

Bug 200765514

Change-Id: Idece787a9aa7d9c9bac52be64f55a9ec962f092f
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587182
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-07 05:34:23 -07:00
Bhadram Varka
64241e1972 osi: eqos: Increase EQOS_MAX_*_SAFETY_REGS 
Issue: Current array size index for EQOS MTL safety
register storage 4. It created issue when interface
going down/up for Orin EQOS (MTL/DMA queues/channels - 8)
while initializing the safety register structure.

Fix: Increase EQOS_MAX_CORE/DMA_SAFETY_REGS to accommodate
Orin EQOS registers extra registers as well.

Bug 200765067

Change-Id: I79226eadfc0964d5034c685c7c31a7989afaeff7
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2585014
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-03 08:02:05 -07:00
Bitan Biswas
e1ffd204f7 scripts: upgrade to k5.10 checkpatch.pl 
Upgrade kernel/nvethernetrm checkpatch.pl to k5.10 version

Bug 200712834

Change-Id: I35477ec2cc6e6ecb829e88db95111b50f1657b67
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587203
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Ketan Patil <ketanp@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-01 09:50:44 -07:00
Narayan Reddy
b943ccf5da osi: core: xpcs: modify lane bringup sequence 
Issue: there is a PHY reset(RX_PCS_PHY_RDY) programming
in Rx sequence that was disabling the Tx path from MGBE PCS

Fix: Control entire programming sequence from SW and
by pass HW FSM

Bug 3359851
Bug 200765222

Change-Id: Iffd00d1dff00204e36eb3a14b19c07dcd3a502b8
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584394
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-28 02:47:23 -07:00
Bhadram Varka
7b29b58c95 Revert "osi: eqos: mgbe: program SID through HV window" 
This reverts commit b16c09af3b.

Reason for revert: Created regression for AV + L

Bug 3358505
Bug 200761024

Change-Id: I31fbd921f9655cd62073918be9d4151f5cc29f8b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584378
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-28 02:46:52 -07:00
Bhadram Varka
b16c09af3b osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID through HV window

Bug 3358505
Bug 200761024

Change-Id: I1db99c85e875aeaf6c692011a0d2fbe16277d288
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2582062
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-25 09:07:33 -07:00
Rakesh Goyal
b4f9f7fae8 nvethernetrm: enable common interrupt in eqos wrapper 
Enable EQOS_CORE_SBD_INTR in ETHER_QOS_COMMON_INTR_ENABLE
and clear in ETHER_QOS_COMMON_INTR_STATUS.

Bug 200760072

Change-Id: Id0e4a6d5704664faf633181d816d3708cb85956a
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2577049
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-19 14:04:07 -07:00
Narayan Reddy
36510e26ad eqos: set ssnic to 6 
Set SSIN to 6 for EQOS mac version 5.3

Bug 200760072

Change-Id: I72923d42313880dd362b7b6b197269f3495a18de
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2575178
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-16 15:26:00 -07:00
Mahesh Patil
5f8d32d75d nvethernetrm: Properly apply eqos sot delay mask 
Fix to apply SOT mask to EQOS_MACSEC_SOT_DELAY to program
SOT delay properly

Bug 200760072

Change-Id: Ib201c17434ca8ef240dae46568aaca8869f32929
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2573240
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: Ashish Mhetre <amhetre@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-16 12:09:57 -07:00
Bhadram Varka
6ceff22325 osi: eqos: Fix queue size config for Orin EQOS 
Issue:
1) MTL Tx/Rx queue configuration happens by reading
HW feature registers from the MAC.
2) For Xavier EQOS RXFIFOSIZE/TXFIFOSIZE - 9 implies
MTL queue size 36KB But for Orin EQOS value - 9
implies MTL queue size 64KB.
3) While calculating per queue fifo size 64KB not considered
which resulted in wrong configuration which is 36KB and
per queue it will be 4KB (36KB/8).
4) For TSO to work properly PBL should be limited to half the
size of programmed queue size. With above incorrect programming
with PBL - 32 queue size becoming 4KB which is exactly same
as programmed queue size. Because of this TSO is not working.

Fix:
Fix Tx/Rx queue configuration by using 64KB for Orin EQOS.

Bug 200761740

Change-Id: I4ed13961133367f4027c2dbf27be28d0990cf3f9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2575466
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Ashish Mhetre <amhetre@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-13 05:39:54 -07:00
Bhadram Varka
972f1cc398 osi: xpcs: fix XPCS wrapper register programming 
Bug 200760072

Change-Id: I704f8f9e5b46ada7bd4dd6dd09fd43d09f10e906
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2572477
Tested-by: Narayan Reddy <narayanr@nvidia.com>
Tested-by: Alex Waterman <alexw@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-11 16:25:54 -07:00
Bhadram Varka
3293a90aba osi: Add core debug for registers/structures 
- Adds core debugging for registers/structures.
- Add change to use single macro for CORE and DMA.

Bug 200737108

Change-Id: If96af2ef0c39e01b6c1dad74ee11fd820df76a8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559319
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-16 16:46:03 -07:00
Bhadram Varka
9cdfd1cefd osi: Update MGBE MAC version 
On uFPGA MGBE MAC version is 0x31 and it got updated
to 0x40 on silicon.

Bug 200751806

Change-Id: Ic9d35b7a36cff158dd17feeddce6267a3ec2a082
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559464
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-15 17:27:56 -07:00
Rakesh Goyal
993cd8cf81 nvethrnetrm: add debug prints and validation function 
issue: 1) Missing code related to GCL validation in MGBE
       2) Missing debug prints

Fix:   Fix above issues
       1) Add call for validate GCL entries for MGBE
       2) Add debug prints for all errors before return

Bug 200622871

Change-Id: I060597fec2de1cb17b80c0c14f257401d3ff8d31
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2557029
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-15 17:17:13 -07:00
Mahesh Patil
f7e004c653 nvethernetrm: adjust macsec mtu configuration 
Adjust macsec mtu setting as osi_core->mtu is not reducing
mtu for macsec SECTAG

Bug 200730979

Change-Id: I69399b5b9ebd04b5c2c8964bab5b6635f66cfef8
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558623
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-15 17:16:57 -07:00
Mahesh Patil
330acf2e3d nvethernetrm: address review comments 
- Convert primitive data type to nv_ type's
- Replace debug pr_ prints with OSI_CORE_ print macro's
- Add all macsec register macro's with prefix MACSEC_
- Update all osi function header as per 5.2 coding guidelines(PLC)
- Remove printk.h header file and use OSI_CORE_ERR macro's in all prints
- Implement clean up LUT's in add_upd_sc() and del_upd_sc()

Bug 3264523

Change-Id: Ie41097c85fbcb90ce0c4cac470fe0f068ed22247
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2548476
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-13 19:27:38 -07:00
Bhadram Varka
d4e6ad6ec6 osi: use max_chans based on MAC version 
Issue: Maximum number of DMA channels is different for
Xavier/Orin EQOS/MGBE IP's. Using macro of maximum number
of channels will create problem for other IP's.

Fix: Assign maximum number of DMA channels based on MAC version.

Bug 200741194

Change-Id: I321780b6868dfb36700863a5852b76424d3bbf6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556425
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-13 09:22:21 -07:00
Rakesh Goyal
843cc0b31b nvethernetrm: bug fix to use absolute time passed as input 
Issue: BTR register don't use fixed value from input
       argument and use only offset with current time.

Fix:   Absolute time can also be input argument.
       Fix bug so it can work with standard utility.

Bug 200622871

Change-Id: I063c29b5d1d1d546ed59f8bf1f870e4876e03858
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556217
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-07-13 09:21:45 -07:00
Bhadram Varka
0192064261 osi: dma: Add debug capabilities 
- Dumps the descriptor if enable_desc_dump flag enabled.
- Dumps registers/structure through OSI DMA IOCTL.

Bug 200737108

Change-Id: I75924cdbd815528dcddba7b9d33dbd4a162f9bbe
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2550985
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-13 09:19:11 -07:00