MISRA rule 10.1 prohibits using signed values with bitwise operators.
Make fifo invalid ID macros compliant with this MISRA rule.
Also use these macros in source code instead of hardcoded numbers to
make the code more readable.
JIRA NVGPU-1006
Change-Id: I2f336d1decbc53b08f93587f2e00ea2cce47f72b
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1983700
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Extract non-chip-specific code that manages the runlists (init, update,
reschedule etc.) to a new file in the common directory. Move the
declarations to a new matching runlist.h header.
Jira NVGPU-1309
Change-Id: I3c7e0032899516487037f47ddc9a7e7aa4b0b33a
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1978058
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Update the fifo code to use the HALs exposed by "Top" unit to
read data from device_info table.
The information for GRAPHICS engine in device_info table is
now parsed using the get_device_info HAL from "Top" unit.
Copy engine(CE) has multiple entries in the device_info table
corresponding to each instance of the engine. Prior to Pascal, each
instance of an engine was denoted by different engine type.
For example in GM20B, there are engine types like COPY_ENGINE0,
COPY_ENGINE1 and so on. In Pascal and chips beyond, a new field
called "inst_id" is added and the engine_type is kept the same for
different instances of an engine. For example in GP10B, all copy
engine entries have same engine type i.e ENGINE_LCE, but different
inst_ids. So for Pascal and chips beyond, we use a different HAL to
get CE information from device_info table.
JIRA NVGPU-1053
Change-Id: Ib40a616d903a5dbef5730678c2ebc3454b8e900d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1969400
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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gk20a_fifo_recover_tsg does high-level software calls and
invokes gk20a_fifo_recover. This function belongs to the tsg unit and
is moved to tsg.c file. Also, the function is renamed to
nvgpu_tsg_recover.
Jira NVGPU-1237
Change-Id: Id1911fb182817b0cfc47b3219065cba6c4ca507a
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970034
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gk20a_fifo_recover_ch does high-level calls and invokes
gk20a_fifo_recover. This function belongs to the channel unit and is
moved to the file channel.c. Also, the function is renamed to
nvgpu_channel_recover.
Jira NVGPU-1237
Change-Id: I31890f85fdb2c42648cc063dd9c4e7e35930dcef
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1970033
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Any tsg specific functions that does high-level software-centric
operations below to the TSG unit and not the FIFO unit.
Move the below public functions as well as their dependent
static functions to common/fifo/tsg.c and also rename them to use the
prefix nvgpu_tsg_*
gk20a_fifo_set_ctx_mmu_error_tsg
gk20a_fifo_abort_tsg
gk20a_fifo_error_tsg
gk20a_fifo_check_tsg_ctxsw_timeout
Jira NVGPU-1237
Change-Id: I4e3da821a878d4b4a0a0b53fbb7f4c10f135f58d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1934299
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Any channel specific functions having high-level software-centric
operations belong to the channel unit and not the FIFO unit.
Move the below public functions as well as their dependent
static functions to common/fifo/channel.c. Also, rename the functions
to use the prefix nvgpu_channel_*.
gk20a_fifo_set_ctx_mmu_error_ch
gk20a_fifo_error_ch
gk20a_fifo_check_ch_ctxsw_timeout
Jira NVGPU-1237
Change-Id: Id6b6d69bbed193befbfc4c30ecda1b600d846199
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1932358
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The function gk20a_fifo_sched_disable_rw accesses HW directly. Rename it
and add a HAL indirection so that it can be called from chip-independent
code.
Also fix some trivial MISRA violations in the function.
Jira NVGPU-1309
Change-Id: Icf320738d3d1d4baa40257a9da3ca2c6b7fefc0b
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1971274
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We had to force allocation of physically contiguous memory for
USERD in nvlink case, as a channel's USERD address is computed as
an offset from fifo->userd address, and nvlink bypasses SMMU.
With 4096 channels, it can become difficult to allocate 2MB of
physically contiguous sysmem for USERD on a busy system.
PBDMA does not require any sort of packing or contiguous USERD
allocation, as each channel has a direct pointer to that channel's
512B USERD region. When BAR1 is supported we only need the GPU VAs
to be contiguous, to setup the BAR1 inst block.
- Add slab allocator for USERD.
- Slabs are allocated in SYSMEM, using PAGE_SIZE for slab size.
- Contiguous channels share the same page (16 channels per slab).
- ch->userd_mem points to related nvgpu_mem descriptor
- ch->userd_offset is the offset from the beginning of the slab
- Pre-allocate GPU VAs for the whole BAR1
- Add g->ops.mm.bar1_map() method
- gk20a_mm_bar1_map() uses fixed mapping in BAR1 region
- vgpu_mm_bar1_map() passes the offset in TEGRA_VGPU_CMD_MAP_BAR1
- TEGRA_VGPU_CMD_MAP_BAR1 is called for each slab.
Bug 2422486
Bug 200474793
Change-Id: I202699fe55a454c1fc6d969e7b6196a46256d704
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959032
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preempt_channel needs to use the channel to pass it to other
public functions, get access to a tsg etc. This qualifies it to take a
pointer to a channel as an input parameter instead of a chid.
Increment the channel ref counter using the function
gk20a_channel_from_id in functions where we get the chid from the h/w
registers directly. Once the prempt_channel function call is done,
use a gk20a_channel_put on the referenced channel.
Jira NVGPU-1461
Change-Id: I6c87c8104cfcb418d468c8c590087fd4aeabf4bd
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1963200
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gk20a_fifo_recover_channel takes a reference to the channel via its
chid before passing the channel pointer to other public functions such
as gk20a_channel_abort and gk20a_fifo_error_ch. This qualifies the
gk20a_fifo_recover_channel to take a pointer to a channel instead of
only chid.
Jira NVGPU-1461
Change-Id: I338a12a05e5ccee785a202fea7848db5201a3a39
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1963199
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Split out the code to check which engines on a particular runlist are
busy from gk20a_fifo_runlist_reset_engines() and make it a HAL op.
Resetting engines is common across chips but status is read from
registers.
Jira NVGPU-1309
Change-Id: I7a63a2942a9e210481822eaf85795fc17dad0dc5
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961822
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The function gk20a_fifo_recover_tsg has to pass a valid struct tsg to
other functions from within. This qualifies it to have a pointer to
struct tsg_gk20a as an input parameter.
Tsg specific parts of the gk20a_fifo_preempt_timeout_rc are now moved
into another function gk20a_fifo_preempt_timeout_rc_tsg
that takes a tsg as an input and passes it to gk20a_fifo_recover_tsg.
The pointer to a tsg is also used to enumerate channels from within.
The function gk20a_fifo_preempt_timeout_rc now contains only channel
specific code.
Jira NVGPU-1461
Change-Id: Ice0a9921567841fb5586a7e4e010c442ca6cf172
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1961675
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gv11b_fifo_preempt_tsg needs to access the runlist_id of the tsg as
well as pass the tsg pointer to other public functions such as
gk20a_fifo_disable_tsg_sched. This qualifies the preempt_tsg to use a
pointer to a struct tsg_gk20a instead of just using the tsgid.
Jira NVGPU-1461
Change-Id: I01fbd2370b5746c2a597a0351e0301b0f7d25175
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1959068
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replace tsgid with a pointer to a struct tsg_gk20a in the function
gk20a_fifo_tsg_abort(). gk20a_fifo_tsg_abort needs to enumerate through
all the channels within the tsg as well as pass the tsg pointer to
other functions, qualifying the need to use a pointer instead as an
input parameter.
Jira NVGPU-1461
Change-Id: I59cec05d5d778f733d0c3e9ffadf46e74e249080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1956567
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MISRA rule 8.3 requires that all declarations of a function
shall use the same parameter names and type qualifiers. There
are cases where the parameter names do not match between
function prototype and declaration. This patch will fix some of
these violations by renaming the parameter as required.
JIRA NVGPU-847
Change-Id: I3f7280b0e4c21b1c2d70fd7f899cf920075f87a3
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1927103
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: I4c04e2720a3b068909cc4af6847d4718568c13ea
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1822740
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Fix some mistakes from commit 0fbc1a2652 (gpu: nvgpu: avoid recursion in
runlist construction) and commit 998bf379df (gpu: nvgpu: add
runlist_append_tsg) for MISRA rules 10.3 and 10.4.
- cast a sizeof to u32 in a calculation to match in size,
- make the NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_* constants unsigned to make
comparisons match in signedness.
Jira NVGPU-1174
Change-Id: I00aa9758ca4352d8eb53a0e8ded42a1ba3b14561
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1938069
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Reduce the size of memory allocations in the channel debug dump by
capturing only the necessary values from the instance block. This also
simplifies the allocation path slightly with the downside of having to
add a capture_channel_ram_dump HAL for reading the interesting parts
explicitly beforehand to the now smaller staging buffer.
Also rename struct ch_state to struct nvgpu_channel_dump_info.
Jira NVGPU-886
Change-Id: I5d7518d9d474b0b728b183383bc83d89ecf91b98
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928207
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MISRA rule 18.7 doesn't allow flexible array members. To work around
that, modify the instance block member in struct ch_state to be an
explicit pointer and allocate it separately for simplicity.
Jira NVGPU-886
Change-Id: I34299bec79bf7706f9cdfa42dee7fba765c9f312
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1928205
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MISRA rule 8.2 makes it mandatory for all function prototypes
to have named parameters. There were few instances where parameter
name(s) for function prototypes were omitted. This patch will
fix the same.
JIRA NVGPU-861
Change-Id: I6cb28482becc2938c574b7d8c6f22463d346d27a
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1917939
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MISRA rule 17.2 forbids recursion as a hazard on the stack space. To
comply and additionally to make the code somewhat more straightforward
to read, rewrite the runlist construction with three explicit functions
that work as the three levels of the earlier recursion. These levels map
to the three priority levels of TSGs and having more than that is
unlikely.
When "runlist interleaving" is enabled, TSGs with higher priorities get
interleaved between the switch of each pair of lower-level priority
TSGs, so that the latency for a job at priority level X is no more than
all jobs' timeslices of priority X and higher, plus at most one job at a
lower level.
This can be illustrated as follows (low, medium, high TSGs 1 and 2):
L1 L2 (only low-priority TSGs)
H1 H2 (only high-priority TSGs)
H1 H2 M1 H1 H2 M2 (no low-priority TSGs)
M1 M2 L1 M1 M2 L2 (no high-priority TSGs)
H1 H2 L1 H1 H2 L2 (no medium-priority TSGs)
H1 H2 M1 H1 H2 M2 H1 H2 L1 H1 H2 M1 H1 H2 M2 H1 H2 L2 (no empty levels)
Without interleaving, the items are simply grouped by priority.
Jira NVGPU-1174
Change-Id: Ic3b5106945df7105633730ecd1d150af770a5e83
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918226
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We right now acquire rulist_submit_mutex to submit runlist and also
to wait for submit completion
But locking is only needed to atomically configure the runlist submit
registers, hence move the locking to inside of
gk20a_fifo_runlist_hw_submit() where we program the registers
Also convert the mutex to spinlock at the same time
Note that similar locking is not required for
tu104_fifo_runlist_hw_submit() since the runlist submit registers
are per-runlist beginning Turing
Bug 200452543
Change-Id: I53d6179b80cb066466b64c6efa9393e55e381bfc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1919058
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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We right now submit new runlist and wait for submit to complete in
gk20a_fifo_update_runlist_locked()
It is possible that multiple runlists are being updated in parallel
by multiple threads since the lock taken by parent of
gk20a_fifo_update_runlist_locked() is per-runlist
Note that the concurrent threads would still construct their runlists
into per-runlist buffer
But we still have a race condition while submitting these runlists
to hardware.
With an application that creates and destroys multiple contexts in
parallel this race condition gets realized and we see h/w reporting
an error interrupt NV_PFIFO_INTR_SCHED_ERROR_CODE_BAD_TSG which means
a bad TSG was submitted
Fix this by adding a global lock for runlist submit and wait sequence
This ensures that concurrent threads do not try to submit runlists
to the hardware at the same time
Bug 200452543
Bug 2405416
Change-Id: I2660a2e5d9af1da400e7f865361722dc0914f96f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1851114
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Fix MISRA rule 10.1 violations involving gk20a_nonstall_ops
enums by replacing them with with corresponding #defines.
Because these values can be used in expressions that require
unsigned values (e.g. bitwise OR) we cannot use enums.
The g->ce2.isr_nonstall() function was previously returning an
int that was a combination of gk20a_nonstall_ops enum bits which
led to the violations.
JIRA NVGPU-650
Change-Id: I6210aacec8829b3c8d339c5fe3db2f3069c67406
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796242
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This reverts commit 0b02c8589d.
Originally change was reverted as it was making ap_compute test on
embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg
preempt with runlist preempt during teardown, preempt timeout set to
100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy
chips) and not issuing preempt timeout recovery if preempt fails, helped
resolve the issue.
Bug 200426402
Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762563
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-Add support for aborting runlist/s. Aborting runlist/s,
will abort all active tsgs and associated active channels
within these active tsgs
-Bare channels are no longer supported. Remove recovery
support for bare channels. In case there are bare
channels, recovery will trigger runlist abort
Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596
Change-Id: I6bec8a0004508cf65ea128bf641a26bf4c2f236d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1640567
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-is_preempt_pending hal does not need timeout_rc_type input param as
for volta, reset_eng_bitmask is saved if preempt times out. For
legacy chips, recovery triggers mmu fault and mmu fault handler
takes care of resetting engines.
-For volta, no special input param needed to differentiate between
preempt polling during normal scenario and preempt polling during
recovery. Recovery path uses preempt_ch_tsg hal to issue preempt.
This hal does not issue recovery if preempt times out.
Bug 2125776
Bug 2108544
Bug 2105322
Bug 2092051
Bug 2048824
Bug 2043838
Bug 2039587
Bug 2028993
Bug 2029245
Bug 2065990
Bug 1945121
Bug 200401707
Bug 200393631
Bug 200327596
Change-Id: Ie76a18ae0be880cfbeee615859a08179fb974fa8
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709799
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Add gk20a_fifo_profile_snapshot() to store the submit time in a
profiling entry that was acquired from gk20a_fifo_profile_acquire().
Also get rid of ifdef CONFIG_DEBUG_FS by stubbing the acquire and free
functions when debugfs is not enabled. This reduces some cyclomatic
complexity in the submit path.
Jira NVGPU-708
Change-Id: I39829a6475cfe3aa582620219e420bde62228e52
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729545
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Code related to MC module is updated for handling
MISRA violations
Rule 10.1: Operands shalln't be an inappropriate
essential type.
Rule 10.3: Value of expression shalln't be assigned
to an object with a narrow essential type.
Rule 10.4: Both operands in an operator shall have
the same essential type.
Rule 14.4: Controlling if statement shall have
essentially Boolean type.
Rule 15.6: Enclose if() sequences with braces.
JIRA NVGPU-646
JIRA NVGPU-659
JIRA NVGPU-671
Change-Id: Ia7ada40068eab5c164b8bad99bf8103b37a2fbc9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1720926
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Add NVGPU_IOCTL_CHANNEL_RESCHEDULE_RUNLIST ioctl to reschedule runlist,
and optionally check host and FECS status to preempt pending load of
context not belonging to the calling channel on GR engine during context
switch.
This should be called immediately after a submit to decrease worst case
submit to start latency for high interleave channel.
There is less than 0.002% chance that the ioctl blocks up to couple
miliseconds due to race condition of FECS status changing while being read.
For GV11B it will always preempt pending load of unwanted context since
there is no chance that ioctl blocks due to race condition.
Also fix bug with host reschedule for multiple runlists which needs to
write both runlist registers.
Bug 1987640
Bug 1924808
Change-Id: I0b7e2f91bd18b0b20928e5a3311b9426b1bf1848
Signed-off-by: David Li <davli@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1549050
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Release runlist_lock and then initiate recovery if preempt
timed out. Also do not issue preempt if ch, tsg or runlist
id is invalid. tsgid could be invalid for below call trace
gk20a_prepare_poweroff->gk20a_channel_suspend->
*_fifo_preempt_channel->*_fifo_preempt_tsg
Bug 2065990
Bug 2043838
Change-Id: Ia1e3c134f06743e1258254a4a6f7256831706185
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662656
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add below new HALs
gops.fifo.add_sema_cmd() to insert HOST semaphore acquire/release methods
gops.fifo.get_sema_wait_cmd_size() to get size of acquire command buffer
gops.fifo.get_sema_incr_cmd_size() to get size of release command buffer
Separate out new API gk20a_fifo_add_sema_cmd() to implement semaphore acquire/
release sequence and set it to gops.fifo.add_sema_cmd()
Add gk20a_fifo_get_sema_wait_cmd_size() and gk20a_fifo_get_sema_incr_cmd_size()
to return respective command buffer sizes
Jira NVGPUT-16
Change-Id: Ia81a50921a6a56ebc237f2f90b137268aaa2d749
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704490
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add below rc_types to be passed to gk20a_fifo_recover
MMU_FAULT
PBDMA_FAULT
GR_FAULT
PREEMPT_TIMEOUT
CTXSW_TIMEOUT
RUNLIST_UPDATE_TIMEOUT
FORCE_RESET
SCHED_ERR
This is nice to have to know what triggered recovery.
Bug 2065990
Change-Id: I202268c5f237be2180b438e8ba027fce684967b6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1662619
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add below two new HALs
gops.fifo.runlist_hw_submit() to submit a new runlist to hardware
gops.fifo.runlist_wait_pending() to wait until runlist write is successful
Set existing API gk20a_fifo_runlist_wait_pending() to
gops.fifo.runlist_wait_pending HAL
Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w
and set it to gops.fifo.runlist_hw_submit HAL
Jira NVGPUT-20
Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700548
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
