Commit Graph

2613 Commits

Author SHA1 Message Date
Nitin Kumbhar
bf03ffbb05 gpu: nvgpu: obj_ctx: fix CERT-C INT violations
Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:310:
cert_violation: Casting "size" from "unsigned long" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/obj_ctx.c:594:
cert_violation: Unsigned integer operation
 "(*g->ops.gr.init.get_patch_slots)(g, config) * 2U" may wrap.

JIRA NVGPU-3410

Change-Id: Icae8246903693d7f5ad66635d3e81d22f6ff2df5
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118522
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-05-20 04:36:49 -07:00
Nitin Kumbhar
7c5316c142 gpu: nvgpu: ctx: fix CERT-C INT violations
Error: CERT INT30-C:
drivers/gpu/nvgpu/common/gr/ctx.c:644:
cert_violation: Unsigned integer operation
 "gr_ctx->patch_ctx.mem.size / 4UL - 2UL" may wrap.

Error: CERT INT31-C:
drivers/gpu/nvgpu/common/gr/ctx.c:580:
cert_violation: Casting "gr_ctx->boosted_ctx" from "bool" to "unsigned int"
 without checking its value may result in lost or misinterpreted data.

JIRA NVGPU-3409

Change-Id: Ib3c865d43ecd3c0eaaafd47b7b65111aa77689bd
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118521
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2019-05-20 04:36:40 -07:00
Thomas Fleury
3881dd6a26 gpu: nvgpu: fix build issue w/ NVGPU_CHANNEL_WDT
Fix build issue w/ safety build.
Add missing } when NVGPU_CHANNEL_WDT is not set.

Jira NVGPU-3012

Change-Id: I60f017a0203662b9acc8a2fa791079deade93736
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121305
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2019-05-18 03:54:52 -07:00
Philip Elcan
aeb8852d54 gpu: nvgpu: fix MISRA 9.1 issues in page_table
MISRA Rule 9.1 requires objects to be initialized before being read.
Update nvgpu_set_pte() to initialize values before they are passed to
nvgpu_locate_pte().

JIRA NVGPU-3340

Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Change-Id: I3d6b3d3eb3d8cb657c46c80c8d03ecf1c0b4f12c
Reviewed-on: https://git-master.nvidia.com/r/2120491
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-17 16:16:54 -07:00
Philip Elcan
f8f9dfeea8 gpu: nvgpu: mm: fix MISRA 13.5 violations in page_table
Fix MISRA rule 13.5 violation for using a function that has side effects
as the right hand side of a logical expression. In this case,
is_iommuable() can have side effects in some OS implementations.

JIRA NVGPU-3340

Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Change-Id: If465f68fce0e9d6d8ef98564229eebd112b28f29
Reviewed-on: https://git-master.nvidia.com/r/2120490
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-17 16:16:45 -07:00
Philip Elcan
40d9609eff gpu: nvgpu: mm: fix 4.7 violation in page_table
MISRA 4.7 requires checking errors returned by functions. This fixes a
case where the error information wasn't being checked before performing
other operations.

JIRA NVGPU-3340

Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Change-Id: I480fde75a07f779450096533ab29c76975aff092
Reviewed-on: https://git-master.nvidia.com/r/2120489
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-17 16:16:36 -07:00
Philip Elcan
dfccdeaace gpu: nvgpu: mm: fix MISRA 16.4 in dma.c
MISRA Rule 16.4 requires a comment or statement in the default lable.
This moves a comment in nvgpu_dma_free(0 before the break to be
compliant.

JIRA NVGPU-3328

Change-Id: Ic4293f486c35eb6396a508508d43d53311fc693c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119647
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-17 15:05:30 -07:00
Vaibhav Kachore
11630ad56f gpu: nvgpu: add support for TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS
This patch adds support for TEGRA_VGPU_CMD_GET_TPC_EXCEPTION_EN_STATUS
in vgpu.

Bug 2555113

Change-Id: I9c822e09e1b4ec84ccaa3110b6f500b26eec6490
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118328
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2019-05-17 06:36:33 -07:00
Antoine Chauveau
b8ba882399 gpu: nvgpu: Remove assertion which triggers intermittently
Partially revert patch c0e725a, which causes intermittent test
failures.

Bug 2599340

Change-Id: I4ac7ef007b4a7beaa2010cc3795ed0f78b4ce9c7
Signed-off-by: Antoine Chauveau <achauveau@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120867
2019-05-17 04:52:47 -07:00
Debarshi Dutta
4c30bd599f gpu: nvgpu: rename tsg_gk20a*/gk20a_tsg* functions.
rename the functions with the prefixes tsg_gk20a*/gk20a_tsg*
to nvgpu_tsg_*

Jira NVGPU-3248

Change-Id: I9f5f601040d994cd7798fe76813cc86c8df126dc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120165
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2019-05-17 01:49:27 -07:00
Debarshi Dutta
1dea88c6c7 gpu: nvgpu: Add NVGPU_CHANNEL_WDT flag
NVGPU_CHANNEL_WDT feature is embedded within the NVGPU_CHANNEL_WDT flag
to allow it to be compiled out for safety builds.

Jira NVGPU-3012

Change-Id: I0ca54af9d7b1b8e01f4090442341eaaadca8e339
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114480
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2019-05-16 23:28:13 -07:00
Seshendra Gadagottu
b2980b0c22 gpu: nvgpu: fix MISRA 10.3 issues in hal.ltc
Change following ltc hal prototype from:
int (*determine_L2_size_bytes)(struct gk20a *gk20a);
to
u64 (*determine_L2_size_bytes)(struct gk20a *gk20a);

JIRA NVGPU-3422

Change-Id: I53cbd7f37cad3c6851e3c5b46af6cdc04013d690
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119996
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2019-05-16 16:26:22 -07:00
Seema Khowala
6f5cd4027c gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below functions
gk20a_enable_channel_tsg
gk20a_disable_channel_tsg

Rename
gk20a_disable_channel_tsg -> nvgpu_channel_disable_tsg
gk20a_enable_channel_tsg -> nvgpu_channel_enable_tsg

JIRA NVGPU-3388

Change-Id: I0c18c4a14a872cecb12ae3089da886be9da43914
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115211
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2019-05-16 16:25:22 -07:00
Thomas Fleury
af2ccb811d gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl
Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
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2019-05-16 15:15:18 -07:00
Philip Elcan
5c09935297 gpu: nvgpu: common: fix MISRA violations
Fix 8.2 violation for not specifying parameter name in prototype of
secure_alloc().

Fix 21.3 & 21.8 violations for using reserved names "free" and "exit."

Fix 8.6 and 21.2 violations for __gk20a_do_idle() and
__gk20a_do_unidle() by renaming the functions and wrapping them in a
missing #ifdef CONFIG_PM.

Fix 5.7 violation for reusing "class" as parameter name when already
defined as a struct.

JIRA NVGPU-3343

Change-Id: I976e95a32868fa0a657f4baf0845a32bd7aceb9e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117913
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2019-05-16 11:57:56 -07:00
Philip Elcan
78c7e601f8 gpu: nvgpu: debug: fix MISRA 5.7 violation
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.

JIRA NVGPU-3346

Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
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2019-05-16 11:57:32 -07:00
Philip Elcan
10006b723a gpu: nvgpu: mm: fix MISRA 21.6 violations in vm.c
MISRA 21.6 prohibits use of snprintf(). Replace uses with strcpy/strcat.

JIRA NVGPU-3332

Change-Id: I795b673d0a855c0fcb28fac76b31ef1b1f39543e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119633
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2019-05-16 09:46:01 -07:00
Seeta Rama Raju
671cc9d785 gpu: nvgpu: MISRA 10.x fix
-- This will MISRA 10.x violations in semaphore_pool.c,
   nvgpu_mem.h, nvgpu_mem.c and posix-nvgpu_mem.c.

JIRA NVGPU-3177

Change-Id: I1db234a47c7097da28fdfd3236d9b7c5fe385d79
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119524
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2019-05-16 04:29:50 -07:00
Philip Elcan
5a0a711464 gpu: nvgpu: fix MISRA 21.2 violation in io.h
MISRA Rule 21.2 prohibits naming functions beginning with double
underscore. So, rename __nvgpu_readl() to nvgpu_readl_impl().

JIRA NVGPU-3361

Change-Id: Ia09a0f57e250fa3934f843671a529ee1b2ac2493
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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2019-05-15 22:29:21 -07:00
Seema Khowala
fb603ef467 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert
nvgpu_channel_deferred_reset_engines

JIRA NVGPU-3388

Change-Id: I745de9fb618803824ae62ed586944ce5d838c92a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115787
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-15 16:47:24 -07:00
Seema Khowala
334f855ac4 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add void to ignore
the return value
update_gp_get

Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count

JIRA NVGPU-3388

Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-15 16:47:14 -07:00
Seema Khowala
766dfb2cb1 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_runlist_reload_ids

JIRA NVGPU-3388

Change-Id: Ie2bf6c48d4f9e673695dc6587df24651e9d8c78c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115767
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-15 16:47:05 -07:00
Seema Khowala
c0e725a576 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_preempt_channel

JIRA NVGPU-3388

Change-Id: Id60d10c0d1593a6b798a037b9ec0efe6c4d20dd5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115762
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-15 16:46:56 -07:00
Seema Khowala
7ebb9d85d9 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below functions and print error messages
g->ops.tsg.force_reset
nvgpu_channel_wdt_stop

JIRA NVGPU-3388

Change-Id: Ia02b0fe040d2181a2b2dc24ec56e443f59505e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-15 16:46:46 -07:00
Seema Khowala
c986b60c6f gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value and nvgpu_assert for
g->ops.mm.cache.fb_flush(g)

JIRA NVGPU-3388

Change-Id: I24ccc4ae57a2827423db4eb96726a0fe5a7f04df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2019-05-15 16:46:36 -07:00
Seema Khowala
c2b3da8e47 gpu: nvgpu: channel MISRA fix for Rule 17.7
Change gk20a_free_priv_cmdbuf from int to void type

Rename
gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry
channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q
free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry

JIRA NVGPU-3388
JIRA NVGPU-3248

Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 16:46:27 -07:00
Philip Elcan
13b94dd3fe gpu: nvgpu: xve: fix MISRA violations
Fix several 17.7 violations where the return values were ignored.

Fix 8.6 violation by removing unused declaration of
gp106_init_xve_ops().

Fix a 21.2 violation by renaming function __do_xve_set_speed_gp106().

JIRA NVGPU-3308

Change-Id: I480950aa42478329df33fd8c9c8c63a10dc11434
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116841
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-05-15 15:57:01 -07:00
Philip Elcan
bb1ca4fef5 gpu: nvgpu: mm: fix MISRA 17.2 violation in nvgpu_allocator
MISRA Rule 17.2 prohibits indirect recursion. nvgpu_allocator_initi()
was calling nvgpu_page_allocator_init(), which in turn was calling back
to nvgpu_allocator_init() to init a buddy allocator.  Rather than
calling back to nvgpu_allocator_init(), have nvgpu_page_allocator_init()
call nvgpu_buddy_allocator_init() directly.

JIRA NVGPU-3332

Change-Id: I1102450ae26dda355d5f5dcc3ddb195871c26c32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114028
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2019-05-15 09:56:17 -07:00
Philip Elcan
bceac52f0b gpu: nvgpu: mm: fix MISRA 4.7 violations in vm.c
This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.

JIRA NVGPU-3332

Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 09:56:08 -07:00
Philip Elcan
43c6e208fd gpu: nvgpu: mm: fix MISRA violations in vm.c
Fix Rule 4.7 violation for failing to check return value.

Fix Rule 14.2 violation when using the nvgpu_list_for_each_entry_safe
macro by refactoring to use a while loop.

Fix Rule 13.5 violation for using a nvgpu_timeout_expired_msg() in a
logical expression because it can have side effects. This was fixed by
refactoring the while loop.

JIRA NVGPU-3332

Change-Id: I1454db82f766a06d3ffd549de43aad6e1b632928
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-15 09:55:59 -07:00
Thomas Fleury
93bfdd3207 gpu: nvgpu: remove unused ch->gpfifo.wrap
ch->gpfifo.wrap was set when updating ch->gpfifo.get,
but never used afterwards. Removed.

Jira NVGPU-3388

Change-Id: I198e9ba0c3716a200a8937c2488cf35e04c0166f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 18:40:21 -07:00
Vinod G
c8899a3f24 gpu: nvgpu: Fix CERT INT32-C C error in common.gr
Fix cert c violations in common.gr

CERT INT31-C: unsigned long to unsigned int without checking, it value
may result in lose or misintepreted data.
Casting the U64 data type define to U32 is causing certc violation.
To avoid this error, add define BITS_PER_BYTE_U32 as a U32 data type.

CERT EXP34-C: dereferencing null pointer "g".

Jira NVGPU-3411

Change-Id: I9eaf76bde967ee075244723c51239a7c85d09e96
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118146
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 17:47:59 -07:00
Thomas Fleury
b1dff583c8 gpu: nvgpu: fix MISRA 10.4 violation in nvgpu.common.mm.vm_area
Below MISRA 10.4 violation is reported in nvgpu.common.mm.vm_area

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/vm_area.c:234:
misra_violation: The condition clause expression of the for loop has
persistent side-effects.

Fix this by replacing with a while loop.

Jira NVGPU-3330

Change-Id: Ica6882d6c73dc0d74159f34279d8f91b7494c65c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117059
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 17:47:41 -07:00
Thomas Fleury
1fd2e43a3f gpu: nvgpu: fix MISRA 21.6 violation in nvgpu.common.mm.as
Below MISRA 21.6 violation is reported in nvgpu.common.mm.as

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:79:
misra_violation: Using function "snprintf".

Fix this by replacing snprintf with strncpy.
Add nvgpu_strnadd_u32 function to convert u32 to string
The function supports radix from 2 to 16.

Jira NVGPU-3333

Change-Id: Idee739dfdedeabb74d0d9f7d4cddd798445f0ee1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117019
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 10:50:12 -07:00
Mahantesh Kumbar
25364895fd gpu: nvgpu: PMU RTOS fw init update
Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.

Allocation happens at pmu early init stage & will deinit at
remove_support stage.

JIRA NVGPU-1972

Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 04:56:34 -07:00
Mahantesh Kumbar
118381411a gpu: nvgpu: replace gk20a_from_pmu() with pmu->g
removed gk20a_from_pmu() & used pmu->g to remove
circular dependency within PMU units.

JIRA NVGPU-1972

Change-Id: I5fd1eae30a81cea5a50dd04c1fdfdb7fd4d0e1b8
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111071
GVS: Gerrit_Virtual_Submit
Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 04:56:18 -07:00
Sagar Kamble
6c22dc7ea4 gpu: nvgpu: use make flag NV_BUILD_CONFIGURATION_IS_SAFETY
Update the shared config file to use the safety build flag NV_BUILD_
CONFIGURATION_IS_SAFETY instead of NVGPU_REDUCED. With these changes
posix userspace and tests will be built in two configs based on this
flag.

JIRA NVGPU-3062

Change-Id: Iaf34dd1a8f66f2dd3f351365c369ed46a484a257
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-14 01:18:38 -07:00
Thomas Fleury
c7b6a7d235 gpu: nvgpu: fix MISRA 10.4 violation in nvgpu.common.mm.nvgpu_sgt
Below MISRA 10.4 violation is reported in nvgpu.common.mm.nvgpu_sgt

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/nvgpu_sgt.c:131:
misra_violation: Essential type of the left hand operand
"mem->mem_flags & 8ULL" (unsigned) is not the same as that of the
right operand "0ULL"(signed).

Fix this by changing right hand operand to 0U.

Jira NVGPU-3334

Change-Id: Ib28bfce363a807ba9f8fa9df9cbb02c636a74898
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117034
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 23:08:49 -07:00
Shih-hsin Li
6f9ef25c12 gpu: nvgpu: fix synchronization in nvgpu_vm_map
The mapping early returned from nvgpu_vm_map might already
be unmapped during channel clean up. Increase refcount of
an already mapped buffer inside the scope of update_gmmu_lock
mutex to avoid this race.

Bug 200494150

Change-Id: I66d9272e42c40cd3aae7ba3bb8106ec37691bf8e
Signed-off-by: Shih-hsin Li <seasonl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114163
(cherry picked from commit af95d14bb0)
Reviewed-on: https://git-master.nvidia.com/r/2116749
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 21:56:07 -07:00
Thomas Fleury
310471bf77 gpu: nvgpu: fix MISRA 17.7 violation in nvgpu.common.mm.mm
Below MISRA 17.7 violation is reported in nvgpu.common.mm.mm

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:645:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.bus.bar1_bind" is unused.

Fix this by checking return value and returning an error in
case of failure.

Jira NVGPU-3331

Change-Id: Iab43d630163af782d3cc87989a64062516a4cd92
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:12:19 -07:00
Thomas Fleury
4cd0e88065 gpu: nvgpu: fix MISRA 10.1 violation in nvgpu.common.mm.mm
Below MISRA 10.1 violation is reported in nvgpu.common.mm.mm

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/mm.c:378:
misra_violation: The expression "g->mm.vidmem.size" of non-boolean
essential type is being interpreted as a boolean value for the
operator "&&".

Fix this by explicitly checking g->mm.vidmem.size > 0U.

Jira NVGPU-3331

Change-Id: I1bb54736593801c7cb684973f411459dae6f008d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116705
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:12:09 -07:00
Thomas Fleury
89155d0ed1 gpu: nvgpu: fix MISRA 21.2 violation in rbtree
Below MISRA 21.2 violation is reported in nvgpu.common.rbtree

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/rbtree.c:188:
misra_violation: _delete_fixup shall not be declared.

Fix this by renaming to delete_fixup.

Jira NVGPU-3305

Change-Id: I09d8da721cc87d3bb9e4a23d00a31a82a8759365
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116681
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:11:59 -07:00
Thomas Fleury
d38723d618 gpu: nvgpu: fix MISRA 15.7 violation in rbtree
Below MISRA 15.7 violation is reported in nvgpu.common.rbtree

${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/rbtree.c:200:
misra_violation: No non-empty terminating "else" statement.

Fix this by re-factoring for loop.
Also re-arranged code to avoid lines over 80 chars.

Jira NVGPU-3305

Change-Id: If7586f1ac9bc411751c92b94969123788a273cf8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116680
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:11:49 -07:00
Seema Khowala
8d34edfee0 gpu: nvgpu: channel MISRA fix for Rule 17.7
Check return value of below function and add err message
ch_data->unbind_single_channel

JIRA NVGPU-3388

Change-Id: Iac979c464600507b3fcfa907d9babc8bdc232338
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115832
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-13 14:10:27 -07:00
Vinod G
5c60645cfa gpu: nvgpu: gr_priv header include cleanup
Add more apis in gr_utils for accessing variables within gr struct.
This helps to avoid including gr_priv.h outside gr files and
derefencing gr struct.

Jira NVGPU-3218

Change-Id: I6f24cc302f10aa1da14a981d80c400a027c9a115
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115930
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 20:15:36 -07:00
Philip Elcan
e332b6023c gpu: nvgpu: vbios: fix MISRA 11.3 violations
MISRA Rule 11.3 prohibits casting between pointer types. This patch
eliminates the 11.3 violations by doing the pointer arithmetic before
the cast.

JIRA NVGPU-3317

Change-Id: I624301041f3b91ddc71b30ba19f04ab492f40794
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114880
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 16:46:20 -07:00
Philip Elcan
4d104a432c gpu: nvgpu: vbios: fix MISRA 5.7 violations
MISRA 5.7 requires that all tag names be unique. Rename local variables
in functions where the local variable was named the same as the struct
type.

JIRA NVGPU-3317

Change-Id: I6604e386ac043ff33369a3ab676a6f59bfcc30c4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114879
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 16:46:11 -07:00
Philip Elcan
173f23754d gpu:nvgpu: vbios: fix MISRA 21.2 violations
MISRA Rule 21.2 prohibits naming identifiers beginning with double
underscore. Rename __nvgpu_bios_readdbyte to nvgpu_bios_readbyte_impl to
comply.

JIRA NVGPU-3317

Change-Id: Ic5eaf0a629db8669c52cc6c8a2218499ceb0d8e4
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114878
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 16:46:01 -07:00
Seema Khowala
defc27ac9b gpu: nvgpu: cg fix MISRA violations
Fix Rule 10.1

Rename gk20a_readl and gk20a_writel
Moved ELCG_* and BLCG_* defines from gk20a.h to cg.h
Cleaned up checkpatch errors

JIRA NVGPU-3424

Change-Id: I8d7de11dd7beb22c0fe44ff770af3b2609434385
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115908
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-10 11:42:52 -07:00
Seshendra Gadagottu
9651138633 gpu: nvgpu: Fix MISRA 5.5 error in common netlist
Avoid use of local variable "max" by renaming it to "max_netlist_num"

JIRA NVGPU-3420

Change-Id: Ie0a49aa6c24617d22efe401ae883d0a9c8b1dff0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116066
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
2019-05-10 10:54:04 -07:00