Commit Graph

7732 Commits

Author SHA1 Message Date
vinodg
4aff9bcd4e gpu: nvgpu: fix for load imbalance across cta subpartitions
CTA_SUBPARTITION_SKEW load balancing is broken across
subpartitions. SW WAR to disable the CTA_SUBPARTITION_SKEW.

Jira NVGPU-5132
Bug 200593339

Signed-off-by: vinodg <vinodg@nvidia.com>
Change-Id: I3faae882a94fc6262cc287df44994cc04b4fd5d6
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308905
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
3d5162f01c gpu: nvgpu: enable fe auto go idle for nvgpu-next
Enable fe auto go idle feature for nvgpu-next.

JIRA NVGPU-5135

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: I5afecea8e039be90424e1bee6e1fd20a2584576b
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2309662
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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2020-12-15 14:13:28 -06:00
Sagar Kamble
ea09ef92b5 gpu: nvgpu: conditional compilation of nvhost code
There were few more nvhost related references unprotected by the config
flag. Fix those.

Bug 2834141

Change-Id: Id7d94e3e6fa471f02697d121b557884c7287c26e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306437
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2020-12-15 14:13:28 -06:00
rmylavarapu
147564cbd5 gpu: nvgpu: NVGPU migration to support latest ucode
Changes:
- Send down BOARDOBJGRP classId to the PMU. Assign each
  BOARDOBJ the classId of its parent group which is set
  to zero in current implementation. Changed in NVGPU to send
  board obj grp classid to PMU.
- Disable IPC VMIN support as pmu-tu10a profile doesn't support.
- Change in clk vf point enumeration types.
- Change in pstate type values.
- Updated ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info
  NVGPU-PMU interface struct with b_ver_expected_is_mask to send
  whether the expected version is single value or should be
  interpreted as a bit mask with bits corresponding to
  expected versions set.

NVBUG-200593676
NVGPU-5066

Change-Id: I17b172d88f8b74fbf78044caf7f64cd8811f9fb7
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308533
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2020-12-15 14:13:28 -06:00
Sagar Kamble
4b97628278 gpu: nvgpu: conditional compile of ltc_streamid
ltc_streamid and tegra-swgroup.h header inclusion is applicable to
gp10b. Hence compile it under the flag CONFIG_ARCH_TEGRA_18x_SOC.

Bug 2834141

Change-Id: I79b8f5e0a4cfeff9298eca5f13a7d1c6f291f7ad
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307298
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2020-12-15 14:13:28 -06:00
Seema Khowala
c79522d452 gpu: nvgpu: gr: enhance firmware method error message
Dump set_falcon method, class and whitelist register
being accessed.

Bug 200594051

Change-Id: Ic7fe014ba917a23b1ca9474bf5bd1d231f7ed60f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2308857
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2020-12-15 14:13:28 -06:00
rmylavarapu
dc32307c13 gpu: nvgpu: Rename therm public struct
Renamed therm public struct to match with the other
units.

NVGPU-4449

Change-Id: I675ce43b136139420b8cc1eecdc395d9165d9f30
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307090
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2020-12-15 14:13:28 -06:00
Sagar Kamble
d0850123a8 gpu: nvgpu: remove tegra_edp_notify_gpu_load usage
Since this is just a nop stub, remove it's usage to reduce the
downstream debt.

Bug 200593710
Bug 2834141

Change-Id: I13e16462d9555bb9ebae01de65c43f59e007785d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307299
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2020-12-15 14:13:28 -06:00
Sagar Kamble
40d3f7518b gpu: nvgpu: create of_chosen variable
nvgpu relies on this OF device_node variable to determine joint_xpu_rail
property. Instead of exporting it from the OF driver as nvgpu is not
available in the upstream, define it in the nvgpu itself.

Bug 200593710
Bug 2834141

Change-Id: I80b928b20869b93f5255b757bcc1758245ee2650
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307297
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2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
6859c9c5a6 gpu: nvgpu: Add nvgpu macro for a pthread API
Add nvgpu macro for pthread API pthread_cleanup_pop(0). The argument
zero would mean that the thread cancellation cleanup handler which is
pushed onto the thread's stack using pthread_cleanup_push() will not
get executed.

JIRA NVGPU-5110

Change-Id: I89a45ccccd8709685f487513bf99d622a82ed891
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2307977
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2020-12-15 14:13:28 -06:00
Sagar Kamble
fa9db74ba6 gpu: nvgpu: conditional compilation of vpr code
There were few more vpr related references unprotected by the config
flag. Fix those.

Bug 2834141

Change-Id: Ic934b7aeb303193c21b73921982a5df9c021ea9b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306438
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2020-12-15 14:13:28 -06:00
Sagar Kamble
7b301c5ace gpu: nvgpu: cond. compile with CONFIG_TEGRA_BWMGR
Protect tegra bwmgr code under the config flag CONFIG_TEGRA_BWMGR.

Bug 2834141

Change-Id: Icb3c9a363a639e3fd8e91ef12dcb62ba7e498747
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
9aa669797d gpu: nvgpu: add pbdma gops for nvgpu_next
Add pbdma gops for nvgpu-next.

Jira NVGPU-4979

Change-Id: If04f5c09cd4a13b0f536a15dbe2b4bd9eb24107a
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302772
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2e4fb38870 gpu: nvgpu: add eng_config hal for nvgpu_next
Add gr.eng_config hal for nvgpu_next.

Jira NVGPU-5049

Change-Id: Ieb342cb0416f965a3f80e3a6e3f0f43a853485ff
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300534
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
5fa0d7f994 gpu: nvgpu: add bundle programming for nvgpu_next
Update bundle programming for nvgpu_next.

JIRA NVGPU-5004

Change-Id: I1c452a9e78cd018de86fb57de10291c4411e7d89
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
feebc746ca gpu: nvgpu: fix global register access list
For legacy chips (gm20b, gp10b and gv11b), incorrect register
offset is used for global access register list:

incorrect: 0x418300, /* gr_pri_gpcs_rasterarb_line_class  */
correct:   0x418380, /* gr_pri_gpcs_rasterarb_line_class  */

Fix this issue by updating global access register list by using
correct register offset value.

NVGPU-5108

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id6722039f8d874dbcb79732dffd727d2ff2a1a72
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306642
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2020-12-15 14:13:28 -06:00
rmylavarapu
e424e4791a gpu: nvgpu: perf: Refactor Perf unit
-Renamed and moved nvgpu_pmu_perf struct from public
to unit specific
-Renamed all functions as per public/private format

NVGPU-5029

Change-Id: If3f479bb1443850a5c8a8714cd1c9da346cb566a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300609
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2020-12-15 14:13:28 -06:00
Vedashree Vidwans
14f268563a gpu: nvgpu: add gr.zbc hal for nvgpu_next
Add gr.zbc hal for nvgpu_next

Jira NVGPU-5084

Change-Id: I678dac83ea67818e1b657b22840f3f4a04584ba8
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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2020-12-15 14:13:28 -06:00
Seeta Rama Raju
551b3bebe8 gpu: nvgpu: Add 0x if falcon data is 0000000
- When the falcon data is 00000000, the dump does not add 0x while printing.

Bug 200586923

Change-Id: I9fda75258290a85b0e4c38f426adc4474d88cdd8
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306485
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2020-12-15 14:13:28 -06:00
Prateek sethi
451797a6d5 gpu: nvgpu: move userspace firmware files to gv11b
qnx unit test access ucode from /proc/boot/gv11b. QNX Unit test face
issues like permission, platform dependency etc when test tries to
access ucode from /proc/boot. To fix issue updating qnx firmware unit
to read ucode from firmware/gv11b in case of unit test. Patch also
updates firmware access path for posix as well.

Jira NVGPU-3582
Bug 2693908

Change-Id: I1b28c8475b6bc4fe5ec3d6a525cb3af152feb887
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306278
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
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2020-12-15 14:13:28 -06:00
Deepak Nibade
7a4ecc8966 gpu: nvgpu: make debugger register access ELPG protected
Some of the APIs that access debugger register are not protected
from ELPG. This might trigger PRI access timeouts for corresponding
registers if GR engine is power gated.

Add nvgpu_pg_elpg_protected_call() to protect against ELPG.

Bug 2820066

Change-Id: I467ea28aaea1c0e36c2d6aabce6a2daea6ee9911
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306383
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2020-12-15 14:13:28 -06:00
Seema Khowala
31b8ecbcee gpu: nvgpu: gp10b: sim: handle priv ring interrupts
priv_ring interrupts are enabled for sim. Handle the
interrupt on sim too.

JIRA NVGPU-4864
JIRA NVGPU-5017

Change-Id: I2ff16c0a8ff152839765556dd3b117995f9de109
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306040
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2020-12-15 14:13:28 -06:00
Philip Elcan
20a4080be0 gpu: nvgpu: quiesce: stop thread gracefully
Previously, nvgpu_sw_quiesce_remove_support() stopped the quiesce
thread abruptly with nvgpu_thread_stop(), which could mean the thread
was killed while still waiting on the cond. Then when the cond was
destroyed, there may be an error since the underlying implementation may
think there is still a thread waiting (such as the Posix
implementation).

Change nvgpu_sw_quiesce_remove_support() to use
nvgpu_thread_stop_graceful() and signal the cond in the callback after
the thread is marked to be stopped. The quiesce thread will then wake up
from the cond wait and see the thread should stop.

JIRA NVGPU-4987

Change-Id: I29322d7867acc33a91092016c540e00bb1ae945a
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306024
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2020-12-15 14:13:28 -06:00
Thomas Fleury
c383b631d7 gpu: nvgpu: check power state in pci shutdown
Bail out if dGPU has not been powered on,

Bug 2867345

Change-Id: I3c388f9fb801cc97de7d9d2c9c3b21bc88e530fa
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304269
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2020-12-15 14:13:28 -06:00
Nicolin Chen
5e854efa65 gpu: nvgpu: Maximize DMA segmentation boundary
Linux kernel has a default 32-bit segmentation boundary for
any device that doesn't explicitly configure it. When nvgpu
tries to allocate a larger memory > 4GB, iommu_dma_map_sg()
function in the kernel will take this boundary into account
and add an internal padding to the allocated IOVA space:

|<---IOVA space 1--->|<---padding--->|<---IOVA space 2--->|

When DMA reads/writes the memory using this discountinued
IOVA space, it may end up with accessing the padding part,
instead of the IOVA space 2.

So this patch adds dma_set_seg_boundary() to nvgpu driver,
by maximizing the segmentation boundary up to DMA_BIT_MASK
to ensure a continued IOVA space.

Bug 200558567

Change-Id: I979d56681dddca56f1b02fce83dc81147a6b0d82
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2304150
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Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Seema Khowala
ffe44aab13 gpu: nvgpu: mc: add hooks for nvgpu-next
JIRA NVGPU-4864

Change-Id: I692d041d005b0d62813df5f16d21c8ae92a2c3e0
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2293201
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
sagar
88e27271eb gpu: nvgpu: fix static analysis issues
coverity tool is not detecting the lenght validation done at caller.
moved length checks to appropriate functions.

used macro instead of hardcoded values.

Jira NVGPU-4780

Change-Id: Ie6b420a6e625eed5374715fd7ca5c87d3ba3d015
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2302335
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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2020-12-15 14:13:28 -06:00
Sagar Kamble
7aea87fb42 gpu: nvgpu: fix syncpt_cmdbuf_gv11b_fusa.o build
On Linux, syncpt_cmdbuf_gv11b_fusa.c was not being compiled under the
config flag CONFIG_TEGRA_GK20A_NVHOST. Fix it.

Bug 2834141

Change-Id: Ib87b019d27f22b534905787b54c807eb7e9e13b4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300720
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Sagar Kamble
630eaa46cb gpu: nvgpu: update the config options & makefile
Added dependency between the Kconfig options as follows where
'->' indicates 'depends on' relation:

SUPPORT_CDE -> COMPRESSION -> DMABUF_HAS_DRVDATA
DGPU -> GK20A_PCI

Defined Kconfig option for VPR and for DGPU that is dependent GK20A_PCI
as well. DGPU related sources are now compiled under config flag DGPU.
Also update conditional compilation of the driver paths w.r.t DGPU,
VPR and COMPRESSION flags.

Bug 2834141

Change-Id: Ia0a39d6d4cf8b36e7f955b7355a5ab41783f821c
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299627
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
Aaron Tian
ef69bbc92b gpu: nvgpu: add unified path of GPU devfreq dev
Add a symbolic link: /sys/devices/gpu.0/devfreq_dev which
pointed to GPU devfreq device: /sys/devices/gpu.0/devfreq/
devfreq<N>. The unified path won't be changed when the
number devfreq<N> is changed.

Bug 200588449

Change-Id: If00c9f9517a13a952d54a2963f31db81fd52e6fb
Signed-off-by: Aaron Tian <atian@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298606
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Leon Yu <leoyu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
Sagar Kamble
74ae8bb20b gpu: nvgpu: add CONFIG_NVGPU_DMABUF_HAS_DRVDATA
dma_buf private data is not supported in upstream kernel. Update
the logic of pin/unpin when this support is not present.

Separate out the related functions to new file and select logic
based on new config flag CONFIG_NVGPU_DMABUF_HAS_DRVDATA.

Bug 2834141

Change-Id: I921758727b1bfc3690f2ab26bccd9befae14d782
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294098
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Sagar Kamble
98e84b8046 gpu: nvgpu: fix the includes in ce unit
As per the coding guidelines, absolute paths in header inclusion are
prohibited. Fix such instances in ce unit.

JIRA NVGPU-5075

Change-Id: I63ebc576e72a8a666a2c9d207dafc4e96473ea32
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2303087
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
rmylavarapu
a23d0c1c19 gpu: nvgpu: Check for timeout and indicate error
For every copy_back enabled PMU cmd sent by NVGPU
we are waiting for PMU response but not checking
for timeout error. This will result in copying invalid
data which causes errors. Implemented timeout check
and return error if timedout.

NVBUG-200530426

Change-Id: I32eba16eeb6f7a56724329ab6d85fae062c6fa3f
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2258947
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2020-12-15 14:13:28 -06:00
rmylavarapu
ed33c465d5 gpu: nvgpu: Check for ACK from PMU before timeout
At present in NVGPU for every get_status cmd we wait
for a response from PMU else timeout. In present code
we look for the ACK very early then after processing
the interrupts, this may result in timeout with valid
response from PMU. To avoid this timeout a check for
ACK is implemented before every timeout check.

NVBUG-200530426

Change-Id: I6f8df51ab73066953ef7c9c05c61aaf543e53b52
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2258899
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Abdul Salam
29d4831780 gpu: nvgpu: Segregate volt unit members based on their accessibility
Currently all unit specific private members are inside ucode_volt_inf.h.
This patch moves the members specific to pmuif to ucode_volt_inf.h and
local to volt.h.
Append all unit specific local functions with volt/nvgpu.
Move volt specific rpc handler from g->pmu to g->pmu->volt.

NVGPU-4492

Change-Id: I626e002b3876c6c5330dec4396b7661b986c6119
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299555
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Divya Singhatwaria
7fb3410d72 gpu: nvgpu: Updated traceability in ACR and PMU
Updated unit test specifcation in ACR and PMU
unit and add traceability from test to design.

JIRA NVGPU-4319
JIRA NVGPU-2192

Change-Id: Iadffaf42f0844c556ba6d9b898d2896863ff0237
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2301579
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2020-12-15 14:13:28 -06:00
Divya Singhatwaria
00b7ea7f13 gpu: nvgpu: Remove hard coded constants from PMU
During code inspection use of some hard coded
constants was found in some parts of the code.
Those constants are replaced by macros

JIRA NVGPU-5031

Change-Id: I50821839bc36c8d28b3e8678abdf82a856b9d8d2
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300562
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Divya Singhatwaria
ed4eb79ac1 gpu: nvgpu: SWUD Lite updates
Updated minor typo errors found during code inspection

JIRA NVGPU-4785
JIRA NVGPU-4789

Change-Id: I37384a852e9a2783e3033a6f12c21eafc00e5bcf
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300560
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
43324f7b1b gpu: nvgpu: Reconcile sim escape paths between RM and nvgpu
SIM models are getting updated to have same escape read path
for RM and nvgpu. Updated nvgpu driver code to have same escape
read mechanism as RM.

This is required for igpu to pass on NET21.

Bug 2539889

Change-Id: I5d37ceb799cafb7fc7dec611fda5f5caac7d7f17
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2130414
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Lakshmanan M <lm@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
6669cbd7de gpu: nvgpu: gv11b: fix veid bundle wait issue
For non go_idle bundles, check should be fe_idle
not gr_idle. fe_gi state will be busy until go_idle
bundle gets processed.

Bug 2804205

Change-Id: I12dd05f59d406aeac9476e0c85b6e457c6bd6bed
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299895
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2020-12-15 14:13:28 -06:00
Rajesh Devaraj
50d71f7c56 gpu: nvgpu: report fecs ctxsw init error
This patch adds callback to report fecs ctxsw init error to 3LSS.
It also moves the related wrapper function to nvgpu_err header
file and adds doxygen documentation.

JIRA NVGPU-5042

Change-Id: I2a051cf19c2940859169799a4dd51adf8870eff4
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2300003
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
Sagar Kamble
18f9d05aae gpu: nvgpu: spec_barrier & DMA_ERROR_CODE update
These macros are not defined in future kernel.

Bug 2834141

Change-Id: Ib2ee419b66f4d949fd538dfbb04b8cffa73c1e44
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299626
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
Scott Long
4fd8df5ca0 gpu: nvgpu: fix misra 10.5 violations
MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.

This change eliminates such a violation in the posix implementation
of nvgpu_thread_cleanup_pop().

Jira NVGPU-3178

Change-Id: I2ad363b4d60c321fa20b23c167d783bebaceb7d3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298986
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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2020-12-15 14:13:28 -06:00
Thomas Fleury
1f9f28df8c gpu: nvgpu: remove barrier from gm20b_channel_bind
In gm20b_channel_bind an nvgpu_smp_wmb() was used presumably to
prevent MMIO writes from being re-ordered after the memory write
to 'ch->bound'. If that was to happen, then unbind routine could
observe the channel as bound and issue concurrent MMIO writes
to unbind the channel. Assuming, the barrier was to prevent
such race, it should have been an nvgpu_wmb(), since
nvgpu_smp_wmb() is for inner shareable domain only.

However, the race possibility between unbind called from close
path and bind from ALLOC_GPFIFO should be ruled out because
close will wait for any active devctl/ioctl to finish before
proceeding.

The race possibility between unbind called from
suspend_all_serviceable_ch path and bind from ALLOC_GPFIFO should
be ruled out because ALLOC_GPFIFO has power refcount at the start
of devctl/ioctl and suspend_all_serviceable_ch is called from
prepare_poweroff path which ensure that power refcount is 0.

Removed nvgpu_smp_wmb().

Jira NVGPU-4927

Change-Id: Ic4f072df364926c10be84e42b83394c13fc97fdc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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2020-12-15 14:13:28 -06:00
Sagar Kamble
6c4a0bb6cd gpu: nvgpu: API updates for newer kernel
access_ok, totalram_pages and zap_vma_ptes are updated in the newer
kernel. Update accordingly.

Bug 2834141

Change-Id: I3097308740f1af3092ac0a5ac2f0146db8148e12
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294097
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2020-12-15 14:13:28 -06:00
Sagar Kamble
d0d8ef79d1 gpu: nvgpu: use READ_ONCE/WRITE_ONCE
In the upstream kernel ACCESS_ONCE is now deprecated with reason as
given in the following related commit:

    commit 381f20fceba8e ("security: use READ_ONCE instead of deprecated
    ACCESS_ONCE")

    ACCESS_ONCE() does not work reliably on non-scalar types. For
    example gcc 4.6 and 4.7 might remove the volatile tag for such
    accesses during the SRA (scalar replacement of aggregates) step.

Replace usages of ACCESS_ONCE with READ_ONCE and WRITE_ONCE in nvgpu.

Bug 2834141

Change-Id: I9904c49e1a4d7b17ed2fe54360051d08595a2982
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2294096
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2020-12-15 14:13:28 -06:00
tkudav
029da0437e gpu: nvgpu: Correct SCP_CTL reg read command
The offsets in minion register manuals are relative to minion base
address. Update the read command to use minion read API instead of
nvgpu_readl().

Change-Id: I6c0e2c11992f69e2fdd9e16dde061c92a771eae0
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292959
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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2020-12-15 14:13:28 -06:00
rmylavarapu
9508cc6f42 gpu: nvgpu: sbr: Load and execute PUB
Implmented functions to load and execute PUB which
is the safety POR.
PUB has following functionality:
1) Lower PLM
2) Reset PMU
3) FBPA register access to devtools

Secure Boot and Runtime (SBR) microcode comprises of
single PLM Update Binary (PUB) which will execute on
SEC2 Engine Falcon. NVGPU shall load and execute PUB
and wait for falcon halt. On successful halt NVGPU
shall proceed with ns ucode loading on respective
falcons.

NVGPU-4549

Change-Id: I8ea897a026bbe2b1714823aba51bfa51864dd68a
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2292330
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2020-12-15 14:13:28 -06:00
Antony Clince Alex
3e6332af9e nvgpu: posix: add fault injection handle
Add fault injection handle for usleep.

Jira: NVGPU-4884

Change-Id: Ibf1fab6680068ff3da7b6e12d9efdb9f09bd1bc9
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2299952
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2020-12-15 14:13:28 -06:00
Petlozu Pravareshwar
d0e81397d5 gpu: nvgpu: unit: update fault injection handler
Update fault injection handling for following mock API:
 - sem_wait()

JIRA NVGPU-3909

Change-Id: I60271153249b77732eb53ef0038a886a51b5c971
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298872
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2020-12-15 14:13:28 -06:00