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290 Commits

Author SHA1 Message Date
Seema Khowala
fb603ef467 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add nvgpu_assert
nvgpu_channel_deferred_reset_engines

JIRA NVGPU-3388

Change-Id: I745de9fb618803824ae62ed586944ce5d838c92a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115787
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:47:24 -07:00
Seema Khowala
334f855ac4 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add void to ignore
the return value
update_gp_get

Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count

JIRA NVGPU-3388

Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:47:14 -07:00
Seema Khowala
766dfb2cb1 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_runlist_reload_ids

JIRA NVGPU-3388

Change-Id: Ie2bf6c48d4f9e673695dc6587df24651e9d8c78c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115767
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:47:05 -07:00
Seema Khowala
c0e725a576 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add nvgpu_assert.
nvgpu_assert is warning on linux but a system halt on safety
builds.
nvgpu_preempt_channel

JIRA NVGPU-3388

Change-Id: Id60d10c0d1593a6b798a037b9ec0efe6c4d20dd5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115762
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:46:56 -07:00
Seema Khowala
7ebb9d85d9 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below functions and print error messages
g->ops.tsg.force_reset
nvgpu_channel_wdt_stop

JIRA NVGPU-3388

Change-Id: Ia02b0fe040d2181a2b2dc24ec56e443f59505e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:46:46 -07:00
Seema Khowala
c986b60c6f gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value and nvgpu_assert for
g->ops.mm.cache.fb_flush(g)

JIRA NVGPU-3388

Change-Id: I24ccc4ae57a2827423db4eb96726a0fe5a7f04df
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:46:36 -07:00
Seema Khowala
c2b3da8e47 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Change gk20a_free_priv_cmdbuf from int to void type

Rename
gk20a_free_priv_cmdbuf -> nvgpu_channel_update_priv_cmd_q_and_free_entry
channel_gk20a_free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_q
free_priv_cmdbuf -> nvgpu_channel_free_priv_cmd_entry

JIRA NVGPU-3388
JIRA NVGPU-3248

Change-Id: I32bc5686a280f72c7bba4ab2d37782e29117f596
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-15 16:46:27 -07:00
Thomas Fleury
93bfdd3207 gpu: nvgpu: remove unused ch->gpfifo.wrap 
ch->gpfifo.wrap was set when updating ch->gpfifo.get,
but never used afterwards. Removed.

Jira NVGPU-3388

Change-Id: I198e9ba0c3716a200a8937c2488cf35e04c0166f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118184
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-14 18:40:21 -07:00
Seema Khowala
8d34edfee0 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below function and add err message
ch_data->unbind_single_channel

JIRA NVGPU-3388

Change-Id: Iac979c464600507b3fcfa907d9babc8bdc232338
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115832
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-13 14:10:27 -07:00
Seema Khowala
970096bfe4 gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of below functions and add warn/err messages
nvgpu_cond_broadcast_interruptible
nvgpu_cond_broadcast
nvgpu_cond_init

JIRA NVGPU-3388

Change-Id: Ie5fd9c461c00066d703e0d5900fc0248da2204db
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114919
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 22:28:22 -07:00
Seema Khowala
877de5b6bd gpu: nvgpu: channel MISRA fix for Rule 8.4 
JIRA NVGPU-3388

Change-Id: I7633639f78f5585bdfb0b99459f82b36136fd31a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114894
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 22:28:12 -07:00
Seema Khowala
e7d50bd224 gpu: nvgpu: channel MISRA fix for Rule 10.4 
Change local variable types to match types defined in struct
being accessed to assign local variables

Change input param types to match types defined in struct
being accessed to pass input params

JIRA NVGPU-3388

Change-Id: If3edc34de14d35d13e0a24e3c48f9cecc2df2a24
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114872
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 22:27:52 -07:00
Seema Khowala
e6a8e63bb6 gpu: nvgpu: channel MISRA fix for Rule 10.1 
JIRA NVGPU-3388

Change-Id: I11b287239a36eaab5582428eb0d209520d0f286a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114871
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 22:27:43 -07:00
Seema Khowala
671f1c8a36 gpu: nvgpu: channel MISRA fix for Rule 21.2 
Rename
_gk20a_channel_get -> nvgpu_channel_get__func
gk20a_channel_get -> nvgpu_channel_get
_gk20a_channel_put -> nvgpu_channel_put__func
gk20a_channel_put -> nvgpu_channel_put
trace_gk20a_channel_get -> trace_nvgpu_channel_get
trace_gk20a_channel_put -> trace_nvgpu_channel_put

JIRA NVGPU-3388

Change-Id: I4e37adddbb5ce14aa18132722719ca2f73f1ba52
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114118
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 04:39:34 -07:00
Seema Khowala
26d13b3b6b gpu: nvgpu: channel MISRA fix for Rule 21.2 
Rename functions starting with '_' and '__'.
__gk20a_channel_kill -> nvgpu_channel_kill
_gk20a_channel_from_id -> nvgpu_channel_from_id__func
gk20a_channel_from_id -> nvgpu_channel_from_id

JIRA NVGPU-3388

Change-Id: I3b5f63bf214c5c5e49bc84ba8ef79bd49831c56e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114037
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 04:39:08 -07:00
Seema Khowala
842c42249d gpu: nvgpu: channel MISRA fix for Rule 8.6 
Remove unused function prototype.

JIRA NVGPU-3388

Change-Id: I3e6ce2321ab0ef5a73c257fc4ece984c02a0a051
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114036
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-09 04:38:53 -07:00
Seema Khowala
3d64bc19df gpu: nvgpu: channel MISRA fix for Rule 17.7 
Check return value of nvgpu_timeout_init and spit
error message. Also return to the calling function
upon timeout init error in few cases.

JIRA NVGPU-3383

Change-Id: I97fcc7343051842a74d9bf379c372b7094c8de86
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113157
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-07 20:28:21 -07:00
Thomas Fleury
44f6c10947 gpu: nvgpu: submit MISRA fixes for Rule 5.7 
Renamed local variable
- sync_fence -> flag_sync_fence

As "sync_fence" is already used to represent a type.

Also, renamed for consistency:
- fence_wait -> flag_fence_wait
- fence_get -> flag_fence_get

Jira NVGPU-3384

Change-Id: Ib40d068f0ebda985303a85a385f4123955d3b4c9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111613
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 17:55:42 -07:00
Thomas Fleury
47b7820cb6 gpu: nvgpu: submit MISRA fixes for Rule 17.7 
Check return value of gk20a_channel_add_job, and clean up
in case of failure.

Jira NVGPU-3384

Change-Id: Ic818d8bcf97fef6360aedd7a2a0a5a7f6f69150f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111612
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 17:55:28 -07:00
Thomas Fleury
9f5ca49a07 gpu: nvgpu: submit MISRA fixes for Rule 15.7 
Refactored if / else statements in nvgpu_submit_channel_gpfifo
to avoid "else if" with no terminating "else" statement.

Jira NVGPU-3384

Change-Id: If553901f418455d77c372fd1d7113553a21096e1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111611
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 17:55:13 -07:00
Thomas Fleury
8b32821634 gpu: nvgpu: submit MISRA fixes for Rule 14.3 
(!c->deterministic) ||
(nvgpu_is_enabled(g, NVGPU_CAN_RAILGATE) && !c->deterministic)

is equivalent to

(!c->deterministic)

Remove second condition in nvgpu_submit_channel_gpfifo

Jira NVGPU-3384

Change-Id: Icf3e460d4fe9d310d94a21895832bbfae595df28
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111610
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 17:54:59 -07:00
Thomas Fleury
1374fba039 gpu: nvgpu: engines MISRA fixes for Rule 10.4 
engine_id cannot be compared directly with NVGPU_ENGINE_GR.
Instead, retrieve engine_info from engine_id, and compare
engine_info->engine_enum with NVGPU_ENGINE_GR

Jira NVGPU-3385

Change-Id: I45a2baaefc2d35521d12ba530b151c6ab7719b68
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111650
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 15:35:07 -07:00
Thomas Fleury
6fe4c09c68 gpu: nvgpu: engines MISRA fixes for Rule 10.3 
Use BIT32 for shift operation on u32 act_eng_id.

Jira NVGPU-3385

Change-Id: I92f55bceafb87ba385786360f8df95f128b92351
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113034
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 15:34:53 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs 
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-06 02:56:53 -07:00
Thomas Fleury
0d1100f2de gpu: nvgpu: tsg MISRA fixes for Rule 17.7 
Check return value of channel_gk20a_update_runlist in
nvgpu_tsg_unbind_channel, and throw an error in case
of failure.

Jira NVGPU-3380

Change-Id: I1214b117d3d202fd805ae8c1fe00cdcc043e621f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111385
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:27:58 -07:00
Thomas Fleury
86859555f8 gpu: nvgpu: tsg MISRA fixes for Rule 15.7 
Refactored if / else statements in nvgpu_tsg_bind_channel and
nvgpu_tsg_check_ctxsw_timeout to avoid "else if" with no
terminating "else" statement.

Jira NVGPU-3380

Change-Id: I741cfbd49c7cb510fff03249e464bb4405ec903f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111384
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:27:43 -07:00
Thomas Fleury
e6638354e9 gpu: nvgpu: tsg MISRA fixes for Rule 14.2 
nvgpu_list_for_each_entry_safe violates MISRA Rule 14.2, as
it uses comma separator in the for clauses. Use a while loop
instead in nvgpu_tsg_release, as we want to empty the list.

Jira NVGPU-3380

Change-Id: I38211cc326e458d0912f374e3692328fb4e9b191
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111383
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:27:29 -07:00
Vinod G
fd79ecec05 gpu: nvgpu: Remove unused gr_priv header include 
Remove unused gr_priv.h and gr.h include from two files.

Jira NVGPU-3218

Change-Id: Ic3ec9a07d2e6928444490d3bc874702a76d0c2c8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110725
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:26:46 -07:00
Seema Khowala
cfb4ff0bfb gpu: nvgpu: rename struct fifo_gk20a 
Rename
struct fifo_gk20a -> nvgpu_fifo

JIRA NVGPU-2012

Change-Id: Ifb5854592c88894ecd830da092ada27c7f05380d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109625
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-03 16:25:43 -07:00
Seema Khowala
170d7464d6 gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo 
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo

Add missing includes for fifo subunits.

JIRA NVGPU-2012

Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:40:42 -07:00
Seema Khowala
39070c653f gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h 
Move and rename
FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID
FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID
FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID
FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID
FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID

JIRA NVGPU-2012

Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109011
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:40:26 -07:00
Seema Khowala
034d44311e gpu: nvgpu: move profile related struct and func 
Add include/nvgpu/profile.h

Move from fifo_gk20a.h to include/nvgpu/profile.h and rename

fifo_profile_gk20a -> nvgpu_profile
gk20a_fifo_profile_acquire -> nvgpu_profile_acquire
gk20a_fifo_profile_release -> nvgpu_profile_release
gk20a_fifo_profile_snapshot -> nvgpu_profile_snapshot

JIRA NVGPU-2012

Change-Id: I4f9fde9f0ccdeedec62d1f612046be14db334a89
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109010
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:40:09 -07:00
Seema Khowala
296ff58eb1 gpu: nvgpu: move engine related struct 
Move from fifo_gk20a.h to engines.h
fifo_pbdma_exception_info_gk20a
fifo_engine_exception_info_gk20a
fifo_engine_info_gk20a

Rename
fifo_pbdma_exception_info_gk20a -> nvgpu_pbdma_exception_info
fifo_engine_exception_info_gk20a -> nvgpu_engine_exception_info
fifo_engine_info_gk20a -> nvgpu_engine_info
NVGPU_ENGINE_GR_GK20A -> NVGPU_ENGINE_GR
NVGPU_ENGINE_GRCE_GK20A -> NVGPU_ENGINE_GRCE
NVGPU_ENGINE_ASYNC_CE_GK20A -> NVGPU_ENGINE_ASYNC_CE
NVGPU_ENGINE_INVAL_GK20A -> NVGPU_ENGINE_INVAL

JIRA NVGPU-2012

Change-Id: I665487721608ff9eacbdebff17d9dbef653de55e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109009
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:59 -07:00
Seema Khowala
3392a72d1a gpu: nvgpu: move runlist related struct and defines 
Move from fifo_gk20a.h to runlist.h
RUNLIST_DISABLED
RUNLIST_ENABLED
MAX_RUNLIST_BUFFERS
struct fifo_runlist_info_gk20a

Rename
fifo_runlist_info_gk20a -> nvgpu_runlist_info

JIRA NVGPU-2012

Change-Id: Ib7e3c9fbf77ac57f25e73be8ea64c45d4c3155ff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109008
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:42 -07:00
Seema Khowala
4b64b3556a gpu: nvgpu: add fifo.bar1_snooping_disable hal 
Add fifo.bar1_snooping_disable hal

Rename and move from fifo_gk20a.c to fifo.c
gk20a_fifo_suspend -> nvgpu_fifo_suspend

Rename
gk20a_readl -> nvgpu_readl
gk20a_writel -> nvgpu_writel

Remove unused defines and function prototypes
from fifo_gk20a.h

JIRA NVGPU-2012

Change-Id: If7eed93340c5c60802b1af40790482fd5e1b33c1
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109007
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 23:39:25 -07:00
Thomas Fleury
bfafc8c4f1 gpu: nvgpu: runlist MISRA fixes for Rule 17.7 
Check return code for nvgpu_pmu_lock_release,
g->ops.runlist.reschedule_preempt_next_locked and
g->ops.runlist.wait_pending and throw an
error message in case of failure.

Jira NVGPU-3379

Change-Id: If8a88e54f3dc769c70b772dfc93acfffb4b38d4d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109684
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:54 -07:00
Thomas Fleury
6e83701982 gpu: nvgpu: runlist MISRA fixes for Rule 15.7 
All "if(expr) else if" constructs shall be terminated with
an else statement. Re-factored checks to avoid "else if"
statement.

Jira NVGPU-3379

Change-Id: Idf8a80a3f314fcf3f3b7a0c6f01bbb9d2202bdf2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109683
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:45 -07:00
Thomas Fleury
0d4ef5fa34 gpu: nvgpu: runlist MISRA fixes for Rule 14.3 
Removed (engine_info != NULL) test in nvgpu_init_runlist_enginfo,
as it cannot be NULL by construction.

Jira NVGPU-3379

Change-Id: I76392a1adf7d4d1c1438a67a0142f4e50ca68eab
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109682
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:36 -07:00
Thomas Fleury
af84bdaae8 gpu: nvgpu: runlist MISRA fixes for Rule 10.4 
Fixed essential type for flags argument (0ULL) passed to
nvgpu_dma_alloc_flags_sys.

Jira NVGPU-3379

Change-Id: I3ab97d98b19bf168ba7a1c2a9357e778b1a242d5
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109681
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:27 -07:00
Thomas Fleury
c5f873fa31 gpu: nvgpu: runlist MISRA fixes for Rule 10.3 
Using u32 with bitops like for_each_set_bit results in MISRA
violation as bitops internally uses unsigned long.
Define tsgid as unsigned long an use (u32) cast when needed.

Jira NVGPU-3379

Change-Id: I99f9dae18ee74223de40dd5990bfad4eee2f4559
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109680
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 17:05:18 -07:00
Seshendra Gadagottu
57be9a09fd gpu: nvgpu: remove circular dependency between gr and fifo 
channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.

Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);

JIRA NVGPU-3214

Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-01 20:36:30 -07:00
Vinod G
7581601f80 gpu: nvgpu: gr_priv header cleanup 
Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.

Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.

Jira NVGPU-3218

Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-01 16:15:32 -07:00
Alex Waterman
c71e764348 gpu: nvgpu: Remove alloc_inst_block from mm HAL 
The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().

JIRA NVGPU-2042

Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-01 15:06:42 -07:00
Thomas Fleury
258a6141fd gpu: nvgpu: rename runlist functions 
Renamed:
- gk20a_runlist_reload -> nvgpu_runlist_reload
- gk20a_fifo_interleave_level_name -> nvgpu_runlist_interleave_level_name
- gk20a_runlist_update_for_channel -> nvgpu_runlist_update_for_channel
- nvgpu_fifo_lock_active_runlists -> nvgpu_runlist_lock_active_runlists
- nvgpu_fifo_unlock_active_runlists -> nvgpu_runlist_unlock_active_runlists
- nvgpu_fifo_get_runlists_mask -> nvgpu_runlist_get_runlists_mask
- nvgpu_fifo_unlock_runlists -> nvgpu_runlist_unlock_runlists
- gk20a_runlist_update -> nvgpu_runlist_update

Jira NVGPU-3198

Change-Id: Ifc5ad2aae546614667c174643ee07283d2716adc
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108029
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-30 12:46:02 -07:00
Thomas Fleury
58167f6601 gpu: nvgpu: clean runlist dependencies 
Split existing runlist HALs into:
- runlist HALs depending on ram hw headers
- runlist HALs depending on fifo hw headers

hal/fifo/runlist_<chip>.c implement
- runlist.entry_size
- runlist.get_tsg_entry
- runlist.get_ch_entry

hal/fifo/runlist_fifo_<chip>.c implement
- runlist.reschedule
- runlist.count_max
- runlist.entry_size
- runlist.hw_submit

Renamed
- nvgpu_fifo_reschedule_runlist -> nvgpu_runlist_reschedule

Jira NVGPU-3198

Change-Id: Icf835b0a4a45e5987e3db9d0931a9f111f418137
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107603
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-30 12:44:20 -07:00
Vaibhav Kachore
f9cc478c31 gpu: nvgpu: change return type of resume_all_serviceable_ch 
- nvgpu_channel_resume_all_serviceable_ch is always returning 0. So,
it is safe to change return type of this function to void.
- This is required to fix MISRA violation: MISRA C-2012 Rule 17.7:
The value returned by a function having non-void return shall be
used.

JIRA NVGPU-3140

Change-Id: I12930ddb21b506266664aac8905326204e9483eb
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2106989
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-29 14:37:22 -07:00
Debarshi Dutta
965062c2bc gpu: nvgpu: remove direct tsg retrieval from fifo 
Added
- nvgpu_tsg_check_and_get_from_id
- nvgpu_tsg_get_from_id

And removed direct accesses to f->tsg array.

Jira NVGPU-3156

Change-Id: I8610e19c1a6e06521c16a1ec0c3a7a011978d0b7
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101251
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:16:47 -07:00
Thomas Fleury
124cdb4509 gpu: nvgpu: move set_interleave to tsg 
Renamed
- gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave

Moved set_interleave from runlist to tsg
- runlist.set_interleave -> tsg.set_interleave

Existing HAL was only setting tsg->interleave, and was not
accessing any register. This is now done in nvgpu_tsg_set_interleave
and tsg.set_interleave is only used in vgpu case.

Jira NVGPU-3156

Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100610
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:16:04 -07:00
Thomas Fleury
3fde3ae650 gpu: nvgpu: move set_timeslice to tsg 
Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us

Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us

Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.

Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry

Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.

Added #defines for min, max and default timeslices.

Jira NVGPU-3156

Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:15:49 -07:00
Vinod G
b32babc7df gpu: nvgpu: gr_priv header cleanup 
Remove unused gr_priv header from channel.c

Jira NVGPU-3218

Change-Id: I3a15f63c8173b1bf84a4965a1a5b2ab0a12ce05a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104478
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-24 23:44:21 -07:00