Renamed local variable
- sync_fence -> flag_sync_fence
As "sync_fence" is already used to represent a type.
Also, renamed for consistency:
- fence_wait -> flag_fence_wait
- fence_get -> flag_fence_get
Jira NVGPU-3384
Change-Id: Ib40d068f0ebda985303a85a385f4123955d3b4c9
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111613
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(!c->deterministic) ||
(nvgpu_is_enabled(g, NVGPU_CAN_RAILGATE) && !c->deterministic)
is equivalent to
(!c->deterministic)
Remove second condition in nvgpu_submit_channel_gpfifo
Jira NVGPU-3384
Change-Id: Icf3e460d4fe9d310d94a21895832bbfae595df28
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111610
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nvgpu_list_for_each_entry_safe violates MISRA Rule 14.2, as
it uses comma separator in the for clauses. Use a while loop
instead in nvgpu_tsg_release, as we want to empty the list.
Jira NVGPU-3380
Change-Id: I38211cc326e458d0912f374e3692328fb4e9b191
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111383
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Check return code for nvgpu_pmu_lock_release,
g->ops.runlist.reschedule_preempt_next_locked and
g->ops.runlist.wait_pending and throw an
error message in case of failure.
Jira NVGPU-3379
Change-Id: If8a88e54f3dc769c70b772dfc93acfffb4b38d4d
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109684
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Using u32 with bitops like for_each_set_bit results in MISRA
violation as bitops internally uses unsigned long.
Define tsgid as unsigned long an use (u32) cast when needed.
Jira NVGPU-3379
Change-Id: I99f9dae18ee74223de40dd5990bfad4eee2f4559
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109680
Reviewed-by: Automatic_Commit_Validation_User
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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Remove gr_priv.h from outside gr files.
Add hal function in gr.init for get_no_of_sm. This helps
to avoid dereferencing gr in couple of files for g->gr->config and
avoid gr_priv.h include in those files.
Replace nvgpu_gr_config_get_no_of_sm call with
g->ops.gr.init.get_no_of_sm for files outside gr unit.
Jira NVGPU-3218
Change-Id: I435bb233f70986e31fbfcb900ada3b3bda0bc787
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109182
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The alloc_insty_block() function in the MM HAL is not a HAL. It does
not abstract any HW accesses; instead it just wraps a dma allocation.
As such remove it from the HAL and move the single gk20a implementation
to common/mm/mm.c as nvgpu_alloc_inst_block().
JIRA NVGPU-2042
Change-Id: I0a586800a11cd230ca43b85f94a35de107f5d1e1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109049
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- nvgpu_channel_resume_all_serviceable_ch is always returning 0. So,
it is safe to change return type of this function to void.
- This is required to fix MISRA violation: MISRA C-2012 Rule 17.7:
The value returned by a function having non-void return shall be
used.
JIRA NVGPU-3140
Change-Id: I12930ddb21b506266664aac8905326204e9483eb
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2106989
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Renamed
- gk20a_tsg_set_runlist_interleave -> nvgpu_tsg_set_interleave
Moved set_interleave from runlist to tsg
- runlist.set_interleave -> tsg.set_interleave
Existing HAL was only setting tsg->interleave, and was not
accessing any register. This is now done in nvgpu_tsg_set_interleave
and tsg.set_interleave is only used in vgpu case.
Jira NVGPU-3156
Change-Id: I5dac1305afcbd950214316289cf704ee8b43fc89
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100610
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Moved the following HALs from fifo to tsg
- set_timeslice
- default_timeslice_us
Renamed
- gk20a_tsg_set_timeslice -> nvgpu_tsg_set_timeslice
- min_timeslice_us -> tsg_timeslice_min_us
- max_timeslice_us -> tsg_timeslice_max_us
Scale timeslice to take into account PTIMER clock in
nvgpu_runlist_append_tsg.
Removed gk20a_channel_get_timescale_from_timeslice, and
instead moved timeout and scale computation into runlist HAL,
when building TSG entry:
- runlist.get_tsg_entry
Use ram_rl_entry_* accessors instead of hard coded values
for default and max timeslices.
Added #defines for min, max and default timeslices.
Jira NVGPU-3156
Change-Id: I447266c087c47c89cb6a4a7e4f30acf834b758f0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100052
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Move chip specific recovery code for volta onwards
architecture to hal/rc/rc_gv11b.c
Rename
fifo.teardown_ch_tsg -> fifo.recover
gk20a_runlist_update_locked -> nvgpu_runlist_update_locked
Remove
Unused h/w headers from fifo_gv11b.c
Use local variable f instead of g->fifo
JIRA NVGPU-1314
Change-Id: Ia535bbe4780e7241fdd911a8f577c6b98cf0fe53
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102897
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Currently, both clk_arb and channels use their own implementation of
a background worker. These implementations are almost identical and can
be extracted out into a single self-contained unit name nvgpu_worker.
Another advantage of using a single worker unit is to avoid duplication
of Unit Tests for this unit in other units.
channel and clk_arb units provide their own specific implementations
via an ops interface named nvgpu_worker_ops which is a part of the
nvgpu_worker struct.
The following high level APIs are exposed by the nvgpu_worker
nvgpu_worker_should_stop
nvgpu_worker_enqueue
nvgpu_worker_init
nvgpu_worker_deinit
The nvgpu_worker_ops containg the following function pointers
pre_process
wakeup_early_exit
wakeup_post_process
wakeup_process_item
wakeup_condition
wakeup_timeout
The specific code in channel and clk_arb is changed to use the above
implementations instead of their own separate implementations.
Jira NVGPU-3101
Change-Id: I14a0bba6a3d61a642b858dec70d5818d5a0472a4
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090475
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Basic units like fifo, rc are having dependency on
gr_falcon. Avoided outside gr units dependency on gr_falcon
by moving following functions to gr:
int nvgpu_gr_falcon_disable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_disable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_enable_ctxsw(struct gk20a *g,
struct nvgpu_gr_falcon *falcon); ->
int nvgpu_gr_enable_ctxsw(struct gk20a *g);
int nvgpu_gr_falcon_halt_pipe(struct gk20a *g); ->
int nvgpu_gr_halt_pipe(struct gk20a *g);
HALs also moved accordingly and updated code to reflect this.
Also moved following data back to gr from gr_falcon:
struct nvgpu_mutex ctxsw_disable_mutex;
int ctxsw_disable_count;
JIRA NVGPU-3168
Change-Id: I2bdd4a646b6f87df4c835638fc83c061acf4051e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100009
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Move chip specific preempt code to hal/fifo
Move non-chip specific preempt code to common/fifo
Remove fifo.get_preempt_timeout
Rename gk20a_fifo_get_preempt_timeout -> nvgpu_preempt_get_timeout
Rename gk20a_fifo_preempt -> nvgpu_preempt_channel
Add fifo.preempt_trigger hal for issuing preempt
Add fifo.preempt_runlists_for_rc hal for preempting runlists during rc
Add fifo.preempt_poll_pbdma hal
Add nvgpu_preempt_poll_tsg_on_pbdma to be called from rc
JIRA NVGPU-3144
Change-Id: Idb089acaa0c6ca08de17487c3496459a61f0bcd4
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2100819
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