GR tick frequency needs to be set to MAX value for profiler
use cases for gp10b/gv11b/tu104 chips.
Add new HAL g->ops.ptimer.config_gr_tick_freq() that configures GR
tick frequency to MAX value and call this HAL in GPU poweron path.
This support is not needed in safety build, so compile everything
only if CONFIG_NVGPU_DEBUGGER is enabled
Bug 200289214
Change-Id: Id8378540cc67ca0041b56990f8676e3a105403a5
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195163
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For safety build, nvgpu driver should enter SW quiesce state
in case an uncorrectable error has occurred. In this state, any
activity on the GPU should be prevented, without powering off the GPU.
Also, a minimal set of operations should be used to enter SW quiesce
state.
Entering SW quiesce state does the following:
- set sw_quiesce_pending: when this flag is set, interrupt
handlers exit after masking interrupts. This should help mitigate
an interrupt storm.
- wake up thread to complete quiescing.
The thread performs the following:
- set NVGPU_DRIVER_IS_DYING to prevent allocation of new resources
- disable interrupts
- disable fifo scheduling
- preempt all runlists
- set error notifier for all active channels
Note: for channels with usermode submit enabled, userspace can
still ring doorbell, but this will not trigger any work on
engines since fifo scheduling is disabled.
Jira NVGPU-3493
Change-Id: I639a32da754d8833f54dcec1fa23135721d8d89a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2172391
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Change the directly called init functions to function pointers in the
HAL. This makes it more consistent. This also allows for writing more
comprehensive unit tests for nvgpu.common.init.
JIRA NVGPU-2239
Change-Id: I05d739a8f8a2e7d385322d93154206eb0bfddc10
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2173920
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CE app functionality from nvgpu is non-safe for igpu. CE engines init
/reset/cg related functionality is required in safety. Hence move the
CE app logic under CONFIG_NVGPU_DGPU flag and update the sources
accordingly.
JIRA NVGPU-3814
Change-Id: I37aa00b1184baccd5fe569ec315be60ac42dac9b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168956
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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- In GV11B, read fuse_status_opt_tpc_gpc register
to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
be set to true or false and mask will be used to write to
fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
sent from userspace is valid and can be used to power gate
the desired TPC
- can_tpc_powergate = false indicates that the mask value
sent from userspace is not valid and cannot be used to
power gate the desired TPC.
Bug 200532639
Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2170736
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If CONFIG_NVGPU_CE is disabled, nvgpu right now does not even reset
the CE engines or initialize prod values.
This ultimately needs to be fixed by adding appropriate initialization
for CE engines even if CONFIG_NVGPU_CE is disabled.
For now, add the code to at least reset CE engines if CONFIG_NVGPU_CE
is disabled
Bug 2526212
Change-Id: Id0a6fbfe44ef7af62715bcee65bef056359f1c19
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165861
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files
JIRA NVGPU-3418
Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
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- Fix Rule 16.1 and 16.6 violations:
Every switch statement shall have at least two
switch-clauses
- Fix Rule 15.6 violations:
The body of an iteration statement shall be a
compound statement.
- Fix Rule 17.7 violations:
The return value of a non-void function shall
be used.
JIRA NVGPU-3546
Change-Id: I475d185945f0998d4d359f4b9ded6e983474f01f
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127923
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renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0
JIRA NVGPU-3418
Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
.init = gv100_bios_init,
.preos_wait_for_halt = gv100_bios_preos_wait_for_halt,
.preos_reload_check = gv100_bios_preos_reload_check,
.devinit = gp106_bios_devinit,
.preos = gp106_bios_preos,
.verify_devinit = NULL,
This was being called as:
g->ops.bios.init(g)
g->ops.bios.preos_wait_for_halt(g)
g->ops.bios.preos_reload_check(g)
g->ops.bios.preos(g)
g->ops.bios.devinit(g)
g->ops.bios.verify_devinit(g)
Change the function access by using sw ops, like:
Create new function: nvgpu_bios_sw_init()
and based on hardware chip call the chip specific
bios sw init function: nvgpu_gv100_bios_sw_init()
and nvgpu_tu104_bios_sw_init()to assign the sw
ops
JIRA NVGPU-2071
Change-Id: Ibfcd9b225a7bc184737abdd94c2e54190fcd90a0
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108526
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Fix 8.2 violation for not specifying parameter name in prototype of
secure_alloc().
Fix 21.3 & 21.8 violations for using reserved names "free" and "exit."
Fix 8.6 and 21.2 violations for __gk20a_do_idle() and
__gk20a_do_unidle() by renaming the functions and wrapping them in a
missing #ifdef CONFIG_PM.
Fix 5.7 violation for reusing "class" as parameter name when already
defined as a struct.
JIRA NVGPU-3343
Change-Id: I976e95a32868fa0a657f4baf0845a32bd7aceb9e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117913
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Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.
Allocation happens at pmu early init stage & will deinit at
remove_support stage.
JIRA NVGPU-1972
Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
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Update the shared config file to use the safety build flag NV_BUILD_
CONFIGURATION_IS_SAFETY instead of NVGPU_REDUCED. With these changes
posix userspace and tests will be built in two configs based on this
flag.
JIRA NVGPU-3062
Change-Id: Iaf34dd1a8f66f2dd3f351365c369ed46a484a257
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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MISRA Rule 13.5 states that the right hand operand of a logical && or ||
operator shall not have persistent side effects. Update the while loop
in gk20a_wait_for_idle() to comply.
JIRA NVGPU-3318
Change-Id: I3e51361914c298416bab1f2f7500d743ce409c8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114658
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MISRA Rule 21.2 prohibits naming identifiers beginning with a double
underscore. This updates the function names __nvgpu_check_gpu_state()
and __gk20a_warn_on_no_regs() to comply.
JIRA NVGPU-3318
Change-Id: Ied2d168272a0f45fb8a08dda0e6fc798ebe3d22d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114656
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Modified PMU subunits init sequence as they required during PMU RTOS
initialize stage, function nvgpu_pmu_early_init() allocates space for
all its subunit & its default values for further usage during runtime,
and function nvgpu_pmu_init() performs setup for sub units & starts
PMU-RTOS boot.
Deinit of all sub units allocated space will handled as part of
remove_support stage & also, during init stage upon failure of
init/setup sequence.
JIRA NVGPU-1972
Change-Id: I3ead9f9bb9e9c1178a02fc99eeec276660477325
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110154
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MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.
This patch fixes some of these reported violations.
Jira NVGPU-858
Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
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create a new unit common.fbp which initializes fbp support and provides
APIs to retrieve fbp data.
Create private header with below data
struct nvgpu_fbp {
u32 num_fbps;
u32 max_fbps_count;
u32 fbp_en_mask;
u32 *fbp_rop_l2_en_mask;
};
Expose below public APIs to initialize/remove fbp support:
nvgpu_fbp_init_support()
nvgpu_fbp_remove_support()
vgpu_fbp_init_support() for vGPU
Expose below APIs to retrieve fbp data
nvgpu_fbp_get_num_fbps()
nvgpu_fbp_get_max_fbps_count()
nvgpu_fbp_get_fbp_en_mask()
nvgpu_fbp_get_rop_l2_en_mask()
Use above APIs to retrieve fbp data in all the code.
Remove corresponding fields from struct nvgpu_gr since they are no
longer referred from that structure
Jira NVGPU-3124
Change-Id: I027caf4874b1f6154219f01902020dec4d7b0cb1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Several of the nvgpu driver capabilities will be disabled in the reduced
version. To know the version of the nvgpu driver we introduce a new
global characteristic flag NVGPU_DRIVER_REDUCED_PROFILE.
JIRA NVGPU-3062
Change-Id: I93c76df1110c24ea0055c77d332fe297d56db65d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108143
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Removed gr dependency on ecc by moving ecc init/remove support
calls to nvgpu_init. With this, only dependency from ecc to gr
present.
Added following parameter in struct nvgpu_ecc to check/update ecc
initialization status:
bool initialized;
JIRA NVGPU-3212
Change-Id: I04611175cbd959cb8082e63c30214266f5d5b731
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107955
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Created PMU fw unit to hold PMU RTOS f/w specific ops, images,
flags & command arguments needed for PMU RTOS ucode support.
Moved PMU fw ops from gk20a.gpu_ops to pmu.fw.ops as these ops
are needed to support different version of PMU fw version for
different chips
JIRA NVGPU-1955
Change-Id: I51385d8c20524431f07cba3378676464663deb20
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090769
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Description:
Present p-state unit handle both pstate boardobj and
initializing all the units. As part of restructuring,
the pstate unit is separated into two units:
1) Perf_pstate: This unit will handle pstate boardobjs.
2) Pmu_pstate: This unit will initialize all the units
which supoort performance states.
Changes:
1) Created pmu_pstate unit.
2) Pstate boardobjs are moved under perf_pstate which
is under perf unit.
NVGPU-1958
Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096339
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Added new function to add require sw initionaltions. before enabling
gr hw. Added nvgpu_netlist_init_ctx_vars and nvgpu_gr_falcon_init_support
as part of this function:
int nvgpu_gr_prepare_sw(struct gk20a *g)
Moved following structure defs from gr_gk20a.h to gr_falcon.h and
renamed appropriately:
gk20a_ctxsw_ucode_segment -> nvgpu_ctxsw_ucode_segment
gk20a_ctxsw_ucode_segments -> nvgpu_ctxsw_ucode_segments
Moved following struct to gr_falcon_priv.h:
gk20a_ctxsw_ucode_info -> nvgpu_ctxsw_ucode_info
Moved following data from struct gk20a to new structure in gr_falcon_priv.h
struct nvgpu_gr_falcon:
struct nvgpu_mutex ctxsw_disable_lock;
int ctxsw_disable_count;
struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
Also moved following data from gr_gk20.h to struct nvgpu_gr_falcon:
struct nvgpu_mutex fecs_mutex;
bool skip_ucode_init;
wait_ucode_status
GR_IS_UCODE related enums
eUcodeHandshakeInit enums
Now add a pointer to this new data structure from struct gr_gk20a to
access gr_falcon related data and modified code to reflect this
change:
struct nvgpu_gr_falcon *falcon;
Added following functions to access gr_falcon data:
struct nvgpu_mutex *nvgpu_gr_falcon_get_fecs_mutex(
struct nvgpu_gr_falcon *falcon);
struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_fecs_ucode_segments(
struct nvgpu_gr_falcon *falcon);
struct nvgpu_ctxsw_ucode_segments *nvgpu_gr_falcon_get_gpccs_ucode_segments(
struct nvgpu_gr_falcon *falcon);
void *nvgpu_gr_falcon_get_surface_desc_cpu_va(
struct nvgpu_gr_falcon *falcon);
JIRA NVGPU-1881
Change-Id: I9100891989b0d6b57c49f2bf00ad839a72bc7c7e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2091358
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