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639 Commits

Author SHA1 Message Date
Sagar Kadamati
d2444e85ed gpu: nvgpu: compile-out debug unit 
debug unit is not need to for safety build, so compile out it

JIRA NVGPU-3542

Change-Id: I60cc256a5659e72ae2e647ec4f1a810ba4aa959d
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133419
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-21 04:35:25 -07:00
Sagar Kamble
5d37a9e489 gpu: nvgpu: compile out sim changes from safety build 
As sim is non-safe unit compile it out. Also removed FMODEL related
nvgpu changes and unit tests from the safety build.

JIRA NVGPU-3527

Change-Id: I22c83e195a09f9150fb6f5a3afff91df2ea075b9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2139455
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-20 16:05:33 -07:00
Rajesh Devaraj
29ec6ad40f gpu: nvgpu: report fb_flush_timeout error 
This patch adds the support to report fb_flush_timeout error to 3LSS.
Specifically, it adds the following service-ID:
NVGUARD_SERVICE_IGPU_HOST_SWERR_PFIFO_FB_FLUSH_TIMEOUT_ERROR

JIRA NVGPU-3460
JIRA NVGPU-3461

Change-Id: Iddf978eedbc676197a19e47e72e08cd71c478a08
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2138051
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-19 22:51:20 -07:00
Deepak Nibade
0755b25231 gpu: nvgpu: remove reset and enable/disable ctxsw hals 
Remove below hals since the corresponding functions are same on all
platforms and they are h/w independent
g->ops.gr.enable_ctxsw()
g->ops.gr.disable_ctxsw()
g->ops.gr.reset()

Call the functions directly at all places

Remove CONFIG_NVGPU_DEBUGGER from places where these functions are
called since they are not debugger dependent
This also helps to disable CONFIG_NVGPU_DEBUGGER and to keep recovery
sequence intact

Jira NVGPU-3506

Change-Id: Id2b208ca23dc4667e78edcd8ad242a8558e0ff64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137255
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-18 01:39:20 -07:00
Deepak Nibade
10fae67c21 gpu: nvgpu: add flag for debugger fields in struct gk20a 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific fields in struct
gk20a

Jira NVGPU-3506

Change-Id: Icfae87e16e0079a2c5f16714b8a8ced7c6572cd4
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137254
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-18 01:39:10 -07:00
Deepak Nibade
67350e2c9c gpu: nvgpu: add flags to debugger specific headers 
Add debugger/cyclestats/fecs_trace compile time flags to debugger
specific unit headers

Jira NVGPU-3506

Change-Id: Iedea5f274243a389dce91edecbc80c58753d4805
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137253
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-18 01:38:54 -07:00
Deepak Nibade
27a133aa4c gpu: nvgpu: add debugger flag for common.hal.ltc unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.hal.ltc unit

Jira NVGPU-3506

Change-Id: I7a330cc60ea90e6b76bd1f783bcecd649032e279
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137251
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-18 01:38:28 -07:00
Rajesh Devaraj
ab70c2e80f gpu: nvgpu: report class/method related errors 
This patch adds support to report class/method related errors to 3LSS.
Specifically, it adds the following service ID:
NVGUARD_SERVICE_IGPU_PGRAPH_SWERR_ILLEGAL_ERROR

JIRA NVGPU-3458
JIRA NVGPU-3461

Change-Id: I9b28ed3074f664254347e059ac699470f95610b3
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2136301
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-18 01:37:43 -07:00
Divya Singhatwaria
8948c91719 gpu: nvgpu: Fix MISRA violations in PMU unit 
- Rule 17.7 states that the value returned by a
  function having non-void return type shall be
  used.
- Add NVGPU_FEATURE_LS_PMU to compile out headers
  in pmu_gv11b.h to fix MISRA violation 8.6

JIRA NVGPU-3570

Change-Id: I6ab104aa72d8fd6419bd336c45e9055a40ba5a7e
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131420
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-14 09:06:06 -07:00
Abdul Salam
7e8d0c2bb1 gpu: nvgpu: Move from TSENSE to TSOSC for TU104 
In TU104 tsense is not calibrated and tsosc needs to be used.
Tsosc is the POR for TU104.
This patch does the following
Remove the GP106 related thermal header and Add TU104 therm.
Rename the files from therm_gp106 to therm_tu104.
Update the debug fs interface to reflect the same.
Update the yaml files.

Bug 200526122

Change-Id: I73fd7d4c516426b5c6b84762480be2d6d572d5a7
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135139
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 23:05:43 -07:00
Seshendra Gadagottu
344eceb739 gpu: nvgpu: fix CERT-C issues in ltc intr driver 
Use nvgpu_safe_add_u32 for u32 additions in ltc interrupt
driver.

JIRA NVGPU-3623

Change-Id: If4d1b126836c5980e7016ed42b588b435f4f7f66
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135322
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 13:15:27 -07:00
Vinod G
c85d4c9e7f gpu: nvgpu: remove ZBC_STENCIL support for safety build 
Add CONFIG_NVGPU_GRAPHICS flag to enable the NVGPU_SUPPORT_ZBC_STENCIL
support.

Jira NVGPU-3580

Change-Id: I630430d5f2cca4a1230bdfe99e46346573030232
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135369
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:07:22 -07:00
Deepak Nibade
a3d30adab2 gpu: nvgpu: add debugger flag for fb units 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.hal.fb unit

Jira NVGPU-3506

Change-Id: If459e623e73ce716088d9cb92c31864c26fe0d3d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132260
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:06:30 -07:00
Deepak Nibade
1112af9f8c gpu: nvgpu: add flag for global fecs trace buffer index 
Add compile time flag check CONFIG_NVGPU_FECS_TRACE for
NVGPU_GR_GLOBAL_CTX_FECS_TRACE_BUFFER

Also add the flag check for setting NVGPU_FECS_TRACE_* characteristics
flag

Jira NVGPU-3506

Change-Id: I57f1538c852834b9be075a7b56b79fd699c04024
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132259
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:06:14 -07:00
Deepak Nibade
436549b9bf gpu: nvgpu: add cilp flag for CILP support 
Add CONFIG_NVGPU_CILP flag for CILP support across all the units

Jira NVGPU-3506

Change-Id: I0c71d38f9db6f00599a5070a8cb9d75d5b5fc351
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132258
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:59 -07:00
Deepak Nibade
1239bf67a5 gpu: nvgpu: add debugger flag for hal.gr.ctxsw_prog unit 
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
hal.gr.ctxsw_prog unit
Also add this flag for PM context allocation/free

Jira NVGPU-3506

Change-Id: Ib40569c7617b8b8aa3343fc89f3d8f30b1d21aa6
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132254
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 12:05:14 -07:00
Sagar Kamble
556ddaf9a3 gpu: nvgpu: add support for removing comptags and cbc from safety build 
Safety build does not support compression. This patch adds support to
compile out compression related changes - comptags, cbc.

JIRA NVGPU-3532

Change-Id: I20e4ca7df46ceec175b903a6a62dff141140e787
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 10:55:27 -07:00
Deepak Nibade
840972c1cc gpu: nvgpu: update TU104 regops whitelist 
List of whitelisted registers is auto generated with script

Bug 200526741

Change-Id: I097f4638ce9c1498ae09cfea2dbc7386fc5e0004
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135669
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 09:35:55 -07:00
Abdul Salam
ebeeec68ed gpu: nvgpu: Add support to query dgpu max freq 
Implement get_maxrate for TU104.
This function will use the clk_arb to get the P0 Max from VBIOS.

Bug 2610308

Change-Id: I09c692676bf949f300c9edd00f4faa26118b124f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133427
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-13 07:39:59 -07:00
Vinod G
a9fce07d11 gpu: nvgpu: Fix MISRA 13.2 errors in hal.gr.intr 
Fix MISRA 13.2 errors in hal.gr.intr unit.
misra_c_2012_rule_13_2_voilation: In hi32_lo32_to_u64, two function
calls in the arguments for which the order of evaluation is undefined.

Jira NVGPU-3621

Change-Id: I2c0d9a4492068f13edfb6ac6309f8679d1fbcee4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134597
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 16:17:06 -07:00
Seshendra Gadagottu
d17b2b9622 gpu: nvgpu: fix CERT INT30-C in hal.gr.falcon 
Fixed CERT C error with following lines by using nvgpu_safe_add_u32:
tag++; --> tag = nvgpu_safe_add_u32(tag, 1U);

Fixed CERT C error with following lines by nvgpu_gr_checksum_u32:
checksum += ucode_u32_data[i]; -->
		checksum = nvgpu_gr_checksum_u32(checksum, ucode_u32_data[i]);

JIRA NVGPU-3622

Change-Id: Id8808365990033e3527605b989b63a4f6d2826f9
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132548
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 16:16:33 -07:00
Philip Elcan
d388e45d98 gpu: nvgpu: mm: fix CERT-C INT30 violations in mmu_fault 
Fix CERT-C INT30 violations in mmu_fault_gv11b.c. INT30 requires
checking for wrap when doing unsigned arithmetic. Use safe ops and
asserts to comply.

JIRA NVGPU-3628

Change-Id: I7f5024d1e95784e0ff3702c8da20e54233df468c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133799
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 14:17:05 -07:00
Philip Elcan
8f25fe41e2 gpu: nvgpu: mm: fix CERT-C STR30 violation in mmu_fault 
Fix CERT-C Rule STR30 violation for assigning string literal to
non-const pointer by changing the declaration.

JIRA NVGPU-3628

Change-Id: I804cf2e02c40b934a1575faa68a0cc3849927699
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133798
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 14:16:50 -07:00
Seshendra Gadagottu
bf68ff68f0 gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver 
Fixed CERT-C issues in hal ltc intr driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I80c3dd9e42dd20bb853db6e60d6a1fd36415ab36
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134686
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 05:08:29 -07:00
Seshendra Gadagottu
330bf3ac2a gpu: nvgpu: fix CERT-C errors in hal ltc driver 
Fixed CERT-C issues in hal ltc driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I05c9cf202b46c39997e77d006ac5930f5cee9cd7
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134685
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-12 05:08:19 -07:00
Alex Waterman
57cee55ce7 Revert "gpu: nvgpu: fix CERT-C errors in hal ltc driver" 
This reverts commit 98f27acf08.

Second part of the series of changes that went in and caused problems
for GVS.

Change-Id: I47e65195d2f4dcbc07f429db77a5c45190693adf
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134478
 2019-06-11 10:50:18 -07:00
Alex Waterman
9d00bea358 Revert "gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver" 
This reverts commit bf861813b7.

This seems to cause a unit test failure in GVS due to a missing channel
test run.

Change-Id: I8609ebf8862a9641b015a7a2c0693e58312ef31d
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134477
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
 2019-06-11 10:50:00 -07:00
Vinod G
a6b1725b04 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.intr unit 
Fix CERT INT30-C erros in hal.gr.intr unit.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: If806b0e9e54c118dba6808a9c73ff107797d3ee0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134074
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:48:04 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags 
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 09:46:24 -07:00
Vinod G
c3c541b1af gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.ecc unit 
Fix CERT INT30-C erros in hal.gr.ecc units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I3811bfe0c542e7960ab8dbc2877465f7a72d1761
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133803
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:05:57 -07:00
Vinod G
fb0e627a25 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.config unit 
Fix CERT INT30-C erros in hal.gr.config units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I67f4df491194f1c5fdb369956f8238cd64cb85f1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132651
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 05:05:30 -07:00
Seshendra Gadagottu
bf861813b7 gpu: nvgpu: fix CERT-C errors in hal.ltc.intr driver 
Fixed CERT-C issues in hal ltc intr driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I4203e7bdd02c41578cad8446f02247749c8cef5c
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133291
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 03:55:33 -07:00
Seshendra Gadagottu
98f27acf08 gpu: nvgpu: fix CERT-C errors in hal ltc driver 
Fixed CERT-C issues in hal ltc driver by replacing
arithmetic operations with nvgpu safe ops.

JIRA NVGPU-3623

Change-Id: I0c6840ac1ee174c509e14e18e89cbacb0fdb650b
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133290
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-11 03:55:25 -07:00
Vinod G
f4b8feccf5 gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.init unit 
Fix CERT INT30-C erros in hal.gr.init units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I1c825decfbfba52136aef55c791e3d328a3470a2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132617
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-10 11:34:47 -07:00
Deepak Nibade
649a2b57a8 gpu: nvgpu: add debugger flag for hal.gr.gr unit 
Add NVGPU_DEBUGGER flag for common.hal.gr.gr unit and corresponding
hals.

Also add this flag for deferred reset functionality

Jira NVGPU-3506

Change-Id: Iee4fbc1305346bb4d779cd69e8fd5539cb07206b
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130149
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:44 -07:00
Deepak Nibade
d315f2a7e2 gpu: nvgpu: add debugger flag for perf units 
Add NVGPU_DEBUGGER flag for common.gr.perfbuf and common.hal.gr.perf
units

Jira NVGPU-3505

Change-Id: Ic01324304114e3fbaf018fd3bd892ccaa655b9ae
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:29 -07:00
Deepak Nibade
c5f5eb896c gpu: nvgpu: add debugger flag for hwpm_map units 
Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and
common.hal.gr.hwpm_map units

Jira NVGPU-3505

Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:28:14 -07:00
Deepak Nibade
455b0da253 gpu: nvgpu: add debugger flag for regops support 
Add NVGPU_DEBUGGER flag for regops API and hals

Jira NVGPU-3505

Change-Id: I9f2b850c881bf05f8ba5b6ef1f59f0d73a948cde
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130146
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 16:27:58 -07:00
Mahantesh Kumbar
b691df5a02 gpu: nvgpu: compile out PMU members & headers for safety 
-compile out nvgpu_pmu members which are not required for
safety buid & modified source as required to support same.
-compile out PMU headers include which are not required for
safety code
-Removed unnecessary PMU header includes from some files

JIRA NVGPU-3418

Change-Id: I5364b1b16c46637d229e82745dd2846cb6335a72
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128228
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-06 06:55:58 -07:00
Vinod G
20b974e724 gpu: nvgpu: Add flag to rop_mapping hal function 
Add NVGPU_GRAPHICS flag to support the rop_mapping hal function and
files which refer this function.
Use only when this flag is defined.

Jira NVGPU-3584

Change-Id: I49b10bb772306ba20004b3836596ea43cf0e1775
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130649
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 22:56:21 -07:00
Thomas Fleury
97762279b7 gpu: nvgpu: make nvgpu_init_mutex return void 
Make the nvgpu_init_mutex function return void.
In linux case, this doesn't affect anything since mutex_init
returns void.
For posix, we assert() and die if pthread_mutex_init fails.

This alleviates the need to error inject for _every_
nvgpu_mutex_init function in the driver.

Jira NVGPU-3476

Change-Id: Ibc801116dc82cdfcedcba2c352785f2640b7d54f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130538
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-05 10:25:52 -07:00
Sagar Kamble
13a7ef2cc7 gpu: nvgpu: handle falcon copy pointer alignment for misra 11.3 deviation 
Function for copying to/form IMEM/DMEM cast pointer to char to
pointer to u32 since falcon data registers are read/written in
4-bytes. Firmware data is generally byte stream and hence we
won't be able to deal in pointer to u32. Hence we need deviate
from misra rule 11.3.
Firmware data is also not aligned at word boundary sometimes
hence we need to copy it byte by byte to conform to the dev-
iation recommendation.

Error: MISRA C-2012 Rule 11.3: ./hal/falcon/falcon_gk20a.c:296:
misra_violation: The object pointer expression "src" of type
"u8 *" is cast to type "u32 *".

JIRA NVGPU-3271

Change-Id: Ic081f97226dbbcf08402970829624933402066eb
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108547
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 21:25:32 -07:00
Seshendra Gadagottu
60e3d135de gpu: nvgpu: add engine valid check before reading engine status 
Before reading engine_status_info, check for NVGPU_INVALID_ENG_ID to
avoid invalid hardware register access.

JIRA NVGPU-3520

Change-Id: I406474b36c9176ce825865ada8ea999a4f9b278e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128742
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 17:55:11 -07:00
Vinod G
9b163a0611 gpu: nvgpu: Fix CERT INT30-C errors in gr.intr unit 
Fix CERT INT30-C errors in gr.intr unit.
Use safe_ops functions nvgpu_safe_mult_u32 and
nvgpu_safe_cast_u32_to_s32 for multiplication and casting operations.

Jira NVGPU-3412

Change-Id: Ief3d1fe39ace9ba49eb839c823179ef82bacd85f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129768
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 16:47:10 -07:00
Deepak Nibade
d16ddb244f gpu: nvgpu: remove g->ops.gr.halt_pipe hal 
Hal API g->ops.gr.halt_pipe() is defined in unsafe unit hal.gr.gr
It is called from safe unit, and it calls into API
g->ops.gr.falcon.ctrl_ctxsw() which is also safe

Hence get rid of unsafe API g->ops.gr.halt_pipe().
Caller now directly calls hal.gr.falcon API to halt pipe

Jira NVGPU-3506

Change-Id: I5439cb79431795fc7c22384832cf632d6db03316
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127755
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 04:15:41 -07:00
Deepak Nibade
0908547ad2 gpu: nvgpu: move some interrupt hals to hal.gr.intr unit 
Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below

g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()

Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit

All of above functions and hals will be needed in safety build

Jira NVGPU-3506

Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-03 04:15:23 -07:00
Prateek Sethi
bf5f86b354 gpu: nvgpu: fix boot time process crash 
In poweron sequence the mc interrupts are being enabled before
initializing ecc support. That means ecc handler can be triggered
if there is ecc error occur and can cause Segmentation Fault.

To fix this issue adding a check in tu104_fbpa_handle_ecc_intr()

Bug 2540926

Change-Id: I277a8946d797bfcaac353d27f4eadf0c7ebbadfa
Signed-off-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125568
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-02 21:04:20 -07:00
Thomas Fleury
a1248d87fe gpu: nvgpu: add refcounting for MMU debug mode 
GPC MMU debug mode should be set if at least one channel
in the TSG has requested it. Add refcounting for MMU debug
mode, to make sure debug mode is disabled only when no
channel in the TSG is using it.

Bug 2515097

Change-Id: Ic5530f93523a9ec2cd3bfebc97adf7b7000531e0
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123017
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-06-01 06:36:14 -07:00
Seema Khowala
1e7405a5dc gpu: nvgpu: Add NVGPU_FEATURE_CHANNEL_TSG_CONTROL compiler flag 
This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id

JIRA NVGPU-3516

Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 16:55:43 -07:00
Vinod G
61fb688f1a gpu: nvgpu: Add flag checking for ZCULL code 
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes.
Define NVGPU_GRAPHICS flag for ZCULL support.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ifd571a5e64e8fb2dfe02a87458a2986681900a6b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127515
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-31 04:08:11 -07:00