This patch does the following:
(1) Removes the usage of hw headers in SDL unit. For this purpose, it moves
the initialization required for errors that can be injected using hw
support, error injection function. Further, it passes the required
information to SDL via hal layers.
(2) Renames (i) PWR as PMU, (ii) nvgpu_report_ecc_parity_err to
nvgpu_report_ecc_err.
Jira NVGPU-3235
Change-Id: I69290af78c09fbb5b792058e7bc6cc8b6ba340c9
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112837
Reviewed-by: Raghuram Kothakota <rkothakota@nvidia.com>
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renamed NVGPU_LS_PMU to NVGPU_FEATURE_LS_PMU to follow
nvgpu naming standard
Compile out LS PMU files when PMU RTOS support is
disabled for safety build by setting NVGPU_LS_PMU
build flag to 0
JIRA NVGPU-3418
Change-Id: Ib09924ac25657e932723c10be573f2f701cb7bea
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127794
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Compile out PMU RTOS specific PMU HAL code when
PMU RTOS support is disabled for safety build by setting
NVGPU_LS_PMU build flag to 0
Added new functions for gv11b PMU HAL to easy compile out
other PMU HAL files.
Replaced all gk20a_writel/readl calls with nvgpu_writel/readl
calls in hal/pmu/pmu_gv11b.c files
JIRA NVGPU-3418
Change-Id: I7c315349aa95721990dc7b1570383669bcb6221f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117691
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pmu_gk20a.c includes hw_mc_gk20a.h other than hw_pwr_gk20a.h
to access & configure pmu interrupt, this breaks single hw header
for HAL file.
Moved PMU interrupt enable to MC unit by creating/modifying current
mc ops intr_unit_config to intr_pmu_unit_config to configure PMU
interrupt specifically as this ops is only used by PMU unit
JIRA NVGPU-3239
Change-Id: I2514f17197708047b46ea712cf4569a5b3bfab2a
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126420
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This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.
Jira NVGPU-3237
Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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PG189 has multiple sensors which can provide interrupt when board
temperature reaches programmed threshold.
This Interrupt is implemented in nvgpu and provide events via clk_arb.
Support is enabled for TU104 with NVGPU_SUPPORT_DGPU_THERMAL_ALERT flag.
Board specific config is added in DT which will be parsed by nvgpu.
Nvgpu does the following.
1.Read gpio line number, interrupt type, and event delay from DT.
2.Call kernel methods and register the interrupt with kernel.
3.Create work queue which will process the interrupt in process context.
4.When interrupt occurs disable interrupt, add work to work queue.
5.In work queue post events and sleep for delay time then enable
Interrupt
Bug 2492512
Change-Id: Ic5694fe366ca492f8afe8a67de4350e9a51af2af
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119411
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
.init = gv100_bios_init,
.preos_wait_for_halt = gv100_bios_preos_wait_for_halt,
.preos_reload_check = gv100_bios_preos_reload_check,
.devinit = gp106_bios_devinit,
.preos = gp106_bios_preos,
.verify_devinit = NULL,
This was being called as:
g->ops.bios.init(g)
g->ops.bios.preos_wait_for_halt(g)
g->ops.bios.preos_reload_check(g)
g->ops.bios.preos(g)
g->ops.bios.devinit(g)
g->ops.bios.verify_devinit(g)
Change the function access by using sw ops, like:
Create new function: nvgpu_bios_sw_init()
and based on hardware chip call the chip specific
bios sw init function: nvgpu_gv100_bios_sw_init()
and nvgpu_tu104_bios_sw_init()to assign the sw
ops
JIRA NVGPU-2071
Change-Id: Ibfcd9b225a7bc184737abdd94c2e54190fcd90a0
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108526
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Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
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The HS ucode runs on PMU with all interrupts disabled. So it will not be
able to detect any data corruption introduced in the IMEM or DMEM due to bit
flips. In order to mitigate this issue validate the integrity of IMEM and DMEM
at the end of HS ucode bootstrap and fail the boot incase of any un-corrected
errors.
Jira NVGPU-3555
Change-Id: Icd9a2bf2c29470629be8524c9b99f90e3036abdc
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2124107
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pbdma fault recovery function reads pbdma status info to retrieve
channel id, tsg id and engine id. pbdma interrupts can only be cleared
after that information has been read otherwise because pbdma exits
from stall state, channel/tsg/engine could have changed and fault
recovery function reads information different from that when interrupt
is issued.
Bug 2123866
Change-Id: Ia0e0462ae02ec89a333c81bd933a74fbae8ae1e7
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2123774
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Since dGPU support is not required for initial safety release, compile
out dGPU sw and hal implementations except below files that are used
by gv11b currently: acr_sw_gv100.c, engine_status_gv100.c, gr_gv100.c
gr_config_gv100.c and hwpm_map_gv100.c.
JIRA NVGPU-3062
Change-Id: I8a6bc8b235e7e5eac5b0e76147b8bd12f9abbd2d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119586
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Since nvlink support is not required for initial safety release, disable
corresponding functionality.
nvgpu_mss_nvlink_init_credits defn. and call is now compiled out using
CONFIG_TEGRA_NVLINK config option.
JIRA NVGPU-3062
Change-Id: I402ed123f07f96125d640fb340957da4828d714a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119584
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Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Fix Misra rule 20.7: Macro parameter expands into an expression without being
wrapped by parentheses.
- Following two macros has been updated to fix the above violation,
HZ_TO_MHZ_ULL and MHZ_TO_HZ_ULL.
Jira NVGPU-3176
Change-Id: I03f7d8f7d5c91ca33fcc594fed0359d5c62eea6b
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120192
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Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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Renamed gk20a_channel_* APIs to nvgpu_channel_* APIs.
Removed unused channel API int gk20a_wait_channel_idle
Renamed nvgpu_channel_free_usermode_buffers in os/linux-channel.c to
nvgpu_os_channel_free_usermode_buffers to avoid conflicts with the API
with the same name in channel unit.
Jira NVGPU-3248
Change-Id: I21379bd79e64da7e987ddaf5d19ff3804348acca
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2121902
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Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:281:
cert_violation: Casting "ts >> 32" from "unsigned long long" to
"unsigned int" without checking its value may result in lost
or misinterpreted data.
Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:186:
cert_violation: Casting "enable" from "bool" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3410
Change-Id: I4879c8e09d8498bb2377b166035ae0e79adf8870
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119397
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NV_PGPC_PRI_MMU_DEBUG_CTRL is now context switched in gv11b
FECS ucode. Enable NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, so that
userspace can use NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE
ioctl for gv11b.
Bug 2515097
Change-Id: Ia9fb36cffc9e67cf96c31c50ffa4c59997258ce2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115019
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MISRA rule 13.5 doesn't allow right-hand operand of logical && or ||
operator to have persistent side effects. The reason is right-hand
operand is executed or checked depending on the left-hand operand value.
That means side effects in the right-hand operand may or may not occur,
contrary to programmer's expectation. Hence, this rule is implemented to
avoid unexpected behavior.
This patch divides if condition with logical && operator to nested if
conditions to resolve this violation.
Jira NVGPU-3277
Change-Id: I9f4387d71427821278db6bbda2eb53bd4d8ea543
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119684
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
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