(!c->deterministic) ||
(nvgpu_is_enabled(g, NVGPU_CAN_RAILGATE) && !c->deterministic)
is equivalent to
(!c->deterministic)
Remove second condition in nvgpu_submit_channel_gpfifo
Jira NVGPU-3384
Change-Id: Icf3e460d4fe9d310d94a21895832bbfae595df28
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111610
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This reverts commit e9a6d179a4 ("gpu: nvgpu: cache gpu clk rate")
- Real clock rate doesn't always equal clock rate requested by caller
- call of clk_set_rate() and update of cached_rate are not atomic
- Real root cause for Bug 2051688 is in bpmp and gboost design
Bug 2538692
Change-Id: I9248e0c69e2271ed2d0070587db59afa6f8160f2
Signed-off-by: Peng Liu <pengliu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109708
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA rule 21.3 forbids from using calloc, malloc, realloc and free
identifiers for function or macro names. This patch renames nvgpu
allocator free operator to free_alloc to follow rule 21.3.
Jira NVGPU-3336
Change-Id: Ie9f48d567255a3e1dca70632fbe3d36b45023f3f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111365
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Below 5.7 violations are reported in common.gr.config unit :
nvgpu/drivers/gpu/nvgpu/common/gr/gr_config.c:628:
identifier_reuse: Identifier "sm_info" is already used to represent a type.
Fix them by renaming struct sm_info to struct nvgpu_sm_info
Jira NVGPU-3225
Change-Id: I26f70a4ed2a5a845e0dc9daeb8fb5474e35d42fb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110986
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MISRA rule 2.2 doesn't allow unused functions and assignments in code.
The reason is presence of unused functions or variable assignments may
indicate error in program's logic. This patch removes an unused function
following rule 2.2.
Jira NVGPU-858
Change-Id: I80b4ae3486038de1a9b1c3afc3b4f17f18cc9efd
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111616
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore. Fix the violations of MISRA rule 21.2 in atomic unit.
Jira NVGPU-3139
Change-Id: I4fbed30542bdd2a2444a5619b5bb2bb5c7736472
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111441
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix for MISRA error Rule 14.2
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.
Jira NVGPU-3227
Change-Id: Ia46d8c9a8fb99f9e49be2eb56cabef6947c5b44b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111678
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
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nvgpu_list_for_each_entry_safe violates MISRA Rule 14.2, as
it uses comma separator in the for clauses. Use a while loop
instead in nvgpu_tsg_release, as we want to empty the list.
Jira NVGPU-3380
Change-Id: I38211cc326e458d0912f374e3692328fb4e9b191
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111383
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Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.
JIRA NVGPU-2042
JIRA NVGPU-1313
Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
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Fix MISRA 5.3 violation for hiding the variable "ret."
Fix MISRA 10.1 violation in the NVGPU_COND_WAIT() macro. The timeout
value was being used as a boolean for the ? operator. Compare to 0
instead.
Fix MISRA 14.3 violation for invariant condition.
Fix MISRA 14.4 violation for using 0 for a boolean in the while
condition.
JIRA NVGPU-3329
Change-Id: I874aa66abb8771f9855ba4312ea068603d5b2e7b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109471
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix MISRA error for Rule 14.3
The switch governing value "offset" cannot reach the default case.
Execution cannot reach this statement "default:".
Change switch statement with if else checking
Jira NVGPU-3227
Change-Id: Ib1ccfe2d3bef94ffaf3e0f963bc21260844d0c91
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110759
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Fix for MISRA Rule 14.2.
Using a comma operator in the first clause of the for loop.
The first clause should either be empty or assign a value to the loop counter.
Don't update the loop counter within the loop body.
Jira NVGPU-3227
Change-Id: I6bee94c0ce7198d6ff4e465e2e0d982d3d358161
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110758
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MISRA rule 10.4 prohibits operator operands having different essential
type. The POSIX ffs() and fls() implementations were subtracting a
signed value of 1 from a unsigned long. The 1 is updated to be 1ULL to
fix the violation.
JIRA NVGPU-3337
Change-Id: I57d64705a3069c05c02635f4dd70902e96046d7d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109645
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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Create a new unit for pramin. This is used for handling the HAL init for
pramin. Move the setup of the pramin gops for to the new pramin HAL.
This eliminates the need for the nvgpu.common.hal.init unit from having
to include the HW header file for pramin.
JIRA NVGPU-3274
Change-Id: I4e2402cf3e4eeb53e0fa5b6428624f8f3668fcd0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108805
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Currently, bitmap allocator reuses identifier "nvgpu_bitmap_alloc" for
an allocation function and as bitmap rbtree node struct. Renaming the
allocation function to "nvgpu_bitmap_balloc". Also, renaming fixed
allocation function to "nvgpu_bitmap_balloc_fixed" for consistency.
Jira NVGPU-3335
Change-Id: I6fe616db5137b2d4e2795a84ae5eafd527f0dba5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110714
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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MISRA 20.7 rule requires macro paramaters to be wrapped in
parantheses when the parameter expands into an expression.
Fix the MISRA rule 20.7 violation in posix cond unit.
Jira NVGPU-3139
Change-Id: Iae1f90a905e73cc0b3104ccab98bcabc81605452
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110264
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
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