Commit Graph

17 Commits

Author SHA1 Message Date
Deepak Nibade
96dc116eed gpu: nvgpu: support context creation for specific GR instance
Get current GR instance pointer with nvgpu_gr_get_cur_instance_ptr() in
nvgpu_gr_setup_alloc_obj_ctx() and update all the code in this function
to use this GR instance pointer instead of globally accessing g->gr->*
data structures.

Add lots of GR engine specific debug prints in context creation path.

Jira NVGPU-5648

Change-Id: Ia8681d115ee88c5848621854f23e1cce4ff3deb2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2415239
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Reviewed-by: Lakshmanan M <lm@nvidia.com>
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2020-12-15 14:13:28 -06:00
Lakshmanan M
aef3367ca5 gpu: nvgpu: Add multi GR gr_config utilty support
This CL covers the following code changes,
1) Added api to get the gr_config per gr_instance_id basis.
2) Added api to covert from gpu_instance_id to gr_instance_id.
3) Modified nvgpu_gr_exec_with_ret_for_instance() utility to handle
   generic data return type.

JIRA NVGPU-5662
JIRA NVGPU-5663

Change-Id: I4ab732e15cdbda25672975f99e23b5e5d27decb0
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413195
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2020-12-15 14:13:28 -06:00
Deepak Nibade
ebb66b5d50 gpu: nvgpu: add macros to get current GR instance
Add macros to get current GR instance id and the pointer
nvgpu_gr_get_cur_instance_ptr()
nvgpu_gr_get_cur_instance_id()

This approach makes sure that the caller is getting GR instance pointer
under mutex g->mig.gr_syspipe_lock in MIG mode. Trying to access
current GR instance outside of this lock in MIG mode dumps a warning.

Return 0th instance in case MIG mode is disabled.

Use these macros in nvgpu instead of direct reference to
g->mig.cur_gr_instance.

Store instance id in struct nvgpu_gr. This is to retrieve GR instance
id in functions where struct nvgpu_gr pointer is already available.

Jira NVGPU-5648

Change-Id: Ibfef6a22371bfdccfdc2a7d636b0a3e8d0eff6d9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2413140
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2020-12-15 14:13:28 -06:00
Deepak Nibade
bafeea3530 gpu: nvgpu: setup HW for each GR instance
Get number of SMs from GR instance specific nvgpu_gr_config pointer
instead of global SM count in below functions :
nvgpu_gr_fs_state_init()
gv11b_gr_init_sm_id_config()

Update nvgpu_gr_config_get_gpc_skip_mask() to return 0 in case gpc_index
is greater than available gpc_count. This is not MIG specific, but based
on code review possible even today for existing chips.
See gm20b_gr_init_pd_skip_table_gpc()

Update nvgpu_gr_get_override_ecc_val() to return GR instance specific
value.

Execute gr_init_setup_hw() for each GR instance.

Disable below failing unit tests:
nvgpu_gr_fs_state.test_gr_fs_state_error_injection
nvgpu_gr_init.test_gr_init_hal_config_error_injection

Jira NVGPU-5648

Change-Id: Ie8f1c0c304c634756786d85facf336a5c9ae8195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2410702
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2020-12-15 14:13:28 -06:00
Deepak Nibade
8d2cb311cb gpu: nvgpu: return current GR instance pointers
Update below APIs to return current GR instance specific pointers
instead of 0th instance specific pointers

nvgpu_gr_get_falcon_ptr()
nvgpu_gr_get_config_ptr()
nvgpu_gr_get_intr_ptr()

Jira NVGPU-5648

Change-Id: Id9608fb40a1f23ec3466cb205002c10b40d08876
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2409534
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2020-12-15 14:13:28 -06:00
Deepak Nibade
cfa360f5b8 gpu: nvgpu: allocate struct nvgpu_gr based on enumerated gr count
Add new API nvgpu_grmgr_get_num_gr_instances() that returns number of
GR instance enumerated by GR manager. This just returns number of sys
pipes enabled since it is same as number of GR instances.

For consistency until common.gr supports multiple GR instances
completely, add a temporary macro NVGPU_GR_NUM_INSTANCES and set it
to 1. If this macro is changed to 0 (for local MIG testing), fall
back to use nvgpu_grmgr_get_num_gr_instances() to get enumerated number
of GR instances.

Use a for loop to initialize other variables of struct nvgpu_gr.

Remove unnecessary NULL check in nvgpu_gr_alloc() since struct gk20a
pointer can never be NULL in this path. Also remove corresponding unit
test code.

Jira NVGPU-5648

Change-Id: Id151d634a23235381229044f2a9af89e390886f2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2400151
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2020-12-15 14:13:28 -06:00
Deepak Nibade
a5f722a5ff gpu: nvgpu: doxygen for gr/gr_utils.h
Add doxygen documentation for gr/gr_utils.h header

Also move nvgpu_gr_checksum_u32() to gr_utils.c instead of declaring
it static inline in header file.

Jira NVGPU-4028

Change-Id: I383e06582b45ad50eef4b505ed8c57fb6620dff9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199508
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2020-12-15 14:05:52 -06:00
Deepak Nibade
6849526d7f gpu: nvgpu: compile out ECC feature override in safety
Overriding of ECC feature is used only in Linux through device
tree fuse overrides. It's not supported in QNX. Hence compile
out below functions from safety build.

nvgpu_gr_get_override_ecc_val()
nvgpu_gr_override_ecc_val()

Move nvgpu_gr_get_golden_image_ptr() under CONFIG_NVGPU_DEBUGGER

Re-arrange all functions in gr_utils.c/h and move all non-safe
functions towards end of file.

Jira NVGPU-4028

Change-Id: Ie56fcf78c32a9b23d2e5f5b51701c5f8ccad62ec
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2199507
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2020-12-15 14:05:52 -06:00
Deepak Nibade
436549b9bf gpu: nvgpu: add cilp flag for CILP support
Add CONFIG_NVGPU_CILP flag for CILP support across all the units

Jira NVGPU-3506

Change-Id: I0c71d38f9db6f00599a5070a8cb9d75d5b5fc351
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132258
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2019-06-13 12:05:59 -07:00
Deepak Nibade
4ac27a24bb gpu: nvgpu: add debugger flag for gr.utils unit
Add CONFIG_NVGPU_DEBUGGER flag for debugger specific code in
common.gr.utils unit.

Jira NVGPU-3506

Change-Id: Iea551df287e06602949b3c2c33ebe565f0a0c921
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132257
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2019-06-13 12:05:44 -07:00
Sagar Kamble
3f08cf8a48 gpu: nvgpu: rename feature Make and C flags
Name the Make and C flag variables consistently wih syntax:
CONFIG_NVGPU_<feature name>

s/NVGPU_DEBUGGER/CONFIG_NVGPU_DEBUGGER
s/NVGPU_CYCLESTATS/CONFIG_NVGPU_CYCLESTATS
s/NVGPU_USERD/CONFIG_NVGPU_USERD
s/NVGPU_CHANNEL_WDT/CONFIG_NVGPU_CHANNEL_WDT
s/NVGPU_FEATURE_CE/CONFIG_NVGPU_CE
s/NVGPU_GRAPHICS/CONFIG_NVGPU_GRAPHICS
s/NVGPU_ENGINE/CONFIG_NVGPU_FIFO_ENGINE_ACTIVITY
s/NVGPU_FEATURE_CHANNEL_TSG_SCHED/CONFIG_NVGPU_CHANNEL_TSG_SCHED
s/NVGPU_FEATURE_CHANNEL_TSG_CONTROL/CONFIG_NVGPU_CHANNEL_TSG_CONTROL
s/NVGPU_FEATURE_ENGINE_QUEUE/CONFIG_NVGPU_ENGINE_QUEUE
s/GK20A_CTXSW_TRACE/CONFIG_NVGPU_FECS_TRACE
s/IGPU_VIRT_SUPPORT/CONFIG_NVGPU_IGPU_VIRT
s/CONFIG_TEGRA_NVLINK/CONFIG_NVGPU_NVLINK
s/NVGPU_DGPU_SUPPORT/CONFIG_NVGPU_DGPU
s/NVGPU_VPR/CONFIG_NVGPU_VPR
s/NVGPU_REPLAYABLE_FAULT/CONFIG_NVGPU_REPLAYABLE_FAULT
s/NVGPU_FEATURE_LS_PMU/CONFIG_NVGPU_LS_PMU
s/NVGPU_FEATURE_POWER_PG/CONFIG_NVGPU_POWER_PG

JIRA NVGPU-3624

Change-Id: I8b2492b085095fc6ee95926d8f8c3929702a1773
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130290
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2019-06-11 09:46:24 -07:00
Deepak Nibade
c5f5eb896c gpu: nvgpu: add debugger flag for hwpm_map units
Add NVGPU_DEBUGGER flag for common.gr.hwpm_map and
common.hal.gr.hwpm_map units

Jira NVGPU-3505

Change-Id: I5c9b6f98c7a8f536f5a8492febaa6140ef2adb6f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130147
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2019-06-06 16:28:14 -07:00
Vinod G
61fb688f1a gpu: nvgpu: Add flag checking for ZCULL code
Add NVGPU_GRAPHICS flag checking for ZCULL specific codes.
Define NVGPU_GRAPHICS flag for ZCULL support.
This flag is disabled for safety build now.

Jira NVGPU-3550

Change-Id: Ifd571a5e64e8fb2dfe02a87458a2986681900a6b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127515
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2019-05-31 04:08:11 -07:00
Vinod G
4eb8663bd6 gpu: nvgpu: Add flag checking for ZBC support
Add NVGPU_GRAPHICS flag checking for ZBC specific codes.
This flag will be disabled for safety build later.

Jira NVGPU-3494

Change-Id: I0f6dc3ac61189fe398bf031e9021b341ff2a7b13
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127447
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2019-05-30 13:36:15 -07:00
Deepak Nibade
646b08a032 gpu: nvgpu: add flag for fecs trace support in rest of the units
Add CONFIG_GK20A_CTXSW_TRACE flag for fecs trace support in rest of
the units like common.gr.utils and common.hal.gr.ctxsw_prog

Jira NVGPU-3414

Change-Id: I8f56bc38defd49a5fc30f79a35047afa7db2ffdf
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2120277
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2019-05-20 15:46:30 -07:00
Vinod G
5c60645cfa gpu: nvgpu: gr_priv header include cleanup
Add more apis in gr_utils for accessing variables within gr struct.
This helps to avoid including gr_priv.h outside gr files and
derefencing gr struct.

Jira NVGPU-3218

Change-Id: I6f24cc302f10aa1da14a981d80c400a027c9a115
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115930
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2019-05-10 20:15:36 -07:00
Seshendra Gadagottu
21f04a94af gpu: nvgpu: avoid dereferencing gr in acr
Added utility function to get gr falcon pointer to avoid direct
de-referencing gr in acr.

struct nvgpu_gr_falcon *nvgpu_gr_get_falcon_ptr(struct gk20a *g);

JIRA NVGPU-3168

Change-Id: I8f05cdbcd5d3e52c585df54f93cf065685733e5d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114214
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2019-05-09 21:14:56 -07:00