once gpu is powered off i.e. power_on set to false, nvgpu isr
does not handle stall/nonstall irq. Depending upon state
of gpu, this can result in either of following errors:
1) irq 458: nobody cared (try booting with the "irqpoll" option)
2) "HSM ERROR 42, GPU" from SCE if it detects that an interrupt is
not in time.
Fix these by masking all interrupts just before gpu power off
as nvgpu won't be handling any irq anymore.
While masking interrupts, if there are any pending interrupts,
then report those with a log message.
Bug 1987855
Bug 200424832
Change-Id: I95b087f5c24d439e5da26c6e4fff74d8a525f291
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770802
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-Renamed "struct pmu_queue" to "struct
nvgpu_falcon_queue" & moved to falcon.h
-Renamed pmu_queue_* functions to flcn_queue_* &
moved to new file falcon_queue.c
-Created ops for queue functions in struct
nvgpu_falcon_queue to support different queue
types like DMEM/FB-Q.
-Created ops in nvgpu_falcon_engine_dependency_ops
to add engine specific queue functionality & assigned
correct HAL functions in hal*.c file.
-Made changes in dependent functions as needed to replace
struct pmu_queue & calling queue functions using
nvgpu_falcon_queue data structure.
-Replaced input param "struct nvgpu_pmu *pmu" with
"struct gk20a *g" for pmu ops pmu_queue_head/pmu_queue_tail
& also for functions gk20a_pmu_queue_head()/
gk20a_pmu_queue_tail().
-Made changes in nvgpu_pmu_queue_init() to use nvgpu_falcon_queue
for PMU queue.
-Modified Makefile to include falcon_queue.o
-Modified Makefile.sources to include falcon_queue.c
Change-Id: I956328f6631b7154267fd5a29eaa1826190d99d1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776070
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The use of the _THIS_IP_ macro in nvgpu introduces two separate
MISRA Rule 11.6 violations.
The first is when when the label address (which gcc generates as
a void *) is cast to an unsigned long and the second is when that
unsigned long is cast back to a void * in the timer and kmem code
that track the value.
Skipping the intermediate use of unsigned long eliminates these
violations. To do this, references to _THIS_IP_ are replaced
with a new (compliant) _NVGPU_GET_IP_ macro.
JIRA NVGPU-895 : MISRA Rule 11.6 violations
Change-Id: I5ea999d8e2b467257fa190b485fa971adcbd0a2b
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774531
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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MISRA Rule 11.6 prohibits the casting of an integer value to a
void *.
The nvgpu allocator used for the fence pool stores the base
address of the associated memory as a u64 and returns it via
nvgpu_alloc_base().
In gk20a_free_fence_pool() this u64 value was cast to a void *
before being passed to nvgpu_vfree() (leading to the violation).
This change modifies gk20a_free_fence_pool() to cast the base
address back to the original struct gk20a_fence * to eliminate
the violation.
JIRA NVGPU-895: MISRA Rule 11.6 violations
Change-Id: If89cf2c1bc8ea4b0b59da4cf8b1c167738f6badc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774530
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
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In the current code, gk20a.h includes io.h which gets directly included
in a lot of other files. io.h contains methods which uses a struct
gk20a as a parameter leading to a circular dependency between io.h
and gk20a.h. This can be mitigated by removing io.h from gk20a.h as
part of larger effort to moving gk20a.h to nvgpu/gk20a.h
JIRA NVGPU-597
Change-Id: I93e504fa9371b88152737b342a75580c65e8f712
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1787316
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-For Si platforms, gk20a_get_gr_idle_timeout returns
3000 ms i.e. 3 sec. Currently this time is used for
preempt polling and this conflicts with channel
timeout if polling times out. Use fifo_eng_timeout_us converted
to ms for preempt polling.
-In case of preempt timeout, do not issue recovery
for si platform. ctxsw timeout will trigger recovery
if needed. For non si platforms, issue preempt timeout rc
if preempt times out.
Bug 2113657
Bug 2064553
Bug 2038366
Bug 2028993
Bug 200426402
Change-Id: I8d9f58be9ac634e94defa92a20fb737bf256d841
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762076
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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-Recovery can be called for various types of faults. Acquire
runlist_lock for all runlists so that current teardown is done
before proceeding to next one.
-For legacy chips teardown is done by triggering mmu fault so
make sure runlist_locks are acquired during teardown and also
during handling mmu fault.
-gk20a_fifo_handle_mmu_fault is renamed as
gk20a_fifo_handle_mmu_fault_locked
-gk20a_fifo_handle_mmu_fault called from gk20a_fifo_teardown_ch_tsg
is replaced with gk20a_fifo_handle_mmu_fault_locked
-gk20a_fifo_handle_mmu_fault acquires/release runlist_lock for all
runlists and calls gk20a_fifo_handle_mmu_fault_locked
Bug 2113657
Bug 2064553
Bug 2038366
Bug 2028993
Change-Id: I973d7ddb6924b50bae2d095152867e99c87e780a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1761197
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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For IOCTL NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY, we do not allow size of buffer
which is not 4 byte aligned
Remove this hard restriction and allow non 4 byte aligned buffer sizes too
since we don't really need to enforce this restriction
Bug 2265535
Change-Id: Ic4d60604be3698e8629f2b289c9e2d19e20ea525
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1784511
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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In order to avoid the circular dependencies,
rearrange the static inline functions from
gk20a.h file.
Moved gk20a_gr_flush_channel_tlb function to
gr_gk20a.c and removed the #include gr_gk20a.h
from gk20a.h
Added a helper function utils.h to
move all generic static inline functions which
have no reference to gpu related structures.
ptimer related functions are moved to
ptimer.h
Implementations for as and pmu are moved to
corresponding files.
JIRA NVGPU-624
Change-Id: I4e956326e773ba037bf3a1696cc4c462085dbbe5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1781941
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Added debugfs node under ltc directory with name:
intr_illegal_compstat_enable
Enabling/disabling of ltc_illegal_compstat intr is
possible through debugfs node.
Since ltc state is lost with rail gate, this setting is
cached and will be populated during ltc initialization.
Bug 2099406
Change-Id: I4bf62228dfd2bbb94f87f923f9f4f6e5ad0b07f0
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774683
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Illegal compstat interrupt indicates an unexpected compression status
given the kind. Since dirty tile mappings expected to have discrepancies
in compbit state, so disabling illegal compstat interrupt.
Bug 2099406
Change-Id: I90207c6bc8a8cfa656ea9a0b4f5605106751c12e
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774572
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- adds static tpc-powergating through sysfs.
- active tpc count will remain till the GPU/systems is not booted again.
- tpc_pg_mask can be written only after GPU probe finishes and
GPU boot is triggered.
Note:
To be able to use this feature, we need to change boot/init
scripts of the OS(used with nvgpu driver) to write to sysfs nodes before
posting discover image size query to FECS.
Bug 200406784
Change-Id: Id749c7a617422c625f77d0c1a9aada2eb960c4d0
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742422
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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FB fault buffer is enabled on finalize poweron. Disable the buffer
in prepare poweroff. This also eliminates the need to disable
the buffer in fault info mem destroy which otherwise accesses
GPU registers after these are locked in prepare poweroff.
Bug 200427479
Change-Id: I1ca3e6ed4417847731c09b887134f215a2ba331c
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776387
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FB hub intr is enabled on finzalize_poweron and disabled on
prepare_poweroff. There is no need to additionally disable
FB hub intr in fault info mem destroy when driver refcount
becomes zero since prepare_poweroff has already been called.
Also prepare_poweroff locks GPU registers from CPU access so
these registers should not be accessed after prepare_poweroff.
Bug 200427479
Change-Id: I62c355502ea494a1d0528c8668cae63743b8957b
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776386
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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- create common file common/ecc.c which include common functions for add
ecc counters and remove counters.
- common code will create a list of all counter which make it easier to
iterate all counters.
- Add chip specific file for adding ecc counters.
- add linux specific file os/linux/ecc_sysfs.c to export counters to
sysfs.
- remove obsolete code
- MISRA violation for using snprintf is not solved, tracking with
jira NVGPU-859
Jira NVGPUT-115
Change-Id: I1905c43c5c9b2b131199807533dee8e63ddc12f4
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1763536
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-During teardown issue runlist preempt
-preempt_ch_tsg hal is removed as it is no more required.
This hal was added to be called from teardown so that if
there is preempt timeout, preempt timeout recovery is not
triggered.
Bug 200426402
Change-Id: I679e3306aa890ff0cfa211cfcc7d5405b7cb1211
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775443
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Since preempt timeout per pbdam/eng/runlist is set to
fifo_eng_timeout_us converted to ms, there could be a
scenario where preempt might time out. In case of preempt
time out, do not issue recovery for si platform.
ctxsw timeout will trigger recovery if needed. For non
si platforms, issue preempt timeout rc if preempt times out.
Bug 200426402
Change-Id: Ifd921280c0443ee9eda31157aaa03b481a529239
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775441
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This reverts commit 0b02c8589d.
Originally change was reverted as it was making ap_compute test on
embedded-qnx-hv e3550-t194 fail. With fixes related to replacing tsg
preempt with runlist preempt during teardown, preempt timeout set to
100 ms (earlier this was set to 1000ms for t194 and 3000ms for legacy
chips) and not issuing preempt timeout recovery if preempt fails, helped
resolve the issue.
Bug 200426402
Change-Id: If9a68d028a155075444cc1bdf411057e3388d48e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762563
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Moved gv11b_detect_ecc_enabled_units function
from gv11b.c to gr_gv11b.c, as this is being
used only in gr_gv11b file.
In order to avoid GR code touching fuse registers,
as it need to include fuse HW headers in GR code,
introduced two fuse HALs which are being called
from GR code. is_opt_ecc_enable for checking
whether ecc enable bit is set in fuse register
and is_opt_feature_overide_disable for checking
whether feature override disable bit is set in
fuse register.
Initialized fuse HAL functions for chips that
make use of those HAL functions.
JIRA NVGPU-615
Change-Id: Iafe5a3940bb19cb3da51e270403450b63c2f67a3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775564
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LTC register write is followed by a register read
and if data doesn't match code will report the error.
Renamed existing nvgpu_writel_check function as
nvgpu_writel_loop as it loops until the write get success.
nvgpu_writel_check function write and read back and
compare the data.
Bug 2039150
Change-Id: I0a49be36aad23936f2d58aa82872710827da1d32
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762344
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mm_gv11b.c has several direct calls to fb_gv11b.h. Redirect them to
go via a HAL. Also make sure the HALs are using parameter with
correct signedness and prefix the parameter constants with
NVGPU_FB_MMU_.
MMU buffer table indices were also defined in fb_gv11b.h, even though
the tables themselves are defined in include/nvgpu/mm.h. Move the
indices to include/nvgpu/mm.h and prefix them with NVGPU_MM_MMU_.
JIRA NVGPU-714
Change-Id: Ieeae7c5664b8f53f8313cfad0a771d14637caa08
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1776131
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Runtime PM is enabled only for iGPU and not for dGPU. For dGPU,
the .probe() of driver pm_runtime_disable()s, if rail-gating is
not enabled. With nvgpu kernel module load/unload, .probe() is
called multiple times for same struct device *. This results
in an overflow of disable_depth (3 bit refcount) and enables
runtime PM on 8th iteration and calls RTPM routines even if it's
disabled.
To effectively manage pm_runtime_disable(), move it from common
nvgpu_remove() to iGPU/dGPU specific routines.
Also, add restore pm_runtime state of device on driver .remove().
Bug 1987855
Change-Id: I781278da546ef9c9ef7d7da7dbea0757df32716f
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770804
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On nvgpu module unload, platform_driver_unregister() detaches
driver from device (driver_detach()). As part of this,
__device_release_driver() results a race between driver's
.runtime_resume(), .remove() and .runtime_suspend().
As nvgpu's .remove() is handling all steps of cleaning up
driver state and shutting down gpu, .runtime_suspend()
shall have no work. So skip .runtime_suspend() is gk20a *g
has already been processed.
Bug 1987855
Change-Id: I024ac63d321689ea04c64b1ffc125da943d482f9
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770803
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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This reverts commit 74d786dd13.
With the recent powergating changes that got merged in k4.14 and by
disabling CONFIG_PROVE_LOCKING, we no longer see any issues in T186.
The reboots observer earlier have stopped and the status of nvgpu_submit
and nvrm_gpu_tests remain the same without causing any more issues
Bug 200414723
Change-Id: Iea872612a233cb3d79df772a78fd6349c69323f2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1775199
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GK20A_DEVFREQ scaling depends on Nvidia downstream kernel
modifications to PM QoS framework. To break that dependency and to
allow devfreq based scaling to work without those changes, introduce a
Kconfig option to conditionally enable the PM Qos based constraints.
Bug 200414723
Bug 200414600
Change-Id: If39a144dfb322176c2d0e6c17d57d0cd6d885c41
Signed-off-by: Timo Alho <talho@nvidia.com>
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1762987
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.
Bug 2106999
Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760366
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-Created common falcon function nvgpu_flcn_bl_bootstrap() to
bootstrap falcon bootloader
-Created HAL gk20a_falcon_bl_bootstrap() which does actual
bootloader bootstrap by fetching parameters and loading
code/parameters as needed.
-Created HAL ops bl_bootstrap under nvgpu_falcon_ops.
-Created struct nvgpu_falcon_bl_info to hold info required
for bootloader to pass to common function
-Removed falcons bootstrap code in multiple file & made
changes to fill struct nvgpu_falcon_bl_info & call
nvgpu_flcn_bl_bootstrap().
Change-Id: Iee275233915ff11f9afb5207ac0c3338ca9dacc1
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756104
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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Move queries of FB MMU configuration to FB HAL. Also use g->ltc_count
instead of reading the number of LTCs from FB. These changes together
remove last direct uses of FB registers from GR.
JIRA NVGPU-714
Change-Id: I1b4b46fc2f636f5c1904e4174040a47a27948999
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1773076
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In some use cases client will disable and preempt TSG and then re-enable it
using IOCTLs provided
In case there is only one context getting re-enabled and there is no other job
submission in parallel runlist fetcher will just sleep until doorbell is
received next time
This causes above mentioned test cases to stall after re-enabling TSG
until some one submits a new job and triggers a doorbell
Fix this by explicitly triggering doorbell in vgpu code
after we enable all channels in TSG.
Bug 2205192
Change-Id: I25d643e06152adc6aaf874baf610316f6cd8f13f
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1772948
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Enable replayable fault only for contexts where they are requested.
This required moving the code to initialize subcontexts to happen
later.
Fix signedness issues in definition of flags.
JIRA NVGPU-714
Change-Id: I472004e13b1ea46c1bd202f9b12d2ce221b756f9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1773262
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