The following HAL pointers are moved to a separate HAL unit named pbdma.
pbdma_acquire_val
get_pbdma_signature
dump_pbdma_status
handle_pbdma_intr_0
handle_pbdma_intr_1
read_pbdma_data
reset_pbdma_header
The functions corresponding to these HAL units are also moved to
pbdma_{arch} files under hal/fifo correspondinging to arch gm20b,
gp10b, gv11b and tu104. Any calls to gk20a_readl and gk20a_writel
are replaced by nvgpu_readl and nvgpu_writel respectively.
Jira NVGPU-2950
Change-Id: I9723f30ddf6582df02c03fceb1fba26a206e1230
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071782
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Move load_smid_config and program_sm_id_numbering hal functions to
corresponding hal files in hal.gr.init.
Add new hal for get_sm_id_size and new static function in common.gr
init code for gr_load_sm_id_config.
JIRA NVGPU-2951
Change-Id: I27755306d278db9fcd5ab60169a64057b2989ea8
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075875
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Move load_tpc_mask and setup_rop_mapping hal functions to hal.gr.init.
Existing load_tpc_mask hal code is split to two parts, one as a common
code in gr_load_tpc_mask and register write to init.tpc_mask hal
functions.
Modify pd_tpc_per_gpc and pd_skip_table_gpc hals in the
hal.gr.init to pass struct nvgpu_gr_config as a parameter.
JIRA NVGPU-2951
Change-Id: I52e26d0f023afa511a8cf8c3e4c54f45350be4ae
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2074892
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Currently ACR header files are part of "include/nvgpu/acr/" folder &
ACR interfaces are not used by any other UNIT which allows headers to
keep restricted to ACR unit, as ACR can be divided into two stage
process like blob preparation & bootstrap, so moved header files from
of "include/nvgpu/acr/" to "nvgpu/common/acr/" to respective blob/
bootstrap/acr header files along with its dependent interfaces, this
allows interfaces restricted to header file based on operation it does.
With this any access to ACR must go through provided public functions,
this header move change caused large code modification & required to
make it with big single CL to avoid build break.
JIRA NVGPU-2907
Change-Id: Idb24b17a35f7c7a85efe923c4e26edfd42b028e3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071393
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Add new hals in unit hal.gr.init to commit RTV circular buffer
g->ops.gr.init.commit_rtv_cb()
g->ops.gr.init.commit_gfxp_rtv_cb()
Remove tu104 hal to commit global ctx buffers
gr_tu104_commit_global_ctx_buffers() since we have specific hals to
commit RTB circular buffer
Update gr_gk20a_commit_global_ctx_buffers() to directly call
hal.gr.init hals to commit RTV buffers
Jira NVGPU-2961
Change-Id: I12a53386654ebfeb98bf187385bb8b839070d569
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075230
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Add a new hal.gr.init unit hal g->ops.gr.init.get_rtv_cb_size() to
retrieve RTV buffer size
Update gr_gk20a_alloc_global_ctx_buffers() to initialize RTV buffer
size if g->ops.gr.init.get_rtv_cb_size hal is present
Remove gr_tu104_alloc_global_ctx_buffers() since it is no longer
required
Jira NVGPU-2961
Change-Id: I44be8dfdda5c813eac445192635a3a6c2b867b3a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075229
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Move g->ops.gr.commit_global_timeslice() hal operation to hal.gr.init
unit as g->ops.gr.init.commit_global_timeslice()
Drop channel pointer in parameter list since it was unused
Also change return type to void since it never returns error
Move corresponding gm20b and gv11b hal operations to hal.gr.init unit
Jira NVGPU-2961
Change-Id: I68deef45af1d52149eb354a1478cc2b5f2e4ec2a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075228
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Add a new hal operation g->ops.gr.init.load_method_init() in hal.gr.init
unit that reads method init netlist bundle and writes those values to
h/w appropriately
Use new hal in gr_gk20a_init_golden_ctx_image() instead of direct
register accesses
Jira NVGPU-2961
Change-Id: If1edd09445e55b5ad9cb1ec7b0f32cab9bfd6f05
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075227
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The fb APIs compression_page_size() and compression_align_mask() were
returning u32s, but the users all really need u64s.
This also eliminates MISRA Rule 10.3 violations for implicit casts to
smaller size objects.
JIRA NVGPU-2954
Change-Id: I8dc2b434d9564c89c0e8a1b19c4acbe167e339c1
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075595
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Move code used for transitioning between link and sublink modes
into a separate unit called 'link_mode_transition' under subelement
'nvlink'.
Also aggregate all the link/sublink mode related ops under
g->ops.nvlink.link_mode_transitions.
JIRA NVGPU-2862
Change-Id: I289faa10fd1c83b6b8d028b44fe244531ca42b15
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2035794
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Moved cbc related code and data from gr to cbc unit.
Ltc and cbc related data is moved from gr header:
1. Ltc related data moved from gr_gk20a -> gk20a and it
will be moved eventually to ltc unit:
u32 slices_per_ltc;
u32 cacheline_size;
2. cbc data moved from gr_gk20a -> nvgpu_cbc
u32 compbit_backing_size;
u32 comptags_per_cacheline;
u32 gobs_per_comptagline_per_slice;
u32 max_comptag_lines;
struct gk20a_comptag_allocator comp_tags;
struct compbit_store_desc compbit_store;
3. Following config data moved gr_gk20a -> gk20a
u32 comptag_mem_deduct;
u32 max_comptag_mem;
These are part of initial config which should be available
during nvgpu_probe. So it can't be moved to nvgpu_cbc.
Modified code to use above updated data structures.
Removed cbc init sequence from gr and added in
common cbc unit. This sequence is getting called
from common nvgpu init code.
JIRA NVGPU-2896
JIRA NVGPU-2897
Change-Id: I1a1b1e73b75396d61de684f413ebc551a1202a57
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2033286
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add new hal operation g->ops.gr.init.fe_go_idle_timeout() in hal.gr.init
unit to enable/disable fe_go_idle timeout
Use this hal in gr_gk20a_init_golden_ctx_image() instead of direct
register access
Remove timeout disable/enable code in gk20a_init_sw_bundle() since
parent API gr_gk20a_init_golden_ctx_image() is already taking care of
that
Jira NVGPU-2961
Change-Id: Ice72699059f031ca0b1994fa57661716a6c66cd2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072550
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Move GR HAL operation g->ops.gr.init_preemption_state() to hal.gr.init
unit as g->ops.gr.init.preemption_state()
Create hal.gr.init unit files for gp10b and gv11b and copy over
corresponding functions to new files
This API now takes gfxp_wfi_timeout_unit and gfxp_wfi_timeout_count as
parameter
Define gfxp_wfi_timeout_unit in struct gr_gk20a as a boolean flag named
gfxp_wfi_timeout_unit_usec
Remove GFXP_WFI_TIMEOUT_UNIT_SYSCLK/USEC macros
Jira NVGPU-2961
Change-Id: I4347b1e30c86c231e44cf274adccd8c70addcdab
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072549
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This struct was earlier moved to falcon_priv.h to give exclusive access
to only falcon unit. However with HAL unit needing access to this we
need to move it public header nvgpu/falcon.h.
JIRA NVGPU-1993
Change-Id: Ia3b211798009107f64828c9765040d628448812a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069688
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Register write from gr_gk20a_init_fs_state function are moved to hal.
New hal added for setting the pd_tpc_per_gpc, pd_skip_table_gpc and
cwd_gpcs_tpcs_num.
pd_tpc_per_gpc helps to describe the number of tpcs in each logical
gpc.
pd_skip_table helps to skip certain TPCs during distribution.
cwd_gpcs_tpcs_num helps to set number of tpcs and gpcs in CWD.
remove write for depreciated NV_PBE_PRI_ZROP_SETTING_NUM_ACTIVE_FBPS
and NV_PBE_PRI_CROP_SETTINS_NUM_ACTIVE_FBPS fields from
BES_ZROP_SETTINGS and BES_CROP_SETTINGS registers. Both these fields
changed to NUM_ACTIVE_LTCS from gm20b onwards and those are being
set in existing hal functions.
JIRA NVGPU-2951
Change-Id: I905b98356e8eadaf7e2481850de841c050ea50c5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072249
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create new hals for wait_idle and wait_fe_idle under gr.init.
modify functions to following hals and use same hals for all chips.
gr_gk20a_wait_idle -> gm20b_gr_init_wait_idle
gr_gk20a_wait_fe_idle -> gm20b_gr_init_wait_fe_idle
JIRA NVGPU-2951
Change-Id: Ie60675a08cba12e31557711b6f05f06879de8965
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2072051
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gr_gk20a_init_golden_ctx_image() right now resets sys/gpc/be units by
directly accessing gr_fecs_ctxsw_reset_ctl_r() register
Move this register write/read sequence to common.hal.gr.init unit
through HAL operation g->ops.gr.init.override_context_reset()
Use new HAL in gr_gk20a_init_golden_ctx_image()
Also fix the delay() operations. delay() should be added before we read
back gr_fecs_ctxsw_reset_ctl_r() register and not after
Jira NVGPU-2961
Change-Id: I70d3a61b5aa60846815dee52ecac544066542695
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070608
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Add new HAL unit common.hal.gr.init with below source files
hal/gr/init/gr_init_gm20b.c
hal/gr/init/gr_init_gm20b.h
In gr_gk20a_init_golden_ctx_image() we force FE power mode on and also
disable it. Extract out this sequence into new unit and expose new HAL
operation that takes a boolean flag to enable/disable power mode
g->ops.gr.init.fe_pwr_mode_force_on()
Use new HAL operation in gr_gk20a_init_golden_ctx_image()
Set this HAL for all the chips
Jira NVGPU-2961
Change-Id: I1dd35d94fda5e5296af67c0abc944e200fb752ea
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2070607
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is_fault_engine_subid_gpc HAL pointer belongs to engine HAL unit instead of
fifo. This patch moves the HAL pointer to a newly constructed engine
HAL unit.
The following new files are added under HAL/fifo/
engines_gm20b.h
engines_gm20b.c
engines_gv11b.h
engines_gv11b.c
Jira NVGPU-1315
Change-Id: If28686bf7350563b06b13348a9fe3ef0099c35b2
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2031659
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Pre-volta, cbc config is part of hw ltc and from volta onwards this is
moved to hw fb. Because of this, cbc_init functions are present in both
cbc unit and fb unit. Pre-volta uses cbc_init from cbc unit and from
volta onwards it uses cbc_init from fb unit.
With this patch, unified two cbc_init functions to cbc unit and created
new fb hal for cbc_configure. cbc unit uses fb hal for cbc_config and
fb unit is independent of cbc unit.
JIRA NVGPU-2897
Change-Id: Ib62f0b08547b031bcb5011c837e43c74931a22fe
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030906
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Create Compression Bit Cache(CBC) unit to have comptags
cache related functionality in one place. In this patch
Moved following gpu ops from ltc to cbc and renamed accordingly:
void (*init)(struct gk20a *g, struct gr_gk20a *gr);
u64 (*get_base_divisor)(struct gk20a *g);
int (*alloc_comptags)(struct gk20a *g, struct gr_gk20a *gr);
int (*ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
u32 min, u32 max);
u32 (*fix_config)(struct gk20a *g, int base);
To avoid ambiguity renamed function pointer from
init_comptags to alloc_comptags.
Moved following function from ltc.h to cbc.h:
nvgpu_ltc_alloc_cbc -> nvgpu_cbc_alloc
Also changed file name that implemented
nvgpu_cbc_alloc functionality from
os/ltc.c -> os/linux-cbc.c
JIRA NVGPU-2897
Change-Id: Ide32a98567e9a3f0a784d62221a6f484f8343e53
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030194
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In case of FBPA we need to consider mask of active FBPAs on dGPUs.
For that we have GR unit HAL g->ops.gr.add_ctxsw_reg_pm_fbpa()
Generic support to consider active mask of unit need not be in a HAL,
move it to common code in add_ctxsw_buffer_map_entries_subunits() itself
This API now supports providing active_unit_mask as its parameter
In case we don't need to consider unit mask caller will simply pass
~U32(0U) to indicate all units are active
In case of FBPA, add a new HAL g->ops.gr.hwpm_pm.get_active_fbpa_mask()
which gets mask of active FBPAs, and pass this value to common API
add_ctxsw_buffer_map_entries_subunits()
Jira NVGPU-2895
Change-Id: I0d208ce53abcd36929c25a4d248868d6eaa5c70d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069472
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Create a new HAL unit hal.gr.hwpm_map that provides chip specific
support to common.gr.hwpm_map unit
We currently have common.gr HAL g->ops.gr.add_ctxsw_reg_perf_pma()
to handle chip specific alignment of perf_pma list
We only adjust the offset of list and remaining code is same
Hence delete above HAL, and add new HAL under hal.gr.hwpm_map
g->ops.gr.hwpm_map.align_regs_perf_pma() which returns correct
alignment if HAL is defined
Remove gr_gv100_add_ctxsw_reg_perf_pma() and
gr_gk20a_add_ctxsw_reg_perf_pma() APIs since they are no longer used
Simplify perf_pma parsing by fixing alignment with new HAL and then
directly calling add_ctxsw_buffer_map_entries()
Jira NVGPU-2895
Change-Id: I1852db846e1f5441e482028c79a3f39c5142b0c2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2069471
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Move the code involved in dealing with minion into a separate unit
called "nvlink_minion". This unit includes minion HW access, ucode
handling, exposing state of minion and also dealing with minion
interrupts. The interfaces to this unit are partially exposed using
g->ops.nvlink.minion ops and rest are part of nvlink_minion.h public
header.
JIRA NVGPU-2860
Change-Id: Iea9288ea5f0b26688540b1eb8ab64afd756941a4
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030103
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Add new power/clock gating functions that can be called by
other units.
New clock_gating functions will reside in cg.c under
common/power_features/cg unit.
New power gating functions will reside in pg.c under
common/power_features/pg unit.
Use nvgpu_pg_elpg_disable and nvgpu_pg_elpg_enable to disable/enable
elpg and also in gr_gk20a_elpg_protected macro to access gr registers.
Add cg_pg_lock to make elpg_enabled, elcg_enabled, blcg_enabled
and slcg_enabled thread safe.
JIRA NVGPU-2014
Change-Id: I00d124c2ee16242c9a3ef82e7620fbb7f1297aff
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2025493
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In gr_gk20a_init_gr_config() we right now directly access a register
from hw_pri_ringmaster_*.h h/w header to read FBP count
Add a new HAL operation to PRIV_RING unit and start using it in GR code
instead of directly accessing register
g->ops.priv_ring.get_fbp_count()
Jira NVGPU-2894
Change-Id: I8a7b5423e28ef40612f55cb2915d7a2cff2f7435
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2030673
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Move bus related HAL code to new top level HAL directory: hal/.
This directory should mirror the common directory as much as
possible.
There's some nice pros here:
1. Isolate HAL and common code.
2. Since the common directory should not be including HAL
related headers directly this structure will make it
easier to catch these sorts of bugs with a script.
Change-Id: Ib9eb03a97d05db17b637b115c650adcbe9553d54
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2011627
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