tpc_pg_mask_read: function returns the value stored in the
tpc_pg_mask node. Since, it does not have the terminator it
returns garbage value after the mask value and gets troublesome
to parse in the userspace. Fix is to add '\n' at the end of the
mask value to be consistent with the earlier releases.
tpc_pg_mask_store: In this function there is a call to check if
gpu is powered on or not. In case when gpu is powered on, the return
value is just assigned to the 'err' variable which is never
returned to notify the application to follow the next steps. Thus,
need to return this value and inform the same to the userspace.
Bug 3445617
Change-Id: Ibb6fed88c83c751a5fb73181089274aa27c3f18b
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2630925
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
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The definition of srctree.nvgpu for external modules is specified as a
function of $(MAKEFILE_LIST). This variable gets extended also when
files are included, so any include directives in the makefile affect the
path because srctree.nvgpu is assigned with "?=" which is lazy like "=".
To avoid problems with the lazy init, use ":=" surrounded with an
explicit check to initialize srctree.nvgpu only when undefined.
Jira NVGPU-6427
Change-Id: Ic9847528d0da73f06bc7e421130c9c54247caadb
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2632925
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- When DISALLOW cmd is sent from driver to PMU the actual
completion of the disallow will be acknowledged by PMU
via a new RPC: ASYNC_CMD_RESP.
- Disallow needs a delayed ACK from PMU in order to disable
the ELPG.
- If ELPG is already engaged, the DISALLOW cmd will trigger
ELPG exit and then transition to PMU_PG_STATE_DISALLOW.
- After this whole process is completed, PMU will send
DISALLOW_ACK through ASYNC_CMD_RESP RPC.
- After disallow command is sent from the driver, NvGPU driver
waits/polls for disallow command ack. This is sent immediately
by RPC framework of PMU.
- Then, the driver will poll/wait for ASYNC_CMD_RESP event which
is the delayed DISALLOW ACK.
- The driver captures the ASYNC_CMD_RESP RPC sent from PMU.
- set disallow_state to ELPG_OFF.
- If the driver does not wait/poll for this delayed disallow
ack from PMU, it can result in pmu halt issues as PMU is still
processing DISALLOW cmd but the driver progressed further which
can result in errors.
Bug 3430273
Bug 3439350
Change-Id: If2acf8391d18cd3c6b8b07e3bf6577667ec99eea
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2631214
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
User fence syncpt_id in the buffer compbits state was set to 0
on allocation through PREPARE_COMPRESSIBLE_READ ioctl or
MARK_COMPRESSIBLE_WRITE ioctl.
In case NVGPU_GPU_COMPBITS_GPU is requested through the ioctl
PREPARE_COMPRESSIBLE_READ, CDE conversion command is not
submitted and the output fence is cloned from the initial
state fence (with syncpt_id=0).
NvRmSyncWait on this fence from userspace lead to below error:
13e40000.host1x: nvhost_syncpt_wait_timeout: invalid syncpoint id 0
Initialize the buffer compbits state user fence syncpt_id to
NVGPU_INVALID_SYNCPT_ID with nvgpu_user_sync_init() so that
the userspace skips the NvRmSyncWait on that fence.
While at it, initialize other uninitialized members, valid_compbits
and zbc_color.
Bug 3360675
Change-Id: Ie2a584546e1ed37841cbdc3472b598794f911e6f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2631235
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Most of the Orin chip specific code is compiled out of safety build
with CONFIG_NVGPU_NON_FUSA and CONFIG_NVGPU_HAL_NON_FUSA. Remove the
config protection from Orin/GA10B specific code. Currently all code
is enabled. Code not required in safety will be compiled out later
in separate activity.
Other noteworthy changes in this patch related to safety build:
- In ga10b_ce_request_idle(), add a log print to dump num_pce so that
compiler does not complain about unused variable num_pce.
- In ga10b_fifo_ctxsw_timeout_isr(), protect variables active_eng_id and
recover under CONFIG_NVGPU_KERNEL_MODE_SUBMIT to fix compilation
errors of unused variables.
- Compile out HAL gops.pbdma.force_ce_split() from safety since this HAL
is GA100 specific and not required for GA10B.
- Compile out gr_ga100_process_context_buffer_priv_segment() with
CONFIG_NVGPU_DEBUGGER.
- Compile out VAB support with CONFIG_NVGPU_HAL_NON_FUSA.
- In ga10b_gr_intr_handle_sw_method(), protect left_shift_by_2 variable
with appropriate configs to fix unused variable compilation error.
- In ga10b_intr_isr_stall_host2soc_3(), compile ELPG function calls
with CONFIG_NVGPU_POWER_PG.
- In ga10b_pmu_handle_swgen1_irq(), move whole function body under
CONFIG_NVGPU_FALCON_DEBUG to fix unused variable compilation errors.
- Add below TU104 specific files in safety build since some of the code
in those files is required for GA10B. Unnecessary code will be
compiled out later on.
hal/gr/init/gr_init_tu104.c
hal/class/class_tu104.c
hal/mc/mc_tu104.c
hal/fifo/usermode_tu104.c
hal/gr/falcon/gr_falcon_tu104.c
- Compile out GA10B specific debugger/profiler related files from
safety build.
- Disable CONFIG_NVGPU_FALCON_DEBUG from safety debug build temporarily
to work around compilation errors seen with keeping this config
enabled. Config will be re-enabled in safety debug build later.
Jira NVGPU-7276
Change-Id: I35f2489830ac083d52504ca411c3f1d96e72fc48
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2627048
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Add support for adding and deleting domains for all runlists together.
The core scheduler logic will control runlist domains.
Initially, however, it may be necessary to only actually schedule only
the GR runlist, but keeping the runlist code agnostic of such scheduling
logic helps isolate the control complexity.
NVGPU-6425
Change-Id: Id6039bd37a293a2cf3eaee5ed84d35459e8b89e7
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628049
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When there are multiple scheduling domains, each runlist pointer has to
be switched according to the active scheduling policy. For now implement
a trivial round robin policy to loop the domains over, just sufficient
for testing. In the future the switching will be owned by the scheduler
code, but this helps prepare the design for that.
The switching will not do anything if there is only one domain, so
current functionality is not affected.
For simplicity, all runlists are switched at the same time. In the
future, it may be desirable to swap e.g. only the GR runlist and keep
others running free, outside scheduler control.
Jira NVGPU-6427
Jira NVGPU-6425
Change-Id: Ic68c13e97761bbdc210c74794de8ccb8dbd45587
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Below sequence leads to the condition where nvgpu logs error
about spurious stall intr occurence:
1. PMU interrupt is set after ELPG command is sent to PMU.
2. Stalling irqhandler sees the interrupt and schedules
the stalling thread.
3. PMU isr gets executed from nvgpu_pmu_wait_fw_ack_status
just before the stalling irq thread is run. Due to this,
top level interrupt gets cleared.
4. When stalling irq thread gets executed it sees no
interrupt and logs as spurious interrupt.
This condition is not actually about "spurious interrupt",
hence change error log to gpu_dbg_intr log type and
rephrase it.
Bug 200780211
Change-Id: Idab62f61007012f7022a836473562795c24821ef
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628275
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Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
SW Profiler's debugfs entry "enable" has both RW permissions set
however the corresponding read operation is set to NULL.
Similarly, the other entries i.e. "percentiles", "raw_entries" and
"basic_stats" only have a read operation defined and write is set to
NULL.
To enable correct permissions, set permission for "enable" to "W"
and set permissions for others as "R" only.
Bug 200747304
Change-Id: I296a0ff08a871f752988c9b0a671c080695d5eab
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2566322
(cherry picked from commit 8542dd388da536ee693610acd0bb3a679ff52881)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2628035
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
On certain platforms, not all copy engine instances are usable. The user
shouldn't submit any work to these engines. To enforce this, remove
these engines from active/host_engine list, this should ensure that these
engines do not get advertised to userspace. In order to accomplish this
introduce the following functions:
- nvgpu_engine_remove_one_dev: This function removes the specified device
entry from following device lists: fifo->host_engines, fifo->active_engines,
runlist->rl_dev_list, runlist->eng_bitmask.
Replace iteration over LCE device type entries using
nvgpu_device_for_each(g, dev, NVGPU_DEVTYPE_LCE), along with this introduce
macro nvgpu_device_for_each_safe.
Introduce gpu_dbg_ce flag for CE debugging.
Bug 3370462
Change-Id: I2e21f18363c6e53630d129da241c8fece106cd33
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2616711
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
On production boards, there is requirement to disable GPU
profiler and debugger support. Add DT property 'support-gpu-tools'
which can be modified to enable/disable debugger/profiler support.
The default behavior is to enable the debugging features and set
'support-gpu-tools' to 1. This property is chosen to be u32 value
to be in sync with GPU vserser property by same name.
The debugger/profiler support is disabled by skipping the creation
of below nodes under /dev/nvgpu/:
1. ctxsw
2. dbg
3. prof
4. prof-dev
5. prof-ctx
Bug 200773450
JIRA NVGPU-7109
Change-Id: I86d72d17fa7f5492e117a4c1cd1144623e9b6132
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2592012
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Following error message is getting printed even when there are no fecs
ecc errors:
nvgpu: 17000000.ga10x gv11b_gr_intr_handle_fecs_ecc_error:114
[ERR] error count corrected: 0, uncorrected 0
To avoid confusion, print error messages only when fecs errors
are reported.
Bug 3417834
Change-Id: I96317555b11e1976f33add4b1dc8d84c936c26fb
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2625723
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
This patch adds two new debug nodes:
- cbc_status to retrieve cbc state information
- cbc_ctrl to flush and mmap cbc
These two nodes are to be used for purpose of testing
and debugging. One immediate goal is to use them for
verifying if CBC is programmed correctly via a user
space test.
Bug 3402817
Change-Id: I4046fb45ebfb48cb4644f88621429e1e323972c0
Signed-off-by: Martin Radev <mradev@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2620184
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Introduce HAL function gops.mssnvlink.get_links, this function retrieves
the number of nvlinks supported by the chip along with their base
addresses.
Update ga10b_mssnvlink_init_soc_credits to call mssnvlink.get_links.
Jira NVGPU-6641
Change-Id: I4ff857925f126bf41dc83eebc5723403244f66b0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618368
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Make ga10b_init_nvlink_soc_credits OS agnostic by replacing OS
specific functions with corresponding nvgpu wrappers. This function is now
assigned to gops.mssnvlink.init_soc_credits HAL.
Introduce nvgpu wrapper, nvgpu_io_map/unmap to map/unmap specified
physical address range.
Jira NVGPU-6641
Change-Id: I337bc75b8ec36552fe471bf5e42f62c19f67ed4a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618237
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Earlier, buffer metadata support was made dependent on compression.
However that is not required.
Update the enabled flag NVGPU_SUPPORT_BUFFER_METADATA setup for
various hals. Enable it for all from linux characteristics init.
Update REGISTER_BUFFER and GET_BUFFER_INFO ioctls to seggregate
the compile/runtime compression functionality.
If compression is disabled, return error in case comptags are
required else don't fail the REGISTER_BUFFER ioctl.
Bug 200767700
Change-Id: I3850ccc879f180c97b830fb3d652c094b9d28a5b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2614378
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Building NVGPU against the current upstream mainline kernel is failing
and errors such as the following are seen.
ERROR: modpost: module nvgpu uses symbol dma_buf_map_attachment from
namespace DMA_BUF, but does not import it.
ERROR: modpost: module nvgpu uses symbol dma_buf_detach from namespace
DMA_BUF, but does not import it.
ERROR: modpost: module nvgpu uses symbol dma_buf_vmap from namespace
DMA_BUF, but does not import it.
Following upstream commit 16b0314aa746 ("dma-buf: move dma-buf symbols
into the DMA_BUF module namespace"), it is now necessary to import the
DMA_BUF module namespace into the NVGPU driver to fix this.
Change-Id: I901b74cea692a5e0d66a190d01fe74a55aaf4431
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621641
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Start transitioning from an assumption of a single runlist buffer to the
domain based approach where a TSG is a participant of a scheduling
domain that then owns has a runlist buffer used for hardware scheduling.
Concretely, move the concept of a runlist domain up to the users of the
runlist code. Modifications to a runlist need to specify which domain is
modified.
There is still only the default domain that is created at boot.
Jira NVGPU-6425
Change-Id: Id9a29cff35c94e0d7e195db382d643e16025282d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621213
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
- The hardware is designed in such a way that
if GR engine is not out of reset, it still takes clock.
- This causes ELCG feature to not engage correctly.
- So for iGPU, SW should bring all supported GR
engines out of reset during gpu boot, if MIG feature
is not enabled.
- This will help low power feature like elcg to
engage correctly and improve dynamic power savings.
- For dGPU, all GRs are out of reset by default by dev init.
Bug 200778542
Change-Id: I5f3519f73b4aaf1804fd112f28fe980f58181cd8
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2613718
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Below error notifier message is not really warning/error as that
is user triggered reset and the notifier value set is already
consumed by userspace hence limit this message to INFO type.
nvgpu: 17000000.gp10b nvgpu_set_err_notifier_locked:142 [ERR] error notifier set to 43 for ch 460
Bug 3344409
Change-Id: Ia41cc85f30111ef72994f3ce8e5113e881c06b1b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2620974
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GVS: Gerrit_Virtual_Submit
Delete an unnecessary check of the active_channels bitmap when
attempting to bind a channel to a TSG. There is already a verification
that the channel must not be a part of a TSG; if it's not, it cannot be
set in the bitmap. All channels become active via a parent TSG, but the
activity check predates this design.
A channel is bound to a TSG early before setting up its gpfifo etc. and
mandatory membership of a TSG is one of the setup_bind prechecks.
Jira NVGPU-6425
Change-Id: Id34686f198db0a0265ffd6a49a0b2e47c37fd5f7
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2621211
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Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Move the active_channels and active_tsgs bitmaps from struct
nvgpu_runlist to struct nvgpu_runlist_domain. A TSG and its channels are
currently active as part of a runlist; in the future, a runlist may be
switched from multiple domains that each are a collection of TSGs.
The changes are still internal to the runlist code. Users of runlists
need no modifications.
Jira NVGPU-6425
Change-Id: I2d0e98e97f04b9716bc3f4890cf881735d0ab664
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2618387
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