Update the below two regops ctxsw address types to fix misnomers:
- CTXSW_ADDR_TYPE_ROP:
This address type is used to access the PMM config registers and does not
belong to the ROP unit. Hence, rename it to CTXSW_ADDR_TYPE_PMM_FBPGS_ROP.
- CTXSW_ADDR_TYPE_BE:
This address type is used to access registers exclusively in ROP unit and not
the entire BE unit. Hence, its more appropriate to rename it to
CTXSW_ADDR_TYPE_ROP.
In addition, rename the following functions:
- pri_is_be_addr_shared => pri_is_rop_addr_shared
- pri_be_shared_addr => pri_rop_shared_addr
- pri_is_be_addr => pri_is_rop_addr
- pri_get_be_num => pri_get_rop_num
Bug 3146324
Change-Id: I8613f0972936699b2ef8f7dbe3de78582af2a35f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2429885
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With Generic Power Domains (genpd), bpmp driver will manage the GPU
powergating. With the nvgpu idle/unidle flows updated for VPR with
genpd/RPM, the usage of the below tegra bpmp calls can be removed
from nvgpu from railgate APIs for t186 and t194. Note that genpd
is available in k4.14 onwards, so this will work on current
downstream kernel.
tegra_bpmp_running
tegra_powergate_is_powered
tegra_powergate_partition
tegra_unpowergate_partition
Runtime suspended state indicates that the device is railgated.
Update the t186 and t194 is_railgated handlers with this. t210
railgate/unrailgate will be still managed by nvgpu as bpmp
support is not present.
Bug 200602747
JIRA NVGPU-5356
Change-Id: Iadfd794cb51bc41ca927b84fc212ac766d60094d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2376642
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Extend the runtime suspend/resume based idle/unidle logic in the
probe case to handling done in gk20a_do_idle/unidle for nvgpu
after the probe completion.
If the railgating is disabled, setting autosuspend_delay to 0 will
enable the suspend. If railgating is enabled, autosuspend delay
will be > 0. Setting it to 0 will enable the immediate suspend.
With this approach based on RPM, forced_reset logic is removed.
force_reset_in_do_idle is also removed as railgating is
supported.
Bug 200602747
JIRA NVGPU-5356
Change-Id: Iaf6d5ab651b8200f0547b45d90f812110cf63c0e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2375941
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With genpd based runtime PM, the device railgating is managed by the PM
core and the nvgpu manages the clocks. To suspend/resume the device for
idling/unidling while initializing secure alloc, runtime PM is to be
enabled during probe.
nvgpu platform railgate handlers will be only managing the clocks.
During probe, the nvgpu driver poweroff/poweron are not to be
invoked as part of driver runtime suspend/resume hence probe
state is added.
After platform probe initializes the clock, explicit runtime resume of
the device is required to sanely suspend it during gk20a_do_idle.
Runtime PM configuration differs based on the NVGPU_CAN_RAILGATE
capability, hence the runtime PM is enabled ("truly") only for
the duration of nvgpu_probe and then the state is reverted at
the beginning of gk20a_pm_late_init.
Bug 200602747
JIRA NVGPU-5356
Change-Id: I1fbd03d3f49da07ccbee9714387e00ffc688864e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2375939
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With genpd based runtime PM, the device railgating is managed by the PM
core and the nvgpu manages the clocks. To suspend/resume the device for
idling/unidling while initializing secure alloc, runtime PM will be
enabled before init_secure_alloc.
nvgpu platform railgate handlers will be only managing the clocks. The
clocks and secure alloc initialization was done in platform probe
(applicable to tegra).
To suspend (railgate and clks disable) and resume cleanly during secure
alloc init, the platform probe should happen first that initializes the
clocks. Post that device runtime PM will handle the device idle/unidle
properly.
Hence, move gk20a_tegra_init_secure_alloc to platform late_probe.
Runtime PM changes are introduced in the later patches.
Bug 200602747
JIRA NVGPU-5356
Change-Id: I5130ff43f7b75ddc51cb7096ba6532b3f5397258
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2375938
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Starting with nvgpu-next, the ctxsw ucode computes the checksum for each
ctxsw'ed register list, this checksum is saved at the end of the same list;
This entry will be given a special placeholder address 0x00ffffff, which can
be used to distinguish it from other entries in the register list.
There is only one checksum per list, even if it has multiple subunits. Hence,
update "add_ctxsw_buffer_map_entries_subunits" to avoid adding checksum
entires for each subunit within a list.
Bug 2916121
Change-Id: Ia7abedc7467ae8158ce3e791a67765fb52889915
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457579
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The function "nvgpu_engine_mmu_fault_id_to_eng_id_and_veid" updates only
the veid field and leaves the engine_id as invalid. This can cause the
recovery to be skipped in certain instances of MMUFAULT; For example,
the MMUFAULT when a unbind is done on a channel which is currently active
on the engine. In this case, the ch_id associated with the fault is -1 and
the function "gv11b_mm_mmu_fault_handle_non_replayable" will not set the
rc_type correctly causing recovery to be skipped and leaving the engine in
a bad state.
Bug 3163660
Change-Id: Ic99c47771a4002c153ac77ab0473b11d01cfd54a
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457259
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
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gr_gv100_reset_hwpm_pmm_registers() writes a bunch of registers in
sys/gpc/fbp chiplets to reset perfmons. To ensure all the writes have
completed it is necessary to readback each chiplet's PRI fence register.
Add and use new HAL g->ops.priv_ring.read_pri_fence() to achieve this.
Implement the HAL for gv11b in new source code file
hal/priv_ring/priv_ring_gv11b.c.
Bug 2510974
Jira NVGPU-5360
Change-Id: If4dd61cb4265422e8c2d16884790eb0fe7f2c103
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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Update pmu ucode version for next pmu to 29323513.
This version is taken from P4 CL#29323216.
Changes:
- Enabled ACR task support
- Disabled few features/code for commands to work
- ELPG fifo preemption hals fixed
- Halt functions in ELPG save and restore functions
are commented as bloaded flag is not getting set. This
is not significant as this change will not have any impact
in elpg functionality.
P4 ToT CL on which above change was made: P4 CL#29322732
P4 CL link: https://p4sw-swarm.nvidia.com/changes/29323216
Bug 200666202
Signed-off-by: Ramesh Mylavarapu <rmylavarapu@nvidia.com>
Change-Id: I34581cc15889463fa363cffb369485171c603247
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447234
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In K5.9 those two functions are changed to reject calls directly
using global pmc pointer. So it's a bit complicated to revert to
the point where GPU can feel free to call them.
For an easier future mantainance, a new set of APIs are added to
all existing kernels to let GPU driver control clamp without any
direct access to PMC registers.
Bug 200663781
Change-Id: Ifce4765525eee6d61083896fc9a126892cbb86ba
Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2441010
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This CL covers the following code changes,
1) Added some more documentation for gpu_instance_id
and gr_instance_id.
2) Used the gr_sys_pipe_id for gr_instance_id.
2) Removed gr_syspipe_id attribute.
4) Removed NVGPU_GPU_FLAGS_SUPPORT_MIG flag.
3) Changed the device node name to use gpu instance id + syspipe id
combination insted of gpu instance id + gr engine instance id.
Bug 2802347
Change-Id: Id6ca7db5765ab31b5d83472be35dde432c2281ed
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2440532
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On Linux, nvrm_gpu can open channel/tsg/address space only using ctrl
node. This tricks nvrm_gpu into considering physical instance as
actual available fGPU if ctrl node is exposed for physical instance.
There is no current requirement to expose physical instance ctrl node.
It might be needed later for profiling use cases.
For now, skip dev node creation for physical instance.
Jira NVGPU-5648
Change-Id: I23398ba993f97e2d2f344876c0c6b0c82b336402
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2439880
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Store nvgpu_cdev pointer in struct tsg_private and assign it in
nvgpu_ioctl_tsg_open.
In gk20a_tsg_ioctl_bind_channel_ex(), extract gpu_instance_id from
cdev pointer and then extract instance specific max VEID count from
gpu_instance_id.
Use this max veid count to validate subcontext id coming from user.
Jira NVGPU-5648
Change-Id: I71cea5180e1ced1a72818d160f1a951c1c6ec770
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2438925
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nvgpu_channel_get_max_subctx_count() right now always returns max subctx
count for 0th instance. Update this function to return max subctx count
for GPU instance for which channel is allocated.
For CE channels that are allocated and managed by nvgpu, cdev pointer is
not set in channel private data (since it is assigned in OS specific
code). For those channels continue returning max subctx count for 0th
instance. CE channels should not need subcontexts anyways.
Add nvgpu_cdev pointer in struct nvgpu_channel_linux. Assign it in
__gk20a_channel_open() and clear it in gk20a_channel_release()
Move code to get runlist and gpu_instance_id after nvgpu_get() call.
Accesses to gk20a pointer should always come after nvgpu_get().
Also add a debug print to dump runlist_id and gpu_instance_id being
used for channel.
Jira NVGPU-5648
Change-Id: Idf58ccefdb7dc9fec78100f79c647e5a00b8fb29
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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