Pre-GP10X
All chips prior to GP10X do not support ZBC (Zero Bandwidth Clear) to stencil
part of the packed kinds (packed kinds refer to Z24S8 and Z32_X24S8 kinds).
Clears for these kinds typically happen in two phases, depth phase and
stencil phase. The depth clears can be compressed or ZBC-ed, whereas the
stencil part is always uncompressed.
Stencil ZBC in GP10X
For GP10X both the depth and the stencil data for these packed kinds can be
ZBC cleared. A given tile will be a cross product of the following states
for depth and stencil.
Depth: Uncompressed, 1-2 plane compressed, 3-4 plane compressed, ZBC index 0,
ZBC index 1
Stencil: Uncompressed, ZBC index 0, ZBC index 1, ZBC index 2
JIRA GV11B-9
Change-Id: I3381fd6305a4fada64211176b8ef98f27b04089f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1235520
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
gv11b needs atleast one subcontext to submit work. To support
legacy in gv11b, currently main context is always copied into
subcontext0 (veid0) during channel commit instance.
As part of channel commit instance, veid0 for that channel is
created and relevant pdb and context info copied to vedi0.
JIRA GV11B-21
Change-Id: I5147a1708b5e94202fa55e73fa0e53199ab7fced
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1231169
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix following sparse warning by making function as static:
$TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/gr_gv11b.c:1529:5:
warning: symbol 'gr_gv11b_setup_rop_mapping' was not declared.
Should it be static?
Bug 200088648
Change-Id: Idd388170f35e7e6cd7559d8aab8968f7e8e545c6
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1261891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Add support for new litter values:
GPU_LIT_NUM_SUBCTX
GPU_LIT_NUM_SM_PER_TPC
Also updated get_litter_value api to use int
instead of enum type.
JIRA GV11B-21
Change-Id: Ide06245d03743e2d757d27d045701beb25b6707b
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1254857
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Update pmu HAL to have function for
is_pmu_supported(). At this moment
pmu support is disabled for gv11b.
JIRA GV11B-21
Change-Id: I1790e6e4dc80e0761df78e6092da2b6ca0e39d64
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1243919
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Enable stall and non-stall interupts for gv11b.
Support for replayable interrupts will be added later.
Hub interrupts are not enabled and they will be enabled
after non-replayabale fault handling is in place.
JIRA GV11B-11
Change-Id: I99cc470dae9d02f92e9fb3cb49186dabfed78875
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1239337
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
gpu is completely out from host1x block and
no need to create device nodes under host1x.
Bug 1735760
Change-Id: I2df861b07b38ce6931a86a928184ad164095948a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1181063
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Fix following sparse warning my making funtion as static:
$TOP/kernel/nvgpu-t19x/drivers/gpu/nvgpu/gv11b/mm_gv11b.c:23:6:
warning: symbol 'gv11b_mm_is_bar1_supported' was not declared.
Should it be static?
Bug 200088648
Change-Id: I4af7ed1ae112813887a14a11b8fcea0b72c90e39
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1236689
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
For gv11b, userd is allocated from sysmem.
Updated gp_get and gp_put functions to read or
write from sysmem instead of bar1 memory.
In gv11b, after updating gp_put, it is required
to notify pending work to host through channel
doorbell.
JIRA GV11B-1
Change-Id: Iebc52e6ccfc8b9ca0c57b227190e0ce1161076f1
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1226613
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
This is done to designate nvgpu-t19x module owners so as to help with
tools like Coverity and Code Coverage.
bug 200195707
Change-Id: I1f75c11392c74372112018ed3f8fc882dd676bc4
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/1220031
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Updated hw headers to CL#37001916. Some of
important changes include new door bell user
mode mechanism and new runlist structure.
Bug 1735765
Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1205888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Event notifications on TSGs should only be sent to the channel that caused the
event to happen in the first place, not evey channel in the tsg. Any more and
the debugger will not be able to tell what channel actually got the event.
Worse yet, if all the channels in a tsg are bound to the same debug session
(as is the case with cuda-gdb), then multiple nvgpu events for the same gpu
event will be triggered, causing events to be buffered and the client to get
out of sync.
One gpu exception, one nvgpu event per tsg.
Bug 1793988
Change-Id: Ifb33b65f09f67b0e323917c7e7ea016fc3676f18
Signed-off-by: Cory Perry <cperry@nvidia.com>
Reviewed-on: http://git-master/r/1194207
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Added control flag for nvgpu infra to allow kernel to create privileged
CE channels for page migration and clearing support between sysmem
and videmem.
JIRA DNVGPU-53
Change-Id: I2d1faf034e194b7a850ac33aec4f6c315c7e552b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1173093
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
For devices that have vidmem available, use the vidmem allocator in
gk20a_gmmu_alloc{,attr,_map,_map_attr}. For others, use sysmem.
Because all of the buffers haven't been tested to work in vidmem yet,
rename calls to gk20a_gmmu_alloc{,attr,_map,_map_attr} to have _sys at
the end to declare explicitly that vidmem is used. Enabling vidmem for
each now is a matter of removing "_sys" from the function call.
Jira DNVGPU-18
Change-Id: Ieb13c21c774380ac0be9987e177b4adc0a647abb
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1176810
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that
buffers represented as a mem_desc and present in vidmem can be mapped to
gpu.
JIRA DNVGPU-18
JIRA DNVGPU-76
Change-Id: I67d476b2c1b84218217ef203e429fb5e8a33adc7
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1169297
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
From this patch onwards, runlist_id is a member of
struct channel_gk20a. So removed hard coded
runlist_id mapping logic.
JIRA DNVGPU-25
Change-Id: Ia02feffdc057b0dceab9721423feeed1cc7a1c12
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1161779
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
