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2627 Commits

Author SHA1 Message Date
Richard Zhao
ab6d4fa543 gpu: nvgpu: create common sim reg accessors 
sim reg accessors is common after it moved to use os abstract layer reg
accessors.

Bug 2999617

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I1c0ff7ca1724cde09dd845c077763709ea2ef915
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517383
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-04-28 19:15:31 -07:00
Vedashree Vidwans
86cb03d2f1 gpu: nvgpu: Replace WAR keyword with "fix" 
Replace/remove "WAR" keyword in the comments in nvgpu driver with "fix".
Rename below functions and corresponding gops to replace "war" word with
"errata" word:
- g.pdb_cache_war_mem
- ramin.init_pdb_cache_war
- ramin.deinit_pdb_cache_war
- tu104_ramin_init_pdb_cache_war
- tu104_ramin_deinit_pdb_cache_war
- fb.apply_pdb_cache_war
- tu104_fb_apply_pdb_cache_war
- nvgpu_init_mm_pdb_cache_war
- nvlink.set_sw_war
- gv100_nvlink_set_sw_war

Jira NVGPU-6680

Change-Id: Ieaad2441fac87e4544eddbca3624b82076b2ee73
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515700
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-04-28 19:14:49 -07:00
Vedashree Vidwans
aba26fa082 gpu: nvgpu: handle chip specific erratas 
Currently, there are few chip specific erratas present in nvgpu code.
For better traceability of the erratas and corresponding fixes,
introduce flags to indicate existing erratas on a chip. These flags
decide if a corresponding solution is applied to the chip(s).

This patch introduces below functions to handle errata flags:
- nvgpu_init_errata_flags
- nvgpu_set_errata
- nvgpu_is_errata_present
- nvgpu_print_errata_flags
- nvgpu_free_errata_flags

nvgpu_print_errata_flags: print below details of erratas present in chip
1. errata flag name
2. chip where the errata was first discovered
3. short description of the errata

Flags corresponding to erratas present in a chip are set during chip hal
init sequence.

JIRA NVGPU-6510

Change-Id: Id5a8fb627222ac0a585aba071af052950f4de965
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2498095
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-04-28 19:14:44 -07:00
Lakshmanan M
3f8c562004 gpu: nvgpu: Add nvgpu_early_poweron() support 
1) NvGpu dev node needs to be created in gpu power on
early stage to avoid latency introduced by udevd.
For creating dev node, device and grmgr init
needs to move to early stage of GPU power on.
After grmgr init, NvGpu can identify the number of MIG
instance required for each physical GPU.
For that, added a new API nvgpu_early_poweron() to handle
early init which is required for before dev node creation.

2) Removed fifo dependency in nvgpu_init_gr_manager()

3) Used get_max_subctx_count() directly to query
the veid/subctx count.

JIRA NVGPU-6633

Change-Id: Ib9d7c3e184c71237b0da9305515ccd8ceda1d5ad
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517173
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 2021-04-22 15:00:54 -07:00
Deepak Nibade
c08719cb0b gpu: nvgpu: move graphics specific HALs to fusa files 
All graphics code is under CONFIG_NVGPU_GRAPHICS and all the HALs are
in non-fusa files. In order to support graphics in safety,
CONFIG_NVGPU_GRAPHICS needs to be enabled. But since most of the HALs
are in non-fusa files, this causes huge compilation problem.

Fix this by moving all graphics specific HALs used on gv11b to fusa
files. Graphics specific HALs not used on gv11b remain in non-fusa files
and need not be protected with GRAPHICS config.

Protect call to nvgpu_pmu_save_zbc() also with config
CONFIG_NVGPU_POWER_PG, since it is implemented under that config.

Delete hal/ltc/ltc_gv11b.c since sole function in this file is moved to
fusa file.

Enable nvgpu_writel_loop() in safety build since it is needed for now.
This will be revisited later once requirements are clearer.

Move below CTXSW methods under CONFIG_NVGPU_NON_FUSA for now. Safety
CTXSW ucode does not support these methods. These too will be revisited
later once requirements are clearer.
NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE

Jira NVGPU-6460

Change-Id: Ia095a04a9ba67126068aa7193f491ea27477f882
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2513675
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 2021-04-22 14:59:38 -07:00
Seshendra Gadagottu
21e1328ea1 gpu: nvgpu: add fb gops for set_atomic_mode 
Separated set_atomic_mode functionality from
init_fs_state/enable_nvlink and created new
fb gops for set_atomic_mode.

In gpu init sequence, set_atomic_mode is
called after acr_construct_execute to take care
of design changes required for nvgpu-next
architectures.

Updated fb_gv11b_init_test to use set_atomic_mode
gops along with init_fs_state.

Bug 3268664

Change-Id: I1ab9eb21cc4cce77f3325c4e8821a75b6e85fba2
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2508095
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 2021-04-22 14:58:36 -07:00
Sami Kiminki
3aceed2db1 gpu: nvgpu: add changes for nvgpu-next 
- Add new UAPI IOCTLs.
- Add nvgpu-next gops in fb and gr.
- Initialize and teardown vab during mm_support

Bug 2999621

Change-Id: Icc241f1a234bfee3fd20dc69b42c92e0af6d445c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2447064
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 2021-04-22 07:35:34 -07:00
dt
f2b69c8704 gpu: nvgpu: mig: Add sysfs nodes for mig mode selection 
This is adding two sysfs nodes
1. mig_mode_config: to select the mig_mode
2. mig_mode_config_list: to list the available mig configs.

Added logic to skip gpu dev node creation only for
real MIG physical device.
Added logic to skip the gpu characteristics flags only for
real MIG physical device.

JIRA NVGPU-6633

Change-Id: I4a450b6d658f76e79d89f863c00dffad4558c70f
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2499284
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 2021-04-21 14:49:57 -07:00
Richard Zhao
cfc1281223 gpu: nvgpu: vgpu: remove gp10b support 
gp10b vgpu won't be supported on future releases.

- removed gp10b vgpu hal code
- removed vgpu bar1 related code
- removed gp10b vgpu linux platform code

Jira GVSCI-10202

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ic1bfeb12c854df3808a0c7e67f5c52bc1e80ab2d
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2517273
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-21 06:06:22 -07:00
absalam
3ec369d60a gpu: nvgpu: Disable Clock Arbitor for TU104 
This patch is to disable the clock arbitor for TU104.
TU104 is not a POR for Drive 6.0 so disabling it to easy migration
of clk arb for GA100.
As a first step all the NVRM Clock tests will be skipped by setting
NVGPU_SUPPORT_CLOCK_CONTROLS to false for TU104.
Then clk arbitor will be rewritten for GA100 and enabled back.
This patch implements by adding a new flag NVGPU_CLK_ARB_ENABLED which
holds the status of clk arbitor for each platform and disables them for
TU104

Bug 200699763

Change-Id: I51cd5c7821bdc0b48080c17a70735925b278ddf5
Signed-off-by: absalam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2515086
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-04-20 07:47:38 -07:00
Richard Zhao
643eb158a3 gpu: nvgpu: move mapped regs to gk20a 
- moved reg fields to gk20a
- added os abstract register accessor in nvgpu/io.h
- defined linux register access abstract implementation
- hook up with posix. posix implementation of the register accessor uses
  the high 4 bit of address to identify register apertures then call the
  according callbacks.

It helps to unify code across OSes.

Bug 2999617

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ifcb737e4b4d5b1d8bae310ae50b1ce0aa04f750c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2497937
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-04-19 19:45:24 -07:00
Antony Clince Alex
95bfa039f5 gpu: nvgpu: tu104: implement l2 sector promotion 
Introduce new HAL gops_ltc.set_l2_sector_promotion to configure L2
sector promotion policy. The follow three promotion settings are support:
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_NONE
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_64B
- NVGPU_GPU_IOCTL_TSG_L2_SECTOR_PROMOTE_FLAG_128B

Add ioctl "NVGPU_TSG_IOCTL_SET_L2_SECTOR_PROMOTION" to the gpu tsg node
to support l2 sector promotion. On chips which do not support sector
promotion, the ioctl returns 0.

Bug 200656177

Change-Id: Iad835a5c954d3b10da436cfafb388aaaa04f44c7
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2460553
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-16 03:35:57 -07:00
Antony Clince Alex
5517e14e57 gpu: nvgpu: tu104: support regops to lts_tstg_cfg2/3 registers 
In-order to support L2 sector promotion, lts_tstg_cfg2,3 registers were
added to the SYS priv save segment of the ctxsw'ed image.

Update gops_gr.decode_priv_addr HAL to include regops support to the
above two registers.

Introduce HAL ops gops_ltc.pri_is_lts_tstg_addr to detect lts_tstg
addresses.

Bug 200656177

Change-Id: I0f6c24d802edf8ac72917ed099d7ae153f6b4219
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510281
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-16 03:35:52 -07:00
ajesh
394b013911 gpu: nvgpu: address DVR comments for common.utils 
Address the issues in common.utils unit which came up in DVR.

JIRA NVGPU-6595

Change-Id: I0573dc97cb33ab7f0618ed43fb60e9b950ccc086
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510296
(cherry picked from commit 3e8a049377d4f3b9ea6f41d9d21eca90bf374b52)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512609
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-04-13 07:13:06 -07:00
ajesh
a3958e6e66 gpu: nvgpu: address DVR comments for posix unit. 
Fix the issues in posix unit as per the DVR comments.

JIRA NVGPU-6615

Change-Id: I0069824c763e80df201df12efa38531eb2399762
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510842
(cherry picked from commit 7eed91174306ba358bb9a4ad6192479d52edde15)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2512606
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-04-13 07:13:01 -07:00
Tejal Kudav
d67cea61f1 gpu: nvgpu: Move SDL err info structs to common 
The SDL's error reporting code will be leveraged by central interrupt
controller (CIC) or common.cic unit.
This is a base patch to move SDL error reporting code from QNX
to common. Move the data structures used during error reporting to
common header - nvgpu_err_info.h

JIRA NVGPU-6522

Change-Id: Ie6b209323a14b9bb38e3402c2427fbcdaae52206
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2504726
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2021-04-09 17:36:42 -07:00
Lakshmanan M
7de19b0956 gpu: nvgpu: Add api to get the physical gpc mask 
1) Added a utility api to query the physical gpc mask for a
gpu instance.
2) Expose physical gpc mask during MIG case (par with legacy case).

JIRA NVGPU-5650

Change-Id: I7efb031ac6539d8859b265f42d269233a3a421bf
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2510854
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-04-07 20:16:38 -07:00
Mayur Poojary
6277d57936 gpu: nvgpu: Add new api for setting longer timeslice on dbg node 
Add new ioctl api for setting longer timeslice and get timeslice
inside 'dbg' dev node.
Update ioctl gpu_get_characteristic to pass the max timeslice value
Add debugfs to access and change the max timeslice value

Bug 1842244

Change-Id: I7e80f59162cf5d90496f9752fc128f5fa8dcc7d2
Signed-off-by: Mayur Poojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471569
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-04-06 04:37:38 -07:00
srajum
a3efb4cc98 gpu: nvgpu: Hiding extra branch with nvgpu_assert(), BUG_ON() API 
- A static inline for POSIX/QNX so that we can hide the branch in
  nvgpu_assert(), BUG_ON() from the branch analysis for users of this
  function.

- A macro for BUG_ON() is showing the extra branch for every instance,
  which causes huge drop in branch coverage.

JIRA NVGPU-6547

Change-Id: Iaa77df2b4d5b3d49596f05d9554604582b1209ae
Signed-off-by: srajum <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2503609
(cherry picked from commit 6f36f0b47ac9911526b6c434a8cf5c4a456aeacf)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2504692
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-03-30 19:05:21 -07:00
Rajesh Devaraj
0a713d366a gpu: nvgpu: add doxygen for macros 
This patch adds doxygen for macros related to SDL unit.
Also, it removes macros related to unused service IDs.

LTC_RSTG is not present in GV11B. So, the error injection
should not be supported for LTC_RSTG. This patch moves
ltc_gv11b_debug_fusa as part of non-safety build.

JIRA NVGPU-6181

Change-Id: Iede1612f1c85e2fad80e22bcc9d10c4552c73a92
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
(cherry picked from commit 6bdd4781d8311613eebaf1cccead01823a45084e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2506140
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-03-30 07:51:36 -07:00
Vedashree Vidwans
e445b57b04 gpu: nvgpu: Move interrupt ISR code to common 
This is one of the steps in restructuring of interrupt code.
- Move ISR logic to common code. This will allow us to add mixed ASIL
error handling levels.
- Modify nonstall ISR to use threaded interrupts. Bottom half of
nonstall ISR will run nonstall operations instead of adding work to
workqueues.
- Remove nonstall workqueue implementation.

JIRA NVGPU-6351

Change-Id: I5f891b0de4b0c34f6ac05522a5da08dc36221aa6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2467713
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 2021-03-25 02:34:57 -07:00
Antony Clince Alex
7f4e39aaf4 gpu: nvgpu: update pma stream teardown sequence 
On nvgpu-next chips additional steps are required for pma stream teardown.
Introduce wrapper function: NVGPU_NEXT_PROFILER_QUIESCE to perform this.

Jira NVGPU-5689

Change-Id: Iafdb9c6091b468b51295827467078d24e47d5e1f
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491755
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-23 04:39:20 -07:00
Divya Singhatwaria
cc34df76f9 gpu: nvgpu: Add support for ELPG_MS feature 
- To enable ELPG_MS feature, add identifier for
  MS_LTC engine.
- The identifier is then passed
  as pg_engine_id to enable the MS_LTC engine.
- Add enable flag NVGPU_ELPG_MS_ENABLED for
  enabling/disabling ELPG_MS feature at init.

JIRA NVGPU-6430

Change-Id: Ie1f477918332d85ec98b3bd4d05b8e773d74eab8
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480750
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-03-18 15:29:06 -07:00
scottl
75d98f55d7 gpu: nvgpu: add SUPPORT_MAPPING_MODIFY flags 
Add new NVGPU_SUPPORT_MAPPING_MODIFY enable flag that is used to
control the value of the exported NVGPU_GPU_FLAGS_SUPPORT_MAPPING_MODIFY
flag.

These flags are currently only enabled on linux in non-virtualized
environments.

Jira NVGPU-6374

Change-Id: Ia85c353b767b4f7d0aebc04838f44996bc38c61f
Signed-off-by: scottl <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2490986
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2021-03-16 14:07:21 -07:00
Sagar Kadamati
9e13fd900d nvgpu: gpu: update runlist in vserver 
On QNX, Setting runlist is not happening till runlist submit. On Linux,
Setting runlist is happening at the time of channel open. due to
implimentations, which effect's channel configuration.

We need runlist for channel configuration from now.

Adding runlist parameter for below calls
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL
 * TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX

Bug 200701789

Change-Id: Ibd3262b43e38f54c76c4ae67ce683eccf4460cdc
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485256
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-16 06:07:30 -07:00
Antony Clince Alex
7072b39783 gpu: nvgpu: gv11b: update prop hww handling 
Update prop hww handling to read and print additional diagnostic
registers.

Generate following registers:
- gr_gpc0_prop_hww_esr_coord_r
- gr_gpc0_prop_hww_esr_format_r
- gr_gpc0_prop_hww_esr_state_r
- gr_gpc0_prop_hww_esr_state2_r
- gr_gpc0_prop_hww_esr_offset_r

Rename following registers and associated fields:
- pes_hww_esr => gpc0_ppc0_pes_hww_esr
- setup_hww_esr = > gpc0_setup_hww_esr
- zcull_hww_esr => gpc0_zcull_hww_esr
- prop_hww_esr => gpc0_prop_hww_esr

Jira NVGPU-6078
Bug 2865015

Change-Id: I131c48d2375ef0a76ac6c57ff1eb019f7c113286
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2472894
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-12 04:38:04 -08:00
Antony Clince Alex
f41e5975d8 gpu: nvgpu: add ioctl to configure l2 max_ways_evict_last 
Add ioctl support to configure and read the max number of lines/ways
in a L2 cache set that can be marked as EVICT_LAST. This is accomplished
through two new ltc hals: set_l2_max_ways_evict_last,
get_l2_max_ways_evict_last. These hals will only be set for nvgpu-next
chips. Incase of legacy chips, the IOCTLs will return error -ENOSYS.

Generate following litter constants to get the number of sets in a l2
slice and the number of ways in each set:
- GPU_LIT_NUM_LTC_LTS_SETS
- GPU_LIT_NUM_LTC_LTS_WAYS

Add gpu characteritics flag: NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED to
allow userspace driver to determine if L2_MAX_WAYS_EVICT_LAST ioctl is
supported.

Bug 200605474

Change-Id: Id3180f891399f5e128500f3835d762aee59953e0
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445884
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-03-12 04:36:22 -08:00
Vedashree Vidwans
3b6eb25668 gpu: nvgpu: update common.ce doxygen comments 
- Update function documentation
- Rename test_setup_env and test_free_env to test_ce_setup_env and
test_ce_free_env respectively. This will make sure that ce test has
independent setup and free functions.
- Add doxygen comments for nonstall workqueue operations in mc.

Jira NVGPU-6249

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I451d7b77e9a4f60fa30a9de640d423199c1a206c
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2459666
(cherry picked from commit b367d3d0ea7f92b722aebdc8cf6018979fe74c47)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480584
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2021-03-04 11:04:25 -08:00
Vedashree Vidwans
0477ce539a gpu: nvgpu: add variable range common.mc doxygen 
Update common.mc API doxygen comments to add input variable ranges.

Jira NVGPU-6240

Change-Id: I512cf3a6975e745fc28b50048513a1cfe3f0b0ee
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
(cherry-picked from commit 63c1be64f4d2c07e0b5c447914bc21e827bf6d76)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2482060
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
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 2021-03-04 11:04:20 -08:00
Vedashree Vidwans
26fc64fb0b gpu: nvgpu: update common.mc function and docs 
- Update documentation for common.mc and gops_mc functions.
- Rename test_setup_env and test_free_env to test_mc_setup_env and
test_mc_free_env respectively. This will make sure that mc test has
independent setup and free functions.
- Add doxygen comments for mc.enable and mc.disable.
- Modify MC unit test description.

Jira NVGPU-6240

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I87291ee5f90b8e3c29c475c00a78c7855de5740e
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457183
(cherry picked from commit c62ff36f87878a8a7513bef06e111117d96c61c8)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480602
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2021-03-04 11:04:15 -08:00
ajesh
d1e836f059 gpu: nvgpu: Fix MISRA violations in Posix 
Fix violations of MISRA Rule 21.2 in Posix unit.

JIRA NVGPU-6533

Change-Id: I21bb6c4c18f7a904d639bf210bcd3d29f37d69bd
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2486766
GVS: Gerrit_Virtual_Submit
(cherry picked from commit 5239352b4acbe29a7cdb39821e68a717b132d2c9)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491861
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2021-03-04 00:37:20 -08:00
ajesh
0030dc3eb4 gpu: nvgpu: fix MISRA violations in Posix unit 
Fix violations of MISRA rule 5.4 in Posix unit.

JIRA NVGPU-6534

Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184
(cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491855
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2021-03-04 00:37:15 -08:00
Deepak Nibade
53cc5be723 gpu: nvgpu: update doxygen for common.gr unit 
Update common.gr doxygen based on review comments from design
verification.
- Add error return values to some APIs.
- Remove redundant description lines from some APIs.

Update gm20b_gr_falcon_status_check_ctx_wait_ucode() to return
actual error codes instead of -1.

Jira NVGPU-6494

Change-Id: Ieb3f5acd27c30cd50049b114ddd8847b1b376ca3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2490213
(cherry picked from commit 3694fd1bdd1ac36f8c91b1fbaab47cadd8ba1868)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2490211
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-03-02 19:34:13 -08:00
Vedashree Vidwans
4cc99d035d gpu: nvgpu: update doxygen for common.fifo 
- Add doxygen comments for nvgpu_tsg_open_common().
- Update return and return value description for
1.	nvgpu_fifo_init_support()
2.	nvgpu_fifo_setup_sw()
3.	nvgpu_fifo_setup_sw_common()
4.	nvgpu_channel_init_support()
5.	gops_fifo.reset_enable_hw()
6.	nvgpu_runlist_get_runlists_mask()

Jira NVGPU-6222

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I2ef150d41695afca303f1e083f559d31895ba602
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2482062
GVS: Gerrit_Virtual_Submit
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Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-03-02 19:31:37 -08:00
Vedashree Vidwans
f4e750cfb2 gpu: nvgpu: name nvgpu_fifo internal structures 
Add names for internal structures in nvgpu_fifo struct. This will clear
"anonymous" struct names from doxygen.

Jira NVGPU-6179

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: I9c34ff5e0626a3b28febe7d0cfdb297eb6785427
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2467531
(cherry picked from commit 82a6fdd73fbca1e65315a5e13bcd0fd4311da583)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480573
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2021-03-02 19:31:32 -08:00
Vedashree Vidwans
4de7b8bbd1 gpu: nvgpu: update doxygen for common.fifo 
Modify doxygen comments
- to add more information
- correct spelling mistakes
- update formatting

Jira NVGPU-6179

Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Change-Id: If0a075b8875c8f5aee1d9710e7348e843a457534
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2467530
(cherry picked from commit b367d3d0ea7f92b722aebdc8cf6018979fe74c47)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480583
GVS: Gerrit_Virtual_Submit
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 2021-03-02 19:31:25 -08:00
Vedashree Vidwans
12bbff3f5a gpu: nvgpu: update doxygen for common.fifo 
Update function return and return value description for
nvgpu_channel_open_new and nvgpu_engine_setup_sw as per review comments.

Jira NVGPU-6179

Change-Id: Ie9a9c7c3918f22071173ca8b51dee49f3e405df6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2471070
(cherry picked from commit cb8ac4e09f3a4803e967987afa2c55d78235149d)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480565
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2021-03-02 19:31:20 -08:00
Seshendra Gadagottu
ca636eaeb7 gpu: nvgpu: gops: mc: add doxygen for ltc_isr 
Add doxygen for mc.ltc_isr, since it is getting called
from fusa code.

Jira NVGPU-6182

Change-Id: I1995cb6a2caef11f0b982b76b5dcd8d809d78a44
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
(cherry picked from commit 8ddc5e9dbbe7d711baafe1e824111010fcc969fb)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488417
GVS: Gerrit_Virtual_Submit
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2021-03-01 22:15:35 -08:00
Seshendra Gadagottu
d6b49345cd gpu: nvgpu: init: nvgpu_check_gpu_state description update 
Update nvgpu_check_gpu_state function description to
reflect it's functionality.

Jira NVGPU-6182

Change-Id: I650098b04e5134cfcada37a99fbe505f3f621855
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
(cherry picked from commit c972d2925bf020270179abc0545335cbdc69113e)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488415
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-03-01 22:15:29 -08:00
ajesh
07cd0697ad gpu: nvgpu: add doxygen update for posix unit 
Add range value and other related details for various
Posix functions.

JIRA NVGPU-6285

Change-Id: I2bee40cc81075ef63bdaaf4ea1d955bbeb9dabd3
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2479890
(cherry picked from commit 0b74c24db8adae83a404aa08b728597b8ca19068)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2486852
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-02-27 04:19:10 -08:00
Lakshmanan M
1438689a89 gpu: nvgpu: Add api to query the availability of multi GR support 
* Added a new api(nvgpu_gr_is_multi_gr_enabled()) to query the
  availability of multi GR support when MIG is enabled.

JIRA NVGPU-5650

Change-Id: I3f8c29db966afb8d72021a093e009492f134ec9d
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488399
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Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-02-25 14:42:22 -08:00
Alex Waterman
5bf229dcd5 gpu: nvgpu: Rename runlist_id to id 
Rename the runlist_id field in struct nvgpu_runlist to just id.
The runlist part is redundant given that this id is already in
'struct nvgpu_runlist'.

Change-Id: Ie2ea98f65d75e5e46430734bd7a7f6d6267c7577
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470306
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-02-19 15:16:46 -08:00
Alex Waterman
bd1b395b5c gpu: nvgpu: Update runlist_id in TSG 
Update the runlist_id field in struct tsg to now be a pointer to
the relevant runlist. This further cleans up the rampant use of
runlist_ids throughout the driver.

Change-Id: I3dce990f198d534a80caa9ca95982255dcf104ad
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2470305
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-02-19 15:16:41 -08:00
Seeta Rama Raju
8d6b654afb gpu: nvgpu: compile out bios dependency from safety build 
- bios not supported for safety, so removing all bios dependencies like
  inclusion of bios header file and gops_bios structure from safety build.

JIRA NVGPU-6302

Change-Id: I47c0be043dc2542ed34e5ef6d65b75ce8b57d276
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2456059
(cherry picked from commit c7554856aac4745038f8ca802a3e0b3a9cbb7f3c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2481700
Reviewed-by: Prateek Sethi <prsethi@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-02-19 05:46:32 -08:00
Seshendra Gadagottu
5bd547f0db gpu: nvgpu: bus: update doxygen for BVEC checks 
Update doxygen to have boundary value check info in
bus unit.

Jira NVGPU-6183

Change-Id: Idab12a6fdddcef016405e4a0fd9369bc6430cba1
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
(cherry picked from commit 90a3fd422cfeda7305127949e28a16fc096f5e11)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2486001
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-02-18 23:44:35 -08:00
Seshendra Gadagottu
c021b18fb1 gpu: nvgpu: fb: update doxygen for BVEC checks 
Update doxygen to have boundary value check info for
input params in common.fb.

Jira NVGPU-6183

Change-Id: Ic07a7688c457c68ba7e9ef96ca8b3bf4145b8236
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
(cherry picked from commit 84f7954eaf499f38af8590a4a1309e0c1f7448bf)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2485995
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2021-02-18 23:44:26 -08:00
Seshendra Gadagottu
f5b6c012cb gpu: nvgpu: therm: update doxygen for BVEC checks 
Update doxygen to have boundary value check info for
init_elcg_mode HAL.

Jira NVGPU-6183

Change-Id: Id0ebb8076a8a65319e40129308ded6ef6466c647
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2481046
(cherry picked from commit 89564f5d7f5371c35734c0eec5ad70edd71e3c17)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483098
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-02-18 23:43:26 -08:00
prsethi
ed739cdba1 gpu: nvgpu: update doxygen for clock unit 
Patch adds doxygen for get_maxrate

Jira NVGPU-6258

Change-Id: I7697134ca693bc14562c53b88e9aa2d44e871c9f
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480512
(cherry picked from commit 610d52755f69cf74f74c1cb8e04985184f7f842c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483391
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-02-17 11:12:27 -08:00
prsethi
8d55f14fc9 gpu: nvgpu: doxygen update for unit os_utils 
Add range value details for various os_utils functions.

Jira NVGPU-6258

Change-Id: Ib930a24d2a4b8e98520d87fcc2f48bef81d26fbd
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2480205
(cherry picked from commit 210e1dd5360d29cad1a432e8de48669d51de134c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2483388
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-02-17 11:12:19 -08:00
Deepak Nibade
a1cbe60bc0 gpu: nvgpu: fix common.gr doxygen typos 
Jira NVGPU-6180

Change-Id: I499634aa407404474a6d3d7d3dfc6271eda21007
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2473441
(cherry picked from commit bdfb68b965b76b216e3a9782ef7f0d1f6cda2df0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2478885
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-02-02 23:34:32 -08:00