Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Fix 8.2 violation for not specifying parameter name in prototype of
secure_alloc().
Fix 21.3 & 21.8 violations for using reserved names "free" and "exit."
Fix 8.6 and 21.2 violations for __gk20a_do_idle() and
__gk20a_do_unidle() by renaming the functions and wrapping them in a
missing #ifdef CONFIG_PM.
Fix 5.7 violation for reusing "class" as parameter name when already
defined as a struct.
JIRA NVGPU-3343
Change-Id: I976e95a32868fa0a657f4baf0845a32bd7aceb9e
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117913
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Check return value of below function and add void to ignore
the return value
update_gp_get
Rename
nvgpu_get_gp_free_count -> nvgpu_channel_update_gpfifo_get_and_get_free_count
nvgpu_gp_free_count -> nvgpu_channel_get_gpfifo_free_count
JIRA NVGPU-3388
Change-Id: I6e2265882c1f34e3bb47eaeac7a2c5a9fbe9b4eb
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2115784
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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This fixes MISRA rule 4.7 violations in the function nvgpu_vm_map(). The
violations were caused by trying to use ERR_PTR() to return error
information. Rather than try to return errors in a pointer, just change
the API to return an int and pass the pointer the arguments.
JIRA NVGPU-3332
Change-Id: I2852a6de808d9203b8c7826e2b8211bab97ccd16
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114027
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix cert c violations in common.gr
CERT INT31-C: unsigned long to unsigned int without checking, it value
may result in lose or misintepreted data.
Casting the U64 data type define to U32 is causing certc violation.
To avoid this error, add define BITS_PER_BYTE_U32 as a U32 data type.
CERT EXP34-C: dereferencing null pointer "g".
Jira NVGPU-3411
Change-Id: I9eaf76bde967ee075244723c51239a7c85d09e96
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2118146
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 21.6 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:79:
misra_violation: Using function "snprintf".
Fix this by replacing snprintf with strncpy.
Add nvgpu_strnadd_u32 function to convert u32 to string
The function supports radix from 2 to 16.
Jira NVGPU-3333
Change-Id: Idee739dfdedeabb74d0d9f7d4cddd798445f0ee1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117019
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 10.1 violation is reported in nvgpu.common.mm.as
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/common/mm/as.c:69:
misra_violation: The expression "({...})" of non-boolean essential
type is being interpreted as a boolean value for the operator "!".
Fix this by adding an explicit cast to bool in is_power_of_2
macro.
Jira NVGPU-3333
Change-Id: I81e0110a6cd66088a5a39c63521efa41cbd90f48
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117018
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Allocate space at runtime for PMU RTOS fw struct, this helps
to reduce the size of nvgpu_pmu struct when LS_PMU support
is not required.
Allocation happens at pmu early init stage & will deinit at
remove_support stage.
JIRA NVGPU-1972
Change-Id: I1452b085f8d3a76e12186f788c2d999a8b4b202d
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111072
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA rule 10.1 requires that the operands shall not be of an
inappropriate essential type.
MISRA rule 10.3 requires that the values of an expression shall not be
assigned to an object with narrower essential type or of a different
essential type category.
MISRA rule 10.4 requires both the operands of an operator in which the
usual arithmetic conversions are performed to have the same essential
type category.
MISRA rule 10.8 requires that the value of a composite expression shall
not be cast to a different essential type category or a wider essential
type.
MISRA rule 21.2 forbids the usage of identifier names which start with
an underscore.
Fix violations of rules 10.1, 10.3, 10.4, 10.8 and 21.2 in types unit.
Jira NVGPU-3300
Change-Id: I3be4218ec8785aa9a116765233273097993baf0d
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117921
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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Below MISRA 21.1 violation is reported in nvgpu.common.utils
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be defined or undefined.
Below MISRA 21.2 violation is reported in nvgpu.common.utils
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/utils.h:56:
misra_violation: The NVGPU_GET_IP shall not be declared.
Fix this by renaming _NVGPU_GET_IP_ to NVGPU_GET_IP
Jira NVGPU-3327
Change-Id: Ied94d8c8d80c2b26df8e742c18255c3dc657d59a
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116696
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Below MISRA 8.6 violation is reported in nvgpu.common.mm.mm
${TEGRA_TOP}/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/mm.h:184:
declaration_with_no_definition: "nvgpu_init_mm_setup_hw" is
declared but never defined.
Fix this by removing nvgpu_init_mm_setup_hw declaration.
Jira NVGPU-3331
Change-Id: I78352c13e6c85cc67a261f62fe33eff64b5f6f5f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116707
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 20.7 requires macro paramaters to be wrapped in parantheses
when the parameter expands into an expression. Fix violations of rule
20.7 in atomic unit.
MISRA rule 10.3 prohibits the assignment of the value of an expression
to an object with narrower essential type or of a different essential
type category. Fix violations of rule 10.3 in atomic unit.
Jira NVGPU-3296
Change-Id: I087a6d15c5d03885aea29f22853e5bbde7880014
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116306
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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MISRA Rule 21.2 prohibits naming identifiers beginning with a double
underscore. This updates the function names __nvgpu_check_gpu_state()
and __gk20a_warn_on_no_regs() to comply.
JIRA NVGPU-3318
Change-Id: Ied2d168272a0f45fb8a08dda0e6fc798ebe3d22d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114656
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix CERT-C error for translating size from "unsigned long" to
"unsigned int".
Error: CERT INT31-C:
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:300:
cert_violation: Casting "size" from "unsigned long" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3409
Change-Id: I304fe39049d4f15361b23970ca2bcaecd2050ca3
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114536
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Fix following misra violations in pmu ipc units:
1. Rule 10.4: msg->msg.init.msg_type was being set value from enum.
converted corresponding value PMU_INIT_MSG_TYPE_PMU_INIT to u8.
Other conversions from signed to unsigned. Conversion of the
enum PMU_RC_MSG_TYPE_UNHANDLED_CMD to unsigned value.
2. Rule 10.6: casted msg->hdr.size to U32 wherever required.
3. Rule 10.7: same as above.
4. Rule 13.5: nvgpu_timeout_expired() has side-effects of updating
the timer counts. Using it as first operand of && in if clause.
5. Rule 16.4: added non-empty default clause to switch.
6. Rule 17.7: return value of nvgpu_pmu_vidmem_surface_alloc,
nvgpu_falcon_copy_to_dmem, nvgpu_pmu_lsfm_int_wpr_region,
nvgpu_timeout_init, pmu_init_perfmon, pmu_handle_event,
pmu_response_handle and memset is handled.
7. Rule 2.2: removed unnecessary initialization of local variable.
JIRA NVGPU-3273
Change-Id: Ie5a53bcdf0d138cb02867a09dc42195449e146a0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112619
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Below MISRA 5.7 violation is reported in common.gr.obj_ctx unit
nvgpu/drivers/gpu/nvgpu/common/gr/obj_ctx.c:68:
identifier_reuse: Identifier "class" is already used to represent a type.
nvgpu/drivers/gpu/nvgpu/include/nvgpu/nvgpu_common.h:27:
type_declaration: Declaring a type with identifier "class".
Fix this by changing variable name "class" to "class_num"
Jira NVGPU-3407
Change-Id: Ic19aa4f1ff0adbe5d946ca18a165975e3af699fa
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114364
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Below MISRA 17.7 violation is reported in common.gr.fs_state unit
nvgpu/drivers/gpu/nvgpu/common/gr/fs_state.c:121:
misra_c_2012_rule_17_7: The return value of a non-void function
"*g->ops.gr.init.rop_mapping" is unused
This hal need not return any error hence convert return type to void
map_tiles are always allocated before calling this hal hence no need
to check if they are allocated in this hal
Jira NVGPU-3407
Change-Id: Ic78946fcc7b4780208c416c444d33aea2db20bfc
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114361
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Modified PMU subunits init sequence as they required during PMU RTOS
initialize stage, function nvgpu_pmu_early_init() allocates space for
all its subunit & its default values for further usage during runtime,
and function nvgpu_pmu_init() performs setup for sub units & starts
PMU-RTOS boot.
Deinit of all sub units allocated space will handled as part of
remove_support stage & also, during init stage upon failure of
init/setup sequence.
JIRA NVGPU-1972
Change-Id: I3ead9f9bb9e9c1178a02fc99eeec276660477325
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110154
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
g->ops.pmu.pmu_elpg_statistics,
g->ops.pmu.pmu_pg_init_param,
g->ops.pmu.pmu_pg_supported_engines_list,
g->ops.pmu.pmu_pg_engines_feature_list,
g->ops.pmu.pmu_is_lpwr_feature_supported,
g->ops.pmu.pmu_lpwr_enable_pg,
g->ops.pmu.pmu_lpwr_disable_pg,
g->ops.pmu.pmu_pg_param_post_init,
g->ops.pmu.save_zbc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id,
struct pmu_pg_stats_data *pg_stat_data);
void nvgpu_pmu_save_zbc(struct gk20a *g, u32 entries);
bool nvgpu_pmu_is_lpwr_feature_supported(struct gk20a *g,
u32 feature_id);
JIRA NVGPU-3209
Change-Id: I6db9b43c7c4a5054720a72487302b740b091044d
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110963
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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MISRA Rule 11.2 doesn't allow conversion to or from an incomplete type
pointer, as it may result incorrect point alignment and may further lead
to undefined behavior.
MISRA Rule 16.x requires all switch statements to be well-formed with
terminating break statement for every switch-clause.
This patch fixes 11.2 and 16.x violations in common.mm.nvgpu_mem.
Jira NVGPU-3339
Change-Id: I002393cc64d44826e6954d1bf6af71bd569e862f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2113096
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Some functions are not accessing hardware directly
but are being called using HAL ops: For example
.pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc,
.pmu_perfmon_start_sampling = nvgpu_pmu_perfmon_start_sampling_rpc,
.pmu_perfmon_stop_sampling = nvgpu_pmu_perfmon_stop_sampling_rpc,
.pmu_perfmon_get_samples_rpc = nvgpu_pmu_perfmon_get_samples_rpc,
These were being called by:
g->ops.pmu.pmu_init_perfmon,
g->ops.pmu.pmu_perfmon_start_sampling,
g->ops.pmu.pmu_perfmon_stop_sampling,
g->ops.pmu.pmu_perfmon_get_samples_rpc
Change the function access by using sw ops, like:
Create new functions:
int nvgpu_pmu_perfmon_init(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_start_sampling_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_stop_sampling_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
int nvgpu_pmu_get_samples_rpc_perfmon(struct gk20a *g,
struct nvgpu_pmu *pmu, struct nvgpu_pmu_perfmon *perfmon);
and based on hardware chip call the chip specific
perfmon sw init function: nvgpu_gv11b_perfmon_sw_init() and
nvgpu_gv100_perfmon_sw_init() and assign the sw ops for perfmon
JIRA NVGPU-3210
Change-Id: I2470863f87a7969e3c0454fa48761499b08d445c
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109899
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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- To enable FECS trace support, nvgpu should set the MSB
of the read pointer (MAILBOX1).
- The ucode will check if the feature is enabled/disabled
before writing a record into the circular buffer. If the
feature is disabled, it will not write the record.
- If the feature is enabled and the buffer is not allocated,
HW will throw a page fault error.
Bug 2459186
Change-Id: I71daf6fdb1bb67974f6e51e091f868cb08d3b0bf
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2111028
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