gm20b_pbdma_handle_intr is only initializing pbdma_status
when either pbdma_intr_0 or pbdma_intr_1 is pending.
This could lead to using non-initialized chsw_status in
gv11b_fifo_preempt_poll_pbdma, and causing unexpected
failures in unit tests.
Read pbdma_status before checking for pbdma interrupts,
to make sure pbdma_status contains valid data.
Jira NVGPU-4887
Change-Id: If1bdb24ae04b58e85e4217c9c0854c01ca65525b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2279111
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This patch removes dependency between pmu.clk and hal.clk.
Below is the implementation.
*Init the clk domains inside pmu.clk unit.
*Set this in a member variable and send it to hal.clk unit
*Use this to determine the valid clock domains and read the
monitor registers for each valid domains.
*Return the domain with error code.
*With this all the clk domain data is removed from hal.clk and
only pmu.clk uses it as it owns it.
JIRA NVGPU-4491
Change-Id: Ie57b2472cfaacfd2ce43ac7f95702bd95fb8bbaa
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2272416
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To achieve permanent fault coverage, the CTAs launched by
each kernel in the mission and redundant contexts must execute on
different hardware resources. This feature proposes modifications
in the software to modify the virtual SM id to TPC mapping across
the mission and redundant contexts. The virtual SM identifier to TPC
mapping is done by nvgpu when setting up the patch context.
The recommendation for the redundant setting is to offset the
assignment by one TPC, and not by one GPC. This will ensure that both
GPC and TPC diversity. The SM and Quadrant diversity will happen
naturally. For kernels with few CTAs, the diversity is guaranteed
to be 100%. In case of completely random CTA allocation,
e.g. large number of CTAs in the waiting queue, the diversity is
1 - 1/#SM, or 87.5% for GV11B, 97.9% for TU104.
Added NvGpu CFLAGS to enable/disable the SM diversity support
"CONFIG_NVGPU_SM_DIVERSITY".
This support is only enabled on gv11b and tu104 QNX non safety build.
JIRA NVGPU-4685
Change-Id: I8e3eaa72d8cf7aff97f61e4c2abd10b2afe0fe8b
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268026
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Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
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MISRA Advisory Directive 4.5 states that identifiers in the same
name space with overlapping visibility should be typographically
unambiguous.
The presence of both the roundup(x,y) and round_up(x,y) macros in
the posix utils.h header incurs a violation of this rule.
These macros were added to keep in sync with the linux kernel variants.
However, there is a key distinction between how these two macros
work in the linux kernel; roundup(x,y) can handle any y alignment while
round_up(x,y) is intended to work only when y is a power-of-two.
Passing a non-power-of-two alignment to round_up(x,y) results in an
incorrect value being returned (silently).
Because all current uses of roundup(x,y) and round_up(x,y) in
nvgpu specify a y value that is a power-of-two and the underlying
posix macro implementations assume as much, it is best to remove
roundup(x,y) from nvgpu altogether to avoid any confusion.
So this change converts all uses of roundup(x,y) to round_up(x,y).
Jira NVGPU-3178
Change-Id: I0ee974d3e088fa704e251a38f6b7ada5a7600aec
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2271385
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MISRA Advisory Directive 4.5 states that identifiers in the same
name space with overlapping visibility should be typographically
unambiguous.
In both the nvgpu_locate_pte_last_level() and gp10b_get_pde0_pgz()
routines this violation is raised because a variable used as
a for-loop index ('i') is ambiguous with a parameter that points
to a struct gk20a_mmu_level ('l').
To fix these violations the loop index 'i' is renamed to 'idx'.
Jira NVGPU-3178
Change-Id: I2cec904201075b48ab6ccfbd0ff6d7e9dcac2867
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2271456
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Following changes are done to common.top code and UT:
1.Change return type for device_info_parse_enum to void as it can never
return non-zero value.
- This is a private HAL and is only called by get_device_info HAL.
- It gets called only for table entry with entry type = enum.
- So there is no error path left.
This helps remove unnecessary branches and get better branch coverage
2. Check if the data parsing function pointers are not NULL before
parsing the device tree. Return error if there are no functions
to interpret the device_info table registers. Add checks for same in
unit test test_get_device_info().
JIRA NVGPU-2204
Change-Id: I8833da7aa58b070d19b50ee17f64362f301bd792
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2269603
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MISRA rule 11.2 doesn't allow conversions of a pointer from or to an
incomplete type. These type of conversions may result in a pointer
aligned incorrectly and may further result in undefined behavior.
This patch addresses rule 11.2 violations related to pointers to and
from struct nvgpu_sgl. This patch replaces struct nvgpu_sgl pointers by
void pointers.
Jira NVGPU-3736
Change-Id: I8fd5766eacace596f2761b308bce79f22f2cb207
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267876
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gv11b_mm_mmu_fault_handle_mmu_fault_common was calling
gv11b_mm_mmu_fault_handle_mmu_fault_ce for any mmu_engine_id
greater than gmmu_fault_mmu_eng_id_ce0_v().
This include GR engine on gv11b.
Check the range of mmu_fault_id for CEs instead, before
calling gv11b_mm_mmu_fault_handle_mmu_fault_ce.
Jira NVGPU-4511
Change-Id: I28a78872918dc97e0878ef4c116059eaf5d7fa7b
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2264975
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Device info data format has changed from gp10b to
gv11b, and MMU fault id was incorrectly decoded for GR engine.
Add gv11b_device_info_parse_data HAL to decode device info
data with correct field definitions.
Move gp10b device_info parse data to non-fusa, since
it is not used anymore in safety build.
Jira NVGPU-4511
Change-Id: I2b3f3b5fec977d63a9ad6cfd99c04f375cf997e8
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262217
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As a part of refactoring, we need to move the volt unit from perf to pmu
as it belongs there and also move the arbitor specific functions under
CLK_ARB as they will be removed from safety build.
This patch does the following
*Move volt struct from perf to pmu
*Move volt setup from pmu_pstate to volt
*Move clk freq related functions into CLK_ARB
NVGPU-4491
NVGPU-4492
Change-Id: I7180cd12bbf91cc4d2e79b6e2d71c16e494c8ff0
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2268215
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Add new unit test to cover gops.gr.init.ecc_scrub_reg HAL function
gops.gr.init.ecc_scrub_reg HAL can generate TIMEOUT errors which are
not returned to caller currently. Update this HAL to return int value
for error propagation.
Jira NVGPU-4458
Change-Id: I98f4d5af2ef17cc4301951fec4d660638c8ef72c
Signed-off-by: dnibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265456
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Clean up a couple of MISRA violations for functions which are not being
compiled in the safety build.
JIRA NVGPU-3873
Change-Id: Iaaf03c9590bc85d5d411b10363c23266df5630c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262191
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fbpa related functions are not supported on igpu safety. Don't
compile them if CONFIG_NVGPU_DGPU is not set.
Also compile out fb and ramin hals that are dgpu specific.
Update the tests for the same.
JIRA NVGPU-4529
Change-Id: I1cd976c3bd17707c0d174a62cf753590512c3a37
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2265402
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Removed BUG_ON statements from gm20b_pbdma_acquire_val, as
condition could never be true. The only overflow that can
happen is in nvgpu_safe_mult_u64.
Compute exponent by shifting timeout (in units of 1024 ns)
until it fits into mantissa. This removes the need to
compute most significant bits, and allows using hw definitions
for mantissa and exponent max values.
Jira NVGPU-3694
Jira NVGPU-4673
Change-Id: Iaf4b5aaafe5b4e759d4e447f76f05f81e201a584
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263650
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Add unit tests to cover the invalid falcon port access, falcon sw init
switch cases, nvgpu_falcon_set_irq, nvgpu_timeout_init failure branch
coverage.
Compile out the functions nvgpu_falcon_get_mem_size & falcon_bootstrap
as they are needed by LS PMU and VBIOS code. For iGPU safety the
falcon functions needing these will call the HAL APIs directly.
This way we avoid the unreachable code as well. Updated the
prototype of falcon bootstrap HAL API as that doesn't return
any error.
With these changes, we get 100% line coverage for common.falcon unit.
JIRA NVGPU-2214
Change-Id: I1fe653d97c1a6a1521d7da38f171928dda58c5b5
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258311
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PMU IRQs were not enabled assuming entire functionality for LS PMU.
Debugging early init issues of PMU falcon ECC errors triggered
during nvgpu power-on will be cumbersome if interrupts are not
enabled early. FMEA analysis of the nvgpu init path also
requires this interrupt be enabled earlier.
Hence, Enable the PMU ECC IRQ early during nvgpu_finalize_poweron.
pmu_enable_irq is updated to enable interrupts differently for
safety and non-safety. PMU interrupts disabling is moved out
of nvgpu_pmu_destroy to nvgpu_prepare_poweroff. Prepared new
wrapper API nvgpu_pmu_enable_irq.
PMU ECC init and isr mutex init is moved to the beginning of
nvgpu_pmu_early_init as for safety, ls pmu code path is
disabled. Fixed the pmu_early_init dependent and mc
interrupt related unit tests.
Update the doxygen for changed functions.
JIRA NVGPU-4439
Change-Id: I1a1e792d2ad2cc7a926c8c1456d4d0d6d1f14d1a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2251732
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pwr_csb slcg, blcg gating registers are covered by pmu slcg/blcg hence
its load functions are not used. Hence, delete the generated data and
functions. slcg, blcg ctxsw_firmware and pg_gr gating reglists are
null hence delete the generated data and functions.
JIRA NVGPU-2175
Change-Id: Ib04d9845331c9a287666d3b8c974e1d3b66a7677
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2263272
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- nvgpu_gr_ctx_load_golden_ctx_image() does not return any error, change
the return type to void
- Check for preemption modes greater than CILP in
nvgpu_gr_ctx_check_valid_preemption_mode
- Check if received class is valid or not in
nvgpu_gr_setup_set_preemption_mode
- Compile out entire nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode since
it is really not doing anything in safety
- Remove the switch statement in nvgpu_gr_obj_ctx_set_compute_preemption_mode
since it is not possible to receive any other value than supported.
Previous function calls ensure that input values are validated.
- nvgpu_gr_obj_ctx_commit_global_ctx_buffers() does not return any
error, change the return type to void
- gops.gr.init.preemption_state HAL is not needed in safety since it
only configures gfxp related timeout
- remove redundant call to gops.gr.init.wait_idle in
nvgpu_gr_obj_ctx_commit_hw_state. We trigger wait despite earlier
failure in same function call.
Jira NVGPU-4457
Change-Id: I06a474ef7cc1b16fbc3846e0cad1cda6bb2bf2af
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2260938
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Split GR ECC initialization into GPC/TPC and FECS ECC init as FECS ECC
errors during acr_construct_execute need to be reported and handled
hence FECS ECC counters are required to be initialized before
acr_construct_execute.
GPC/TPC ECC counters are dependent on the GR config that will be
initialized only after acr_construct_execute.
nvgpu_gr_intr_init_support is moved to nvgpu_gr_prepare_sw.
FECS ECC interrupt is enabled by default hence interrupt is not
enabled through gr_fecs_host_int_enable_r in nvgpu_gr_prepare_sw.
JIRA NVGPU-4439
Change-Id: Ifc9912f0578015a6ba1e9d38765c42633632b15f
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2261987
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Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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handle_tex_exception hal is not set for safety build. Add
CONFIG_NVGPU_HAL_NON_FUSA checking for that hal.
log_mme_exception hal is supported only for turing. Add
CONFIG_NVGPU_DGPU checking for that hal.
gr_intr_handle_class_error always return -EINVAL. Change the
return as void to avoid unwanted error checking.
nvgpu_gr_intr_get_channel_from_ctx function parameter curr_tsgid will
never be NULL based on the current call. Remove unwanted
(curr_tsgid != NULL) check from this function.
Jira NVGPU-4454
Change-Id: I165d1cc5f9e308dfb11d905b59151b44f63a31bb
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2259763
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Compile out the function mc_gp10b_log_pending_intrs() with the
CONFIG_NVGPU_NON_FUSA macro since it isn't used in the FUSA build.
JIRA NVGPU-2224
Change-Id: I5b2d465142be7d1bddf114c7374ced7b297c33d0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2257127
Reviewed-by: Automatic_Commit_Validation_User
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Compile out unused code in gr.falcon for safety build.
By default NVGPU_SEC_SECUREGPCCS is enabled in Safety build. Add
CONFIG_NVGU_GR_FALCON_NON_SECURE_BOOT checking with non secure code.
In gm20b_gr_falcon_wait_ctxsw_ready function watchdog timer value is
calculated based on clock rate, not needed for safety code.
Add CONFIG_NVGPU_HAL_NON_FUSE checking for unused code in that function.
gm20b_gr_falcon_gr_code_less_equal is the last op status we check.
SKIP or any other status following this will be failed in checking
for valid op status. So code reaching this function mean it is for
only for GR_IS_UCODE_OP_LESSER_EQUAL. So removing the checking for
opc_status != GR_IS_UCODE_OP_LESSER_EQUAL in this function
Jira NVGPU-4453
Change-Id: I156cac59f52779fa7f78052c1f0115d0e8f03bf9
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258768
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Minion Ucode is enabling HS Ucode Encyrption. Minion Ucode builds
will put out separate Debug-signed and Prod-signed Encrypted image
files. The driver will load prod image or debug image depending
on the setting of DEBUG fuse setting.
Add support to read the SCP_CTL_STAT register to differentiate
debug and prod boards and load correct binary accordingly.
Update the binary name to support two minion ucodes binaries in
the build.
JIRA NVLINK-283
Bug 2701677
Change-Id: I5348e9705708eeab4ce639b0721f10882d8970a7
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2258097
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MISRA Advisory Rule 4.4 states that sections of code should
not be commented out.
This change removes the following comment from gp10b_get_device_info():
} else { /* (entry == top_device_info_entry_engine_type_v()) */
JIRA NVGPU-3178
Change-Id: I0d5f0e9370a24b20c6e7487c92b956eb9e8a3048
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2256362
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* Updated types and added error checks
* Modified GR condition for ctxsw disable count
CERT-C error check was added to detect error on integer overflow
But below logic couldn't detect first overflow, so updated condition
INT_MAX < gr->ctxsw_disable_count --> it became true after overflow
So, we didn't detected in first overflow and lead to assert on enable
JIRA NVGPU-3400
Change-Id: I6b0265a464f8f19efa7b0761612c6e9ffb3bd2bd
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206282
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