In this CL, following ctxsw related code is moved to hal gr falcon.
1. gr_gk20a_wait_ctxsw_ready -> gm20b_gr_falcon_wait_ctxsw_ready
2. gr_gk20a_submit_fecs_method_op ->
gm20b_gr_falcon_submit_fecs_method_op
3. gr_gk20a_submit_fecs_sideband_method_op->
gm20b_gr_falcon_submit_fecs_sideband_method_op
Above functions are populated with following gr.falcon hals and called
from the current code as required:
int (*wait_ctxsw_ready)(struct gk20a *g);
int (*submit_fecs_method_op)(struct gk20a *g,
struct fecs_method_op_gk20a op, bool sleepduringwait);
int (*submit_fecs_sideband_method_op)(struct gk20a *g,
struct fecs_method_op_gk20a op);
Following static function also moved to gr_gk20a.c to hal gr falcon.
gr_gk20a_ctx_wait_ucode -> gm20b_gr_falcon_ctx_wait_ucode
JIRA NVGPU-1881
Change-Id: Icb4238dcacaf46ecfcada8bc8dcdeb68b6278bab
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085189
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new hal g->ops.gr.falcon.set_current_ctx_invalid() in hal.gr.falcon
unit to invalidate current_ctx by setting invalid flag in register
gr_fecs_current_ctx_r()
Use new hal in gr_gk20a_init_golden_ctx_image() instead of accessing the
register directly
Define the hal for all supported chips
Jira NVGPU-2961
Change-Id: I756dac505c661ea2754abdbf6934927d1b469be3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085032
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Moved enable/disable HALs from fifo to tsg:
- tsg.enable
- tsg.disable
gk20a_tsg_enable and gv11b_tsg_enable are moved to HAL,
since they are chip specific, even though they do not
directly access chip registers.
Removed vgpu_gv11b_tsg_enable as it was identical to
gv11b_tsg_enable.
Changed gv11b_fifo_locked_abort_runlist_active_tsgs and
gv11b_fifo_teardown_ch_tsg to use tsg.enable HAL instead
of calling directly gk20a_disable_tsg HAL implementation.
Jira NVGPU-2979
Change-Id: I721650c64dcf8cd158652e362292af45df43819f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083156
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Move handle_tex_exception hal function to hal.gr.intr
Move hal function for gm20b and gp10b chips.
Removed the null implementation in gv11b hal.
Modify ops->gr.handle_tex_exception call to
ops->gr.intr.handle_tex_exception
JIRA NVGPU-3016
Change-Id: Ifd88ab6f35301525f7a58e8ccf2f4796dda640bf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084387
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Code for secure/non-secure ctxsw booting spread across gr_gk20a.c
and gr_gm20b.c. With this change this code is move to gr falcon unit.
Ctxsw loading is now supported with 2 supported common functions:
1.Non secure boot:
int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g);
2.Secure boot:
int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g);
Now gr ops function "int (*load_ctxsw_ucode)(struct gk20a *g);" is moved to
gr falcon ops and in chip hals it is set with secure/non-secure booting.
Non-secure booting: nvgpu_gr_falcon_load_ctxsw_ucode support ctxsw loading
in 2 methods: bit-banging uode or booting with bootloader
A. Common and hal functions for non-secure bit-banging ctxsw loading:
Common: static void nvgpu_gr_falcon_load_dmem(struct gk20a *g) ->
Hals: void (*load_gpccs_dmem)(struct gk20a *g,i
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_dmem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Common: static void nvgpu_gr_falcon_load_imem(struct gk20a *g) ->
Hals: void (*load_gpccs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Other basic HALs:
void (*configure_fmodel)(struct gk20a *g); -> configure fmodel for ctxsw loading
void (*start_ucode)(struct gk20a *g); -> start running ctxcw ucode
B.Common and hal functions for non-secure ctxsw loading with bootloader
First get the ctxsw ucode using: nvgpu_gr_falcon_init_ctxsw_ucode, then
Common: static void nvgpu_gr_falcon_load_with_bootloader(struct gk20a *g)
void nvgpu_gr_falcon_bind_instblk((struct gk20a *g) ->
Hal: void (*bind_instblk)(struct gk20a *g, struct nvgpu_mem *mem, u64 inst_ptr);
Common: nvgpu_gr_falcon_load_ctxsw_ucode_segments ->
nvgpu_gr_falcon_load_ctxsw_ucode_header ->
nvgpu_gr_falcon_load_ctxsw_ucode_boot for both fecs and gpccs ->
Hals: void (*load_ctxsw_ucode_header)(struct gk20a *g, u32 reg_offset,
u32 boot_signature, u32 addr_code32, u32 addr_data32,
u32 code_size, u32 data_size);
void (*load_ctxsw_ucode_boot)(struct gk20a *g, u64 reg_offset, u32 boot_entry,
u32 addr_load32, u32 blocks, u32 dst);
Other basic HAL to get gpccs start offset:
u32 (*get_gpccs_start_reg_offset)(void);
C.Secure booting is support with gpmu and acr and with following additional
common function in gr falcon.
static void nvgpu_gr_falcon_load_gpccs_with_bootloader(struct gk20a *g) ->
nvgpu_gr_falcon_bind_instblk and nvgpu_gr_falcon_load_ctxsw_ucode_segments
Additional basic hals:
void (*start_gpccs)(struct gk20a *g);
void (*start_fecs)(struct gk20a *g);
Following ops from gr is removed, since it is not required to set by chip hals:
void (*falcon_load_ucode)(struct gk20a *g, u64 addr_base,
struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
Now this is handled by static common function:
static int nvgpu_gr_falcon_copy_ctxsw_ucode_segments( struct gk20a *g,
struct nvgpu_mem *dst, struct gk20a_ctxsw_ucode_segments *segments,
u32 *bootimage, u32 *code, u32 *data)
JIRA NVGPU-1881
Change-Id: I895a03faaf1a21286316befde24765c8b55075cf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083388
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new hal g->ops.gr.init.load_sw_bundle_init() in hal.gr.init unit
and move corresponding code from gk20a_init_sw_bundle()
Add this hal to all the supported chips
Move g->ops.gr.init_sw_veid_bundle() hal to hal.gr.init unit
Move definition of hal to gv11b chip file of hal.gr.init
Add this hal for gv11b/gv100/tu104
Move g->ops.gr.init_sw_bundle64() hal to hal.gr.init unit
Move definition of hal to tu104 chip file of hal.gr.init
Add this hal for tu104
Jira NVGPU-2961
Change-Id: I560c2ba95fb820275d5ccb46939007c58481ccbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083631
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fifo_pbdma_isr is moved to fifo_intr_gk20a HAL unit and renamed to
gk20a_fifo_pbdma_isr.
The pbdma specific handling part of the function
gk20a_fifo_handle_pbdma_intr is now separated into a top level HAL
function named handle_pbdma_intr. This HAL function is implemented
for GM20B and all the other architectures use the same implementation.
handle_pbdma_intr can accept NULL values for the parameters handled and
error_notifier.
gk20a_fifo_handle_pbdma_intr is called from
gv11b_fifo_poll_pbdma_chan_status and gk20a_fifo_pbdma_isr.
The call to gk20a_fifo_handle_pbdma_intr from
gv11b_fifo_poll_pbdma_chan_status doesn't progress to recovery.
Thus, the function gk20a_fifo_handle_pbdma_intr is removed to decouple
pbdma handling from recovery. gv11b_fifo_poll_pbdma_chan_status now
directly calls the HAL handle_pbdma_intr. For gk20a_fifo_pbdma_isr,
rc_type is used to proceed to recovery by calling
gk20a_fifo_pbdma_fault_rc.
gk20a_fifo_pbdma_fault_rc is changed to public from static.
Jira NVGPU-2950
Change-Id: I4f3597aca2317d4b745cd47bab9dd95c927160a9
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073535
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Move functions related to init_ctxsw_ucode to common
falcon from gr_gk20a.c. Modified code to call this new
function and modified function names in common falcon
to reflect new re-org.
JIRA NVGPU-1881
Change-Id: I389f5c902bfbec17cdb4b16840a5ba66f6b1e331
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081331
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Created gr falcon hal unit with moving following hal functions
from gr to gr falcon:
u32 (*fecs_base_addr)(void);
u32 (*gpccs_base_addr)(void);
void (*dump_stats)(struct gk20a *g);
u32 (*fecs_ctxsw_mailbox_size)(void);
u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g);
Modified chip hals to populate these new functions and related code
now refers to gr falcon hals.
Modified kernel headers to have following defs for
fecs/gpccs base address in gm20b/gp10b/gv11b/tu104:
static inline u32 gr_fecs_irqsset_r(void);
static inline u32 gr_gpcs_gpccs_irqsset_r(void);
Created base gm20b hals for fecs/gpccs_base_addr and
removed redundant gp106 related hals.
JIRA NVGPU-1881
Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081245
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Group gr falcon init related function together during init and
gr_reset sequence. This init sequence has following functions:
gr_gk20a_init_ctxsw
gr->ops.gr.init_ctx_state
gk20a_init_gr_bind_fecs_elpg
This init sequence will be moved to common gr falcon unit.
During gk20a_gr_reset sequence, instead of separate function calls
for fecs reglist operations, switched to helper function
gk20a_init_gr_bind_fecs_elpg. Also, this call needs to be protected
with g->can_elpg setting since it involves gpmu instblk.
JIRA NVGPU-1881
Change-Id: I74542ccb5f5ffce11374d30b8d5a5cc705feed9f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081244
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move g->ops.gr.commit_global_cb_manager() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_cb_manager()
Move hal definitions to gm20b/gp10b hal files appropriately
Add nvgpu_gr_config pointer to the parameter list of this hal so that
it does not have to dereference struct gr_gk20a in hal.gr.init unit
Jira NVGPU-2961
Change-Id: Iaff476648fa6abdf5a79be500f65a40eb90c0b08
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.commit_global_attrib_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_attrib_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b/gv11b hal files appropriately
Jira NVGPU-2961
Change-Id: I5437a190a9e027997f63ef0e741d99e6bbebab3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077218
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.commit_global_pagepool() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_pagepool()
Also move g->ops.gr.pagepool_default_size() hal to
g->ops.gr.init.pagepool_default_size()
Add global_ctx boolean flag as parameer to
g->ops.gr.init.commit_global_pagepool() to distinguish between
committing global pagepool v/s ctxsw pagepool buffers
Remove register header accessors from gr_gk20a_commit_global_ctx_buffers()
and move them to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Remove g->ops.gr.pagepool_default_size() hal for gv11b since gv11b can
re-use gp10b hal
Jira NVGPU-2961
Change-Id: Id532defe05edf2e5d291fec9ec1aeb5b8e33c544
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Delete apply_ctxsw_timeout_intr ops and add
ctxsw_timeout_enable ops
Move chip specific sched_error and ctxsw_timeout
functions to hal/fifo/fifo_intr_* and hal/fifo/ctxsw_timeout_*
Add nvgpu_rc_ctxsw_timeout function under common/rc/rc.c
Do not check ctxsw timeout for channels that are no more
bound to tsg.
JIRA NVGPU-1312
Change-Id: Ide977fb60b3b72a27d9f22873f7a416c3bd1181d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075734
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Move init_gpc_mmu hal to hal.gr.init and update the
g->ops.gr.init_gpc_mmu call as g->ops.gr.init.gpc_mmu
Add new hal, pes_vsc_stream which will enable the master bit to
take floorsweep into consideration.
Modify the disable_rd_coalesce hal as su_coalesce hal and
set_rd_coalesce call as lg_coalesce hal and move to hal.gr.init
su_coalesce hal function touches only the surface read coalesce bit.
lg_coalesce hal function touches only the lg read coalesce bit.
JIRA NVGPU-2951
Change-Id: Ifc5e36f7e75d3b74142a83a3c78a9cb2b81752eb
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079532
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Create interrupt hal unit under hal.gr.intr.
This holds the interrupt and exception related hals.
Move enable_exceptions and enable_gpc_exceptions hal functions to
hal.gr.init location.
Modify enable_exceptions hal to pass gr->config and enable or disable
parameters.
Modify enable_gpc_exceptions to pass gr->config parameter.
Add new hal function enable_interrupts with enable or disable parameter
This hal helps to enable and disable the gr interrupts as needed.
gr init calls that use these hals are modified to
g->ops.gr.intr.enable_exceptions
g->ops.gr.intr.enable_gpc_exceptions
JIRA NVGPU-3016
Change-Id: Ib62f8bf0b5289b815c8eff4d32a47387f24af51b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077857
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Move g->ops.gr.commit_global_bundle_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_bundle_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Jira NVGPU-2961
Change-Id: I6358dce963857402aa1d4d5606bf75398b9be83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077216
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.get_global_ctx_cb_buffer_size() and
g->ops.gr.get_global_ctx_pagepool_buffer_size() hals to hal.gr.init
unit
Move corresponding hal definitions to hal.gr.init unit
Jira NVGPU-2961
Change-Id: Ifff3e2073f6d9bca5b37244f7e107bad885e7ca7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077215
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Moved following ltc related data to struct nvgpu_ltc
and has a reference to it from struct gk20a:
struct nvgpu_spinlock ltc_enabled_lock;
u32 max_ltc_count;
u32 ltc_count;
u32 slices_per_ltc;
u32 cacheline_size;
Added function remove_support for ltc and it is called
during nvgpu remove sequence.
Added following helper functions in ltc.h:
u32 nvgpu_ltc_get_ltc_count(struct gk20a *g);
u32 nvgpu_ltc_get_slices_per_ltc(struct gk20a *g);
u32 nvgpu_ltc_get_cacheline_size(struct gk20a *g);
Removed redudnant ltc.init_fs_state call from vgpu init
sequence since it is getting called from nvgpu_init_ltc_support.
NVGPU-2044
Change-Id: I3c256dc3866f894c38715aa2609e85bd2e5cfe5a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2073417
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Remove below variables from struct gr_gk20a
u32 bundle_cb_default_size;
u32 min_gpm_fifo_depth;
u32 bundle_cb_token_limit;
u32 attrib_cb_default_size;
u32 alpha_cb_default_size;
u32 attrib_cb_gfxp_default_size;
u32 attrib_cb_gfxp_size;
u32 attrib_cb_size;
u32 alpha_cb_size;
Instead add below hals in hal.gr.init unit to get all of above sizes
u32 (*get_bundle_cb_default_size)(struct gk20a *g);
u32 (*get_min_gpm_fifo_depth)(struct gk20a *g);
u32 (*get_bundle_cb_token_limit)(struct gk20a *g);
u32 (*get_attrib_cb_default_size)(struct gk20a *g);
u32 (*get_alpha_cb_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_default_size)(struct gk20a *g);
u32 (*get_attrib_cb_gfxp_size)(struct gk20a *g);
u32 (*get_attrib_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_alpha_cb_size)(struct gk20a *g, u32 tpc_count);
u32 (*get_global_attr_cb_size)(struct gk20a *g, u32 max_tpc);
Define these hals for all gm20b/gp10b/gv11b/gv100/tu104 chips
Also add hal.gr.init support for gv100 chip
Remove all accesses to variables from struct gr_gk20a and start using
newly defined hals
Remove below hals to initialize sizes since they are no more required
g->ops.gr.bundle_cb_defaults(g);
g->ops.gr.cb_size_default(g);
g->ops.gr.calc_global_ctx_buffer_size(g);
Also remove definitions of above hals from all the chip files
Jira NVGPU-2961
Change-Id: I130b578ababf22328d68fe19df581e46aebeccc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077214
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- Make a new structure: nvgpu_pmu_pg for PG unit
- This new struct combines all PG unit variables like
elpg_stat, elpg_refcnt, pg_init etc. into one
structure as a part of PG unit refactoring.
- Use pmu_pg struct to access all PG variables.
- Eg: &pmu->pmu_pg.elpg_mutex, &pmu->pmu_pg.pg_mutex
and so on.
NVGPU-1973
Change-Id: I9973072826f4089f6315827bce49fa30dbcbcdda
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071306
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Add nvgpu_tsg_set_error_notifier function for setting error_notifier
for all channels of a tsg.
Add nvgpu_tsg_timeout_debug_dump_state function for finding if
timeout_debug_dump is set for any of the channels of a tsg.
Add nvgpu_tsg_set_timeout_accumulated_ms to set
timeout_accumulated_ms for all the channels of a tsg.
JIRA NVGPU-1312
Change-Id: Ib2daf2d462c2cf767f5a6e6fd3436abf6860091d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077626
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new hal fifo_access to control the gr_gpfifo_ctl_r register to
enable or disable the access bit and semaphore access bit.
g->ops.gr.init.fifo_access function call with true or false
parameter to enable or disable the fifo_access.
JIRA NVGPU-2951
Change-Id: I67ad7ce9f176d7ce347e8acb425f7a4bb9e088ca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077705
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
