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2534 Commits

Author SHA1 Message Date
smadhavan
d3509af0f5 gpu: nvgpu: add next-core selection flag for acr 
NVGPU_ACR_NEXT_CORE_ENABLED indicates which core to
use for acr bootstrap. This flag will be set based on PMU
and GSP core selection fuses in case of non-safety
and safety builds respectively

Change-Id: Id8daca20ba56648c1d7074ea2dd2384739c88704
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2455895
Reviewed-by: svcguardwords <svcguardwords@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
tkudav
05e3482106 gpu: nvgpu: Enhance doxygen for common.ptimer APIs 
Add details about the purpose served by the common.ptimer APIs.

JIRA NVGPU-6235

Change-Id: I4e4716135649aa611646e63c1b4e9b37eacde60b
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2456005
(cherry picked from commit 7b8907a0e8445d7b97fd0fdd2ca763e039b5893c)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457621
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
tkudav
2ee6a0f554 gpu: nvgpu: Add details to common.class APIs 
Add more details about the purpose served by the common.class
APIs.

JIRA NVGPU-6244

Change-Id: I16e4d62175a05ff6f71b7148d1ea7874d1fe01ac
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2455939
(cherry picked from commit 5ad0a0b6fdc1b68fea6570bf434bf479f8bd05ea)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457393
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
tkudav
882e418d1b gpu: nvgpu: Add details to common.fbp API retval 
Add doxygen comments to describe the possible return values from
common.fbp API in case of error.

JIRA NVGPU-6237

Change-Id: Ifff997f18d61f855fc83914fbbe4ea09c5fafbaf
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2455034
(cherry picked from commit 5d646ef5d3f18c91f2d60c0abf4cecb84154bf4a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457392
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
mkumbar
c62cfa2efb gpu: nvgpu: get PMU NEXT core irqmask 
-Add new PMU ops to get NEXT core irq mask
-Add support to handle NEXT core interrupt request.

Bug 200659053
Bug 3199589

Change-Id: I78738f074a425f8934bbba28bf6996eeec7ab05a
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2457077
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Antony Clince Alex
48265944c4 gpu: nvgpu: update doxygen for common.ecc unit 
Updated doxygen comments for common.ecc unit functions to better
describe return values.

Jira NVGPU-6248

Change-Id: I36e94d7e41e28072c4bb0699024724e25fe3b35c
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2456423
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:48 -06:00
mkumbar
ee7cdf1fff gpu: nvgpu: Add multiple signature parsing support for ACR 
- Add multiple signature parsing support for ACR using ucode version
fuse value.
-Signature file contains multiple signatures and need to select
one signature using ucode version to validate the ucode.

Bug 200673810

Change-Id: I39007d4e2e8bb959caf278275d153b633a775def
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2455171
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
Lakshmanan M
d85588c9a3 gpu: nvgpu: update doxygen for some mm public functions 
This patch updates the doxygen for following mm functions that
are used by other sub-units in GPU to mm unit.

1) Initialize MM
2) GMMU Map
3) GMMU Unmap
4) VM Init
5) VM Map
6) VM UnMap

JIRA NVGPU-5932

Change-Id: Ia4ff43d7afc96f853d69c8cf88dfcb27a9bc3548
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2454483
Reviewed-by: svcguardwords <svcguardwords@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Joshua Widen
60f44506a3 Revert "gpu: nvgpu: get PMU NEXT core irqmask" 
This reverts commit 4ff427c51619cecdcc74fdbb388d82421cf45655.

Reason for revert: Testing for regression seen in GVS.

Bug 3198736

Change-Id: If12da341c3e13907bdcbb778c8fb4118cd5e3803
Signed-off-by: jwiden <jwiden@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2456791
Reviewed-by: svcguardwords <svcguardwords@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
dt
ea5fe7c66c gpu: nvgpu: doxygen: update return values 
This is updating return values of some APIs.

JIRA NVGPU-6259

Change-Id: Ic54dd7988b0704cd845f977add83ffbadf2424fb
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2453981
(cherry picked from commit 28b1aca455d9ee11455b92a3a07c92487e9f00e6)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2455954
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcguardwords <svcguardwords@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
mkumbar
8284832300 gpu: nvgpu: get PMU NEXT core irqmask 
-Add new PMU ops to get NEXT core irq mask
-Add support to handle NEXT core interrupt request.

Bug 200659053

Change-Id: I8b1c9b9d74ed59b4130fea712f970b4a31a8b4fe
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2429042
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Lili Sang
3f0ea98b73 gpu: nvgpu: Add get_gr_context support for Linux. 
Implement the feature of retrieving gr context contents for all chips.
Two IOCTLs, NVGPU_DBG_GPU_IOCTL_GET_GR_CONTEXT_SIZE and _GET_GR_CONTEXT,
are added.

Bug 3102903

Change-Id: If11006f4e294f190785a2c3159ca491b9f3b5187
Signed-off-by: Lili Sang <lilis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2449183
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Chris Johnson <cwj@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
Rajesh Devaraj
bfa712ab3d gpu: nvgpu: update doxygen for error reporting functions 
This patch updates the doxygen for error reporting functions that
are used to report errors from sub-units in GPU to SDL unit.

JIRA NVGPU-6149

Change-Id: I250f5775c2aac44239d49625d9c30c838adcbb1f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2452643
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Deepak Nibade
b23a114c63 gpu: nvgpu: ensure all perfmon writes are complete after reset 
gr_gv100_reset_hwpm_pmm_registers() writes a bunch of registers in
sys/gpc/fbp chiplets to reset perfmons. To ensure all the writes have
completed it is necessary to readback each chiplet's PRI fence register.

Add and use new HAL g->ops.priv_ring.read_pri_fence() to achieve this.

Implement the HAL for gv11b in new source code file
hal/priv_ring/priv_ring_gv11b.c.

Bug 2510974
Jira NVGPU-5360

Change-Id: If4dd61cb4265422e8c2d16884790eb0fe7f2c103
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2453631
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
Jon Hunter
8c94013c4d gpu: nvgpu: Add host1x support 
Add support for the upstream host1x driver with the 'Host1x/Tegra UAPI'
series [0] applied. The host1x support is only enabled if the kernel
configuration variable CONFIG_TEGRA_HOST1X_NEXT is set. Please note that
the initial implementation only supports Tegra194.

[0] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=206532

Bug 3156385

Change-Id: If531a8b866b48ba5a2af021756a4b5d158b8d59a
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2429981
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Richard Zhao
7364c311fa gpu: nvgpu: vgpu: add ctxsw buffer rtvcb support for gfxp 
gfxp needs to set a different rtv buffer which is larger than the
default rtv global buffer.

Jira GVSCI-4732

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I1383b6b0abff40904133a7b32559899f9259ae89
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2448161
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
Deepak Nibade
d584294545 gpu: nvgpu: set preemption mode for specific GR instance 
Pass gr_instance_id to function nvgpu_gr_setup_set_preemption_mode()
which picks up correct nvgpu_gr struct pointer based on instance id.

nvgpu_gr_get_cur_instance_ptr() is not needed in this special case
since there is no PGRAPH register programming required to set preemption
mode. All writes/updates are done on context image.

Also fix unit tests accordingly to always select 0th GR instance.

Jira NVGPU-5648

Change-Id: I46eff816d5a4afe784bf75b64ee9d698c77eb64a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435468
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Lakshmanan M <lm@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
Lakshmanan M
883c12529a gpu: nvgpu: Add multi GR reset support for MIG 
* Added multi GR reset/recovery support for MIG.
* Added a api to get the gr engine id using gr instance id.

JIRA NVGPU-5650
JIRA NVGPU-5653

Change-Id: I12ece75a4c33f0944f404121b54879e814dda6df
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2443644
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Lakshmanan M
613e1e704a gpu: nvgpu: Add recursive gr remap window support 
Added logic to support recursive gr remap window support using
thread id and recursive lock count.

JIRA NVGPU-5650
JIRA NVGPU-5647

Change-Id: I4fca4b776fa009d630ecea38947c45bfea048e41
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2443279
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:48 -06:00
Vedashree Vidwans
2386ddd038 gpu: nvgpu: modify pbdma.get_fc_target 
Modify pbdma.get_fc_target() to accept nvgpu_device pointer. This is
required for nvgpu-next.

JIRA NVGPU-6135

Change-Id: I8baa58c704ee32ee68e87915029ac2be2132d4a4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2440180
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:48 -06:00
David Ung
47c30eb80f gpu: nvgpu: Updated with generator headers 
Add pmu_idle_mask_1, pmu_idle_mask_2 and pmu_idle_mask_2_supp

Bug 2833620

Change-Id: I616ea584646c6affacc3df4c63ccff59d574ab52
Signed-off-by: David Ung <davidu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422614
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Richard Zhao
e8a356548e gpu: nvgpu: vgpu: add runlist_id to cmd TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX 
Server side needs channel runlist_id to do channel operations.

Jira GVSCI-8166

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: Ie51f7263851d24d95756bd60f29ba01fdc13ec49
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2438020
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
tkudav
9251621f5f gpu: nvgpu: Add GV11b missing register 
Add the missing register definition as highlighted by HAL
checker tool for GV11b.

Bug Bug 200604892

Change-Id: Id4127a8bdf8a866cdecd2457d327bed16530ef09
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2437691
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a252cc244a gpu: nvgpu: modify alloc_as ioctl to accept mem size 
- Modify NVGPU_GPU_IOCTL_ALLOC_AS and struct nvgpu_alloc_as_args to
accept start address and size of user memory. This allows configurable
address space allocation.
- Modify gk20a_as_alloc_share() and gk20a_vm_alloc_share() to receive
va_range_start and va_range_end values.
- gk20a_vm_alloc_share() initializes vm with low_hole = va_range_start,
and user vma size = (va_range_end - va_range_start).
- Modify nvgpu_as_alloc_space_args and nvgpu_as_free_space_args to
accept 64 bit number of pages.

Bug 2043269
JIRA NVGPU-5302

Change-Id: I243995adf5b7e0e84d6b36abe3b35a5ccabd7a37
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2385496
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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 2020-12-15 14:13:28 -06:00
tkudav
8303e93a60 gpu: nvgpu: Fix HAL checker mismatches for GV11B 
Add missing register definitions and set few HALs to NULL
as they are not relevant on GV11B.

Bug 200604892

Change-Id: I41aa87f50652eb1d0e99729838a58310cf586546
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2430348
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Richard Zhao
1d38ccbe47 gpu: nvgpu: vgpu: add support_sm_ttu to constants 
vgpu set flags according to support_sm_ttu returned by server.

Jira GVSCI-7553

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I877de0c1e7cfafef3df6619d3b076ad4e2d41227
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435945
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
69948919b7 gpu: nvgpu: make user vma start,end pde aligned 
Any PDE can allocate memory with a specific page size. That means memory
allocation with page size 4K and 64K will be realized by different PDEs
with page size (or PTE size) 4K and 64K respectively. To accomplish this
user vma is required to be pde aligned.
Currently, user vma is aligned by (big_page_size << 10) carried over
from when pde size was equivalent to (big_page_size << 10).

Modify user vma alignment check to use pde size.

JIRA NVGPU-5302

Change-Id: I2c6599fe50ce9fb081dd1f5a8cd6aa48b17b33b4
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2428327
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
00d1e10ff2 gpu: nvgpu: accept small_big_split in vm_init 
Currently, when unified address space is not requested, nvgpu_vm_init
splits user vm at a fixed address of 56G.
Modify nvgpu_vm_init to allow user to specify small big page vm split.

JIRA NVGPU-5302

Change-Id: I6ed33a4dc080f10a723cb9bd486f0d36c0cee0e9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2428326
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Lakshmanan M
7f9ce100f8 gpu: nvgpu: Dynamic VEID allocation support for MIG 
Removed veid_start_offset and max_veid_count_per_tsg
in mig static config.

JIRA NVGPU-5650
JIRA NVGPU-5647

Change-Id: I18315b957548aa8679f066a956125c4004773bd3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2435072
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2531107818 gpu: nvgpu: add zbc debug flag and prints 
Add debug prints in zbc table functions and add zbc debug flag to enable
manageable and modular debug prints related to zbc.

Bug 3156369

Change-Id: I0fd532ba6e4fd8dba125a2270ea70aaafdb2ed8e
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434170
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Antony Clince Alex
58f58d0097 gpu: nvgpu: print length of various ctxsw'ed register lists 
Add function nvgpu_netlist_print_ctxsw_reg_info to print the number of entries
present in each of the ctxsw'ed register lists.

Parse and populate GRCTX_REG_LIST_PERF_SYS_CONTROL register entires.

Jira NVGPU-6096

Change-Id: I7ea25c397a29793ede4eb0c408a5150a66de9e18
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2406379
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Richard Zhao
e367f670fd gpu: nvgpu: vgpu: add rtv circular buffer support 
If rtv hals are not null, ask server to map it as part of global
buffers.

Bug 3158160

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I56c030877219fc7a5a23e5c2715f98996b3c429f
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434876
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 2020-12-15 14:13:28 -06:00
Seeta Rama Raju
c1173d11df gpu: nvgpu: Fix for MISRA 10.1 violation 
- The expression "0" of non-boolean essential type is being interpreted
  as a boolean value for the operator "!"

JIRA NVGPU-6058

Change-Id: Iff9f81dcca5b4aa6636b688888010d5c964b93c1
Signed-off-by: Seeta Rama Raju <srajum@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417642
(cherry picked from commit dcc8cdbc09e3db3500be7a350295bee58808a62a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434188
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Lakshmanan M
55f472a0b7 gpu: nvgpu: Use logical GPC id mask 
Replaced logical GPC id mask instead of physical GPC id mask
for GPCCS falcon index mask programming required for multi-GR boot.

JIRA NVGPU-5650

Change-Id: I0fad31ea962d2f0bd069aa20deeea16ea29c307a
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2434229
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 2020-12-15 14:13:28 -06:00
mkumbar
8c402095db gpu: nvgpu: PMU NS bootstrap on next core 
PMU NEXT profile NS ucode load and bootstrap on next core

JIRA NVGPU-5215

Change-Id: I0d8f2ae7695d1d2fc830c4f6b324490d844adabe
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2411320
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 2020-12-15 14:13:28 -06:00
Rajesh Devaraj
97fac69162 gpu: nvgpu: update doxygen for ce 
The reporting of CE_NONBLOCK_PIPE interrupt to Safety_Services
has been removed already. This patch updates the corresponding
doxygen to maintain consistency.

JIRA NVGPU-6124

Change-Id: Id286a06d035c21e6b19a751c5a6642a562ad1fbc
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2428870
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Seema Khowala
04de14215b gpu: nvgpu: add NVGPU_SUPPORT_VPR check for vpr_resize 
VPR resize requires GPU to be reset (idle/unidle).
Allow GPU idle/unidle only when NVGPU_SUPPORT_VPR is true.

Bug 3122410
Bug 3144940

Change-Id: I08fb26a0d901922ee78c379982446616a880b9b3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2427470
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Tested-by: Vedashree Vidwans <vvidwans@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Deepak Nibade
c6aae8c049 gpu: nvgpu: use fixed address mapping for pma byte buffer 
Use fixed address mapping for pma byte buffer so that the address of
this buffer always fits in 32 bits.

This also requires to move unmap sequence to OS specific function since
different unmap API is now needed for linux and QNX.

Also call nvgpu_prof_free_pma_stream_priv_data() before
nvgpu_profiler_free_pma_stream() since former uses mm->perfbuf which
is released in later.

Bug 2510974
Jira NVGPU-5360

Change-Id: I398b0ca4f96527d6e09c9aacacb4b43c90f5bfc9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2424691
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
smadhavan
1a6a819709 gpu: nvgpu: make flcn read/write non chip specific 
Current falcon type agnostic readl/writel has the
name gk20a_falcon_read/writel and is static.
This change will:
* rename it as nvgpu_falcon_read/writel
* make it non static.
* replace corresponding usage.

JIRA NVGPU-5736

Change-Id: I825c55a1f7eb95d54584f20070984ddefa607fa1
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2421149
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
78fb67bb0b gpu: nvgpu: move fuse definitions to fuse.h 
Move common fuse definition macros to fuse.h. This will allow all
chip specific fuse files to use the common macros.

Jira NVGPU-6081

Change-Id: I85b5250809eef26a40f5b4b9bf6908dfa0d2be1f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2422892
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 2020-12-15 14:13:28 -06:00
Antony Clince Alex
c36752fe3d gpu: nvgpu: sim: make ring buffer independent of PAGE_SIZE 
The simulator ring buffer DMA interface supports buffers of the following sizes:
4, 8, 12 and 16K. At present, it is configured to 4K and it  happens to match
with the kernel PAGE_SIZE, which is used to wrap back the GET/PUT pointers once
4K is reached. However, this is not always true; for instance, take 64K pages.
Hence, replace PAGE_SIZE with SIM_BFR_SIZE.

Introduce macro NVGPU_CPU_PAGE_SIZE which aliases to PAGE_SIZE and replace
latter with former.

Bug 200658101
Jira NVGPU-6018

Change-Id: I83cc62b87291734015c51f3e5a98173549e065de
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420728
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 2020-12-15 14:13:28 -06:00
Prateek sethi
223baa5883 gpu: nvgpu: add support for ACB SLCG on gv11b 
Register list for ACB SLCG is auto generated with scripts.
Add HAL operations to enable/disable ACB clock gating.

Bug 200647909

Change-Id: I4be4c14cc072fcccd91031a5a40321f5ff11f549
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2420355
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 2020-12-15 14:13:28 -06:00
Peter Daifuku
a331fd4b3a gpu: nvgpu: pd_cache enablement for >4k allocations in qnx 
Mapping of large buffers to GMMU end up needing many
pages for the PTE tables. Allocating these one by one
can end up being a performance bottleneck, particularly
in the virtualized case.

This is adding the following changes:

 - As the TLB invalidation doesn't have access to mem_off,
   allow top-level allocation by alloc_cache_direct().
 - Define NVGPU_PD_CACHE_SIZE, the allocation size for a new slab
   for the PD cache, effectively set to 64K bytes
 - Use the PD cache for any allocation < NVGPU_PD_CACHE_SIZE
   When freeing up cached entries, avoid prefetch errors by
   invalidating the entry (memset to 0).
 - Try to fall back to direct allocation of smaller chunk for
   contiguous allocation failures.
 - Unit test changes.

Bug 200649243

Change-Id: I0a667af0ba01d9147c703e64fc970880e52a8fbc
Signed-off-by: dt <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2404371
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
94bc3a8135 gpu: nvgpu: rearch zbc code and update hals 
Update nvgpu_gr_zbc as:
struct nvgpu_gr_zbc {
   struct nvgpu_mutex zbc_lock;	/* Lock to access zbc table */
   struct zbc_color_table *zbc_col_tbl; /* SW zbc color table pointer */
   struct zbc_depth_table *zbc_dep_tbl; /* SW zbc depth table pointer */
   struct zbc_stencil_table *zbc_s_tbl; /* SW zbc stencil table pointer */
   u32 min_color_index;	/* Minimum valid color table index */
   u32 min_depth_index;	/* Minimum valid depth table index */
   u32 min_stencil_index;	/* Minimum valid stencil table index */
   u32 max_color_index;	/* Maximum valid color table index */
   u32 max_depth_index;	/* Maximum valid depth table index */
   u32 max_stencil_index;	/* Maximum valid stencil table index */
   u32 max_used_color_index; /* Max used color table index */
   u32 max_used_depth_index; /* Max used depth table index */
   u32 max_used_stencil_index; /* Max used stencil table index */
};

Add global struct nvgpu_gr_zbc_table_indices
struct nvgpu_gr_zbc_table_indices {
       u32 min_color_index;
       u32 min_depth_index;
       u32 min_stencil_index;
       u32 max_color_index;
       u32 max_depth_index;
       u32 max_stencil_index;
};

Currently, hw zbc table registers are written during both
gr_init_setup_sw() and gr_init_setup_hw().
- Modify nvgpu_gr_zbc_load_default_table() to
nvgpu_gr_zbc_load_default_sw_table() to only update sw copy of zbc table
during gr_init_setup_sw().
- Modify nvgpu_gr_zbc_load_table() to write zbc values stored in sw zbc
table to hw registers.

Re-structure zbc function as per zbc type i.e. color, depth and stencil.

Add gr.zbc.init_table_indices() hal to initialize zbc indices. Valid ZBC
table indices start from 1. HW indices start from 0 for color, depth and
stencil tables. Note that the corresponding format registers follow ZBC
index range starting at 1.
- void (*init_table_indices)(struct gk20a *g,
	struct nvgpu_gr_zbc_table_indices *zbc_indices);
- Add corresponding functions for legacy chips
- Add zbc color, depth and stencil table size hw defines
- Remove ltc.zbc_table_size() hal
- Update ltc.set_zbc_s_entry(), ltc.set_zbc_color_entry and
ltc.set_zbc_depth_entry() accordingly.

Bug 3122410
Bug 3122649

Change-Id: Ib799991ad35c6613534c0a6eb07f3bf24e600dc5
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2417620
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 2020-12-15 14:13:28 -06:00
Lakshmanan M
0e7b6e27e8 gpu: nvgpu: Add multi GR sec2 boot support 
This CL covers the following code changes,
1) Added API to get the physical gpc id masks.
2) Added multi GR instance sec2 boot support for MIG.

JIRA NVGPU-5650

Change-Id: I16c6bd34b5e8d86ad807fafac4b2441c097eb3e2
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2419092
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
673cd507a8 gpu: nvgpu: add mm gops to get default va size 
Currently, default va aperture size, user size and kernel size are
defined as fixed macros. However, max va bits can be chip specific.
Add below mm gops API to obtain default aperture, user and/or kernel
virtual memory size.
void (*get_default_va_sizes)(u64 *aperture_size,
		u64 *user_size, u64 *kernel_size);

JIRA NVGPU-5302

Change-Id: Ie0c60ca08ecff6613ce44184153bda066803d7d9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2414840
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 2020-12-15 14:13:28 -06:00
sagar
f3153a3ecc gpu: nvgpu: update doxygen for obj_alloc 
Updated doxygen documentation for supported calss names.

Jira NVGPU-4378

Change-Id: Ib3572ffd651556d767dd0cc3323e6c15da52af35
Signed-off-by: sagar <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2298592
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 2020-12-15 14:13:28 -06:00
Deepak Nibade
c8b2bd7a03 gpu: nvgpu: check default and valid preemption modes 
APIs to set preemption modes right now have config based code to set
default preemption modes or to check if given preemption mode is valid
or not. This makes code unreadable and complex.

Rework nvgpu_gr_obj_ctx_init_ctxsw_preemption_mode() so that it checks
for initial preemption modes in the beginning. If no preemption mode is
passed while allocating context, get default preemption modes with
gops.gr.init.get_default_preemption_modes() and use them.

Rework nvgpu_gr_ctx_check_valid_preemption_mode() so that it is more
readable. Use gops.gr.init.get_supported_preemption_modes() to validate
incoming preemption modes against supported preemption modes.

Log preemption modes getting set in
nvgpu_gr_obj_ctx_set_ctxsw_preemption_mode().

Disable failing unit test. It will need rework according to new code.

Jira NVGPU-5648

Change-Id: Ie1a3e1aeae7826a123e104d9d016f181bea3b271
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Lakshmanan M
c0e2dc5b74 gpu: nvgpu: Add subctx programming for MIG 
This CL covers the following code changes,
1) Added api to init inst_block for more than one subctxs.
2) Added logic to limit the subctx bind based on
   max. VEID count allocated to a gr instance.
3) Renamed nvgpu_grmgr_get_gr_runlist_id.

JIRA NVGPU-5647

Change-Id: Ifec8164a9e5f46fbd0538c3dd50e19ee63667a54
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2418463
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 2020-12-15 14:13:28 -06:00
Deepak Nibade
dd9298c959 gpu: nvgpu: move perf unit accesses to common.perf unit 
Below HALs are implemented in common.gr unit, but they really belong
to common.perf unit since they access registers from perf unit.
gops.gr.init_hwpm_pmm_register()
gops.gr.get_num_hwpm_perfmon()
gops.gr.set_pmm_register()
gops.gr.reset_hwpm_pmm_registers()

Move them to common.perf unit, and update all the code accordingly
gops.perf.init_hwpm_pmm_register()
gops.perf.get_num_hwpm_perfmon()
gops.perf.set_pmm_register()
gops.perf.reset_hwpm_pmm_registers()

Add new HAL gops.gr.get_pm_ctx_buffer_offsets() and set it to
gr_gk20a_get_pm_ctx_buffer_offsets() for all chips.

Bug 2510974
Jira NVGPU-5360

Change-Id: Ib5e84ed5c8b6e72cc6923161e55fc2c3a6a4070e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
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 2020-12-15 14:13:28 -06:00