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Author SHA1 Message Date
Sagar Kamble
dac79ce2f9 gpu: nvgpu: fix CERTC violation in falcon unit 
Fix below CERTC violation:

linux-nvgpu/drivers/gpu/nvgpu/common/falcon/falcon.c:430
  Checker: CERT INT30-C
linux-nvgpu/drivers/gpu/nvgpu/common/falcon/falcon.c:430:
  5. cert_int30_c_violation: Unsigned integer operation
     "ucode_header[1U] + 255U" may wrap.

JIRA NVGPU-4131

Change-Id: I2e60e6468047d497bcd8b72ee0730301b8221423
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210611
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
38cc3ed48f gpu: nvgpu: fix CERT-C violations in mm 
INT30-C requires that unsigned integer operations do not wrap.

Jira NVGPU-3882

Change-Id: I2424416e79d4203931fd28afc1c9349a746d8f68
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211033
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
3eaf08f06f gpu: nvgpu: fix CERT-C violations in mm 
INT33-C requires that modulo operations check divisor has non-zero value

Jira NVGPU-3882

Change-Id: Ic9cd1ca081f0ef98d5f81bb2d1c43a2a69273275
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210255
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
4c5058ade7 gpu: nvgpu: move mm gpu_ops out of gk20a.h 
gk20a.h will include gops_mm.h to contain mm gpu_ops definitions. This
will allow to document MM HALs at high level.

Jira NVGPU-4105

Change-Id: Ic99cb39a8e40084071f230fdecd362fd6add3877
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208921
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
bf4311a0e3 gpu: nvgpu: mm: code complexity cleanup mmu_fault 
This patch divides complex code segments into smaller functions to
reduce code complexity in hal mm mmu_fault gv11b_fusa code.

Jira NVGPU-4065

Change-Id: I360939dd8fd2673159a515f535edbaf400930c77
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205949
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
266c2b819f gpu: nvgpu: mm: code complexity cleanup vm code 
This patch divides nvgpu_vm_do_init() and nvgpu_vm_map() into smaller
functions to reduce code complexity in vm.c.

Jira NVGPU-4065

Change-Id: If5aadfa22e8bb5205576e621cc1314a2509bee3f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2205941
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
c14493e2fa gpu: nvgpu: fix CERT-C INT31 violation in static_analysis.h 
Fix INT32-C violation in nvgpu_safety_checks() by using the safe cast
operation.

JIRA NVGPU-3868

Change-Id: I959f8a4a9a61ce57b9db8e4a72b1f03da0b5f038
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210115
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Scott Long
52a4dd74e2 gpu: nvgpu: fix misra 18.4 violations 
This change eliminates MISRA Advisory Rule 18.4 violations in the
following cases:

 * nvgpu_submit_append_gpfifo_user_direct()
 * nvgpu_submit_append_gpfifo_common()
    - use array-indexing to access gpfifo entry lists
 * gv11b_gr_intr_record_sm_error_state()
    - use array-indexing to access sm_error_states table

Advisory Rule 18.4 states that the +, -, +=, and -= operators should
not be applied to an expression of pointer type.

JIRA NVGPU-3798

Change-Id: I736930e4ba09a88888b0ef48f62496c4082ea5a1
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2210173
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:05:52 -06:00
vinodg
3d546ad863 gpu: nvgpu: unit: more coverage for gr interrupt unit 
Add support for nonstall isr call from unit test
Add support for setting global esr for sm exception
Add null functions for tex exception and log_mme_exception

Jira NVGPU-4085

Change-Id: I8f4650008fa9e45f81f151e1acb13718801c8f8b
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209874
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
vinodg
5bd62ba4c8 gpu: nvgpu: check for valid ctx in gr error report code 
Add checking whether the current context is valid on reporting
sm exception error. This is needed as the interrupt unit test
call without a valid channel.

Jira NVGPU-4096

Change-Id: Ic6c49593dea26148f33f3bbf41a5dee437925c56
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209873
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:05:52 -06:00
Vinod G
4930e923fa gpu: nvgpu: gr interrupt code correction 
Changed handle_ssync_hww hal function return value
from int to void. No need to check return value if
handle_ssync_hww pointer is valid.

Jira NVGPU-4085

Change-Id: I6f6e2b629d16d1f678304182429c9c6a5ecdae9b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209868
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
c7a2633e82 gpu: nvgpu: Correct misra error in gr unit 
Correct 5.3 misra error in gr ecc unit
misra_c_2012_rule_5_3_violation: Declaration with identifier
"err" hides another declaration.
Change the variable name inside the function.

Jira NVGPU-4085

Change-Id: Ib8cd62ce98da1cf1bf327eb8dd92e51c1b77d6f4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209867
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vinod G
c0684633d2 gpu: nvgpu: Add checking for non safety code 
Add checking for unused non safety code in the
gr interrupt unit.
Add #ifdef CONFIG_NVGPU_HAL_NON_FUSA checking for
gm20b_gr_intr_tpc_exception_sm_enable function which is not being
called in safety code.
Add #ifdef CONFIG_NVGPU_DEBUGGER checking for
gm20b_gr_intr_tpc_exception_sm_disable function which is needed
with debugger enable.

Jira NVGPU-4085

Change-Id: Ie721505cdfced5b6b0443624d6e7cca2a0d4a19a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208918
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
425f0871d2 gpu: nvgpu: add doxygen documentation mm.allocator 
Add doxygen documentation in allocator.h for mm.allocator.

Jira NVGPU-4035

Change-Id: I8c586e6d2da52de1246d5584c65773723203d506
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204125
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
89cc37305b gpu: nvgpu: add doxygen documentation mm.nvgpu_mem 
Add doxygen documentation in nvgpu_mem.h for mm.nvgpu_mem

Jira NVGPU-4045

Change-Id: I24d4f6901dba42a92a6f9473d3e344dfe62b8e9c
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203999
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
f9e33430ed gpu: nvgpu: fix MISRA rule 8.6 violation 
nvgpu_channel_sync_wait_syncpt is not defined in safety build with the
removal of KMD submit. However, it's declaration was not compiled out.
Fix it.

JIRA NVGPU-3873

Change-Id: Ib2dea5172d53da58c5a16be90bd6f8204bd15572
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2209498
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
4a5ee02291 gpu: nvgpu: unit: init: update to work with new init design 
To address CCM in nvgpu_finalize_poweron(), some init APIs were updated
and broke the init unit test, so it was disabled. This addresses the
breakage and re-enables the test.

JIRA NVGPU-3980

Change-Id: I61b6595e0903373c36f949a5ec1e85718fd13f32
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207420
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
d10447e717 gpu: nvgpu: init: make poweron table driven 
Change nvgpu_finalize_poweron() to call the subunit init functions by
using a table. The table is local to nvgpu_finalize_poweron() since the
function pointers are stored at runtime in the gk20a struct during HAL
init. The table also includes a field for checking an enable flag before
calling the init op, if required.

The primary motivation for this change is to reduce CCM for
nvgpu_finalize_poweron(). This change reduced the TCC metric from 40 to
10.

The init unit test is disabled until it can be updated to match the new
design.

JIRA NVGPU-3980

Change-Id: Ic93d3fdd185cc7feb883c898284e15b251277a8b
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202974
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
065f98f669 gpu: nvgpu: init: add return for all init APIs 
This adds return values for all init APIs. This make all the init APIs
have the same signature. This is a prerequisite to making a table of
init functions.

JIRA NVGPU-3980

Change-Id: I5b71fd06ad248092af133ffe908e2930acb6d2b0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202973
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
b3e3509b4a gpu: nvgpu: bios: update bios init API 
Remove the second parameter for the nvgpu_bios_sw_init()
function so the function only requires the gk20a object. The
g->bios was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.

JIRA NVGPU-3980

Change-Id: Id70e2b6b3a9b2705815591d02730d2d2620771c0
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202972
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
67e1fbca1f gpu: nvgpu: acr: update acr init APIs 
Remove the second parameter for the nvgpu_acr_init() and
acr_construct_execute() functions so they only require the gk20a
object. The g->acr was always passed for this parameter. And this
makes the API signature match the other init functions in the driver.

JIRA NVGPU-3980

Change-Id: I8c513b1dcb9c6083f0f3e2f7b6f31dc78c5c8200
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202971
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
a877192641 gpu: nvgpu: sec2: update sec2 API 
Remove the second parameter for the nvgpu_init_sec2_setup_sw()
function so the function only requires the gk20a object. The
g->sec2 was always passed for this parameter. And this makes the
API signature match the other init functions in the driver.

JIRA NVGPU-3980

Change-Id: I22f526d961da44da64d563f5f3136c62cf9f4adf
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202970
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
19dd64930d gpu: nvgpu: pmu: move rtos init to func ptr 
This moves the nvgpu_pmu_rtos_init() to a HAL function pointer which
makes it consistent with the other init APIs.

JIRA NVGPU-3980

Change-Id: I562e264deaec76f2a45026a07f24d35b291b1930
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202969
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
b53ec4731e gpu: nvgpu: pmu: update init APIs 
Remove the second parameter for the pmu_early_init() and pmu_init()
functions so they only require the gk20a object. The g->pmu was always
passed for this parameter. And this makes the API signature match the
other init functions in the driver.

JIRA NVGPU-3980

Change-Id: Iae9361a5f14bc5c1d02f4ddb6583f30b71b22d59
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202968
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
78c1f328bb gpu: nvgpu: init: consolidate falcon init/free calls 
Combine all of the falcon_sw_init() calls into nvgpu_falcons_sw_init()
and combine all of the falcon_sw_free() calls into
nvgpu_falcons_sw_free().

JIRA NVGPU-3980

Change-Id: I23008a19be95a8cf4f73e2a18c414bce8879e8a2
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2202967
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
b21da03432 gpu: nvgpu: clk: remove unused HAL 
The clk HAL disable_slowboot() is not set for any platform and is thus
unused, so remove it

JIRA NVGPU-3980

Change-Id: Idb61ae35e85d35e852f18d22c076a1e16e723e88
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2196421
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Vedashree Vidwans
17d5df6a24 gpu: nvgpu: mm: allocator code complexity cleanup 
This patch divides complex code segments into smaller functions to
reduce code complexity in allocators.

Jira NVGPU-4065

Change-Id: I844f71592fe990765c5ec162431323a8e4bf0ef9
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2201907
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Seshendra Gadagottu
0697d4237b gpu: nvgpu: netlist: compile out non safety function for safety build 
Move functions used only by sim under CONFIG_NVGPU_NON_FUSA.
Following functions are compiled out for safety build:

void nvgpu_netlist_set_fecs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_fecs_data_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_inst_count(struct gk20a *g, u32 count);
void nvgpu_netlist_set_gpccs_data_count(struct gk20a *g, u32 count);

struct netlist_u32_list *nvgpu_netlist_get_fecs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_fecs_data(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_inst(struct gk20a *g);
struct netlist_u32_list *nvgpu_netlist_get_gpccs_data(struct gk20a *g);

void nvgpu_netlist_vars_set_dynamic(struct gk20a *g, bool set);
void nvgpu_netlist_vars_set_buffer_size(struct gk20a *g, u32 size);
void nvgpu_netlist_vars_set_regs_base_index(struct gk20a *g, u32 index);

JIRA NVGPU-2773

Change-Id: I37bdf498d5e152dc0d438644e3996835c1150e78
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208831
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Scott Long
67179c661e gpu: nvgpu: fix misra 4.4 violations 
This change eliminates the two instances of MISRA Advisory
Rule 4.4 violations from nvgpu by moving the code in question
within #if 0/#endif.

Advisory Rule 4.4 states that sections of code should not
be commented out.

JIRA NVGPU-3798

Change-Id: Id7c501d2d9407a87af5db54c3590705f67ba1ba3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208185
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Scott Long
77ffea99bd gpu: nvgpu: fix misra 18.4 violations 
This change eliminates MISRA Advisory Rule 18.4
violations in the following by accessing g->fifo.channel
with array indexing:

 * nvgpu_channel_init_support()
 * nvgpu_channel_semaphore_wakeup()

Advisory Rule 18.4 states that the +, -, +=, and -=
operators should not be applied to an expression
of pointer type.

JIRA NVGPU-3798

Change-Id: I6b1bf360db6ec25894cc0ea430c33067e0cddf64
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207550
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
7985a281de gpu: nvgpu: unit: update required_tests.json with falcon tests 
Keep the required_tests.json file up to date with current falcon unit
tests.

JIRA NVGPU-4126

Change-Id: I46b0cf4d9fb41302f4a3f9e43c39227cfba96c6a
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208836
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
5f2a64baa7 gpu: nvgpu: unit: fix test_falcon_mem_rw_zero 
Memory type parameter was set to MEM_IMEM always in the falcon test
test_falcon_mem_rw_zero. Fix it.

JIRA NVGPU-4126

Change-Id: I49711a8167942c87f965bb135132c224bf55d117
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208835
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Sagar Kamble
c7d51e4838 gpu: nvgpu: unit: add SWUTS docs for falcon unit tests 
This adds the SWUTS documentation for nvgpu-runlist unit tests:
 - test_falcon_sw_init_free
 - test_falcon_reset
 - test_falcon_mem_scrub
 - test_falcon_idle
 - test_falcon_halt
 - test_falcon_mem_rw_init
 - test_falcon_mem_rw_range
 - test_falcon_mem_rw_aligned
 - test_falcon_mem_rw_zero
 - test_falcon_mailbox
 - test_falcon_bootstrap

JIRA NVGPU-3943

Change-Id: I343cb12f884844d778e94c7e9df7bae9dbdbe3c0
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2208834
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
9ad3de64b1 gpu: nvgpu: unit: SWUTS for interface.rbtree 
Add SWUTS documentation for the interface.rbtree unit.

JIRA NVGPU-3943

Change-Id: I9555090bc986f5cea76add6a46309a13b37f371c
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207312
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
bac3b84a7b gpu: nvgpu: unit: SWUTS for interface.lock 
Add SWUTS documentation for the interface.lock unit.

JIRA NVGPU-3943

Change-Id: I705755482ee98217dc5015a42fea6f13ba852a61
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207311
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
b7066e0bf1 gpu: nvgpu: unit: SWUTS for interface.bsearch 
Add SWUTS documentation for the interface.bsearch unit.

JIRA NVGPU-3943

Change-Id: I40ffe7d004823f4a04532cb01bd548579b4dbf70
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207310
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Richard Zhao
1ad0bf9098 gpu: nvgpu: vgpu: add mmu_debug_mode support 
Added two new IVC commands that set gr and fb mmu debug mode.

Bug 2586624

Change-Id: I358fb04713a9754fb209c0a90d02130dd4a1caf6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204980
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
ef2d30328f gpu: nvgpu: ecc: improve CCM for nvgpu_ecc_free 
This reduces the code complexity for nvgpu_ecc_free() by creating a
helper function free_ecc_stat_count_array().

The TCC metric is reduced from 27 to 5.

JIRA NVGPU-4094

Change-Id: I80c85fe56d253616817682278f4bef241c346d57
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206518
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
vinodg
16a07a66ec gpu: nvgpu: unit: gr unit test for fecs errors 
Add gr interrupt unit test to cover all fecs errors.

Jira NVGPU-4085

Change-Id: Ia5b2bb61473348e993a26432bd45b781900a2d71
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207585
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
vinodg
63d333e324 gpu: nvgpu: unit: add more gr interrupt test 
Add gr interrupt unit test to cover gpc and tpc
exceptions.

Jira NVGPU-4085

Change-Id: I514c376d46b5ded345846465ef54d7b132341907
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207482
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
780b1f156b gpu: nvgpu: add doxygen documentation in mm.as 
Add doxygen documentation for mm.as in the as.h header.

JIRA NVGPU-4036

Change-Id: I274ba146395ba463cf9d4f575ea817f9c633e5f7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203941
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
7918cbb4f0 gpu: nvgpu: unit: unit tests for mm.as 
This patch adds unit testing for the mm.as unit including:
- feature tests
- error injection testing
- 100% line coverage and 96% branches (one missing branch that
  cannot be tested or removed)

JIRA NVGPU-917

Change-Id: I54bdac21e56554d1d960955f1a140ab98c9f3e5e
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194399
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Nicolas Benech
6a6fa99d8a gpu: nvgpu: unit: fw: add nvgpu.nvgpu error injection support 
Similar to DMA and KMEM, this allows to trigger errors in a couple
of functions within os/nvgpu: gk20a_busy and nvgpu_posix_probe

JIRA NVGPU-917

Change-Id: I033861d7ff449fac1275c27dffcdf922de3f0ac7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2194398
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Philip Elcan
9378675213 gpu: nvgpu: whitelist MISRA violations for WARN_ON/BUG_ON 
Whitelist false positive violations cause by a Coverity bug that
that overrides the WARN_ON/BUG_ON macros. See nvbug 2277532 for
details on the bug.

JIRA NVGPU-4031

Change-Id: I395f97c89580195485e93275663a062f26ab6fc7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207326
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Preetham Chandru Ramchandra
8ec2b11d04 gpu: nvgpu: use the right config name for s/w sema 
The correct config to be used is CONFIG_NVGPU_SW_SEMAPHORE and not
CONFIG_NVGPU_SW_SEMAPHPORE.
Due to this the s/w semaphores were not getting freed.

Bug 200542024

Change-Id: I5eee0d52f0c1116e68a304b94e01fd407e74526e
Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207182
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
dinesh
8244de0729 gpu: nvgpu: Change in scheduler class for threads 
As per one of the requirement priority of interrupt threads in
qnx should be changed to 21 with SCHED_RR class. NVGPU driver
is creating threads with FIFO class. This makes delay in scheduling
other interrupt threads.

This is added to change the schduler class to RR.

JIRA NVGPU-4121

Change-Id: Ie0a5f08b95cfab4ffbbd3c0c74a53324c64c202f
Signed-off-by: dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206210
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shashank Singh <shashsingh@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Seema Khowala
e340c9df05 gpu: nvgpu: re-org struct to move NON FUSA HALs at the end 
This is required to doxygen FUSA HALs and then pull
the content into SWUD.
Doxygenating NON FUSA HALs can be skipped.

JIRA NVGPU-3950

Change-Id: Ia1917fbb1c5d14753cb522691544e2f76aeb5a51
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204079
GVS: Gerrit_Virtual_Submit
Reviewed-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Seema Khowala
136d4861eb gpu: nvgpu: arch: add fifo specific gops_*.h 
JIRA NVGPU-3590

Change-Id: Ic10d123f1ccb151da294471095f3df50c37d2c8e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2204042
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Seema Khowala
202e066d4e gpu: nvgpu: move fifo specific gpu_ops out of gk20a.h 
gk20a.h will include gops_member.h where member corresponds to the
member of gpu_ops.

This is needed to doxygen HALs at high level without
exposing chip specific hal files.

JIRA NVGPU-3950

Change-Id: I99a5e6f45cf93dde47eac12ce76ba65c38d7fa67
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203960
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00
Prateek sethi
07beae3c6a gpu: nvgpu: userspace: Add channel_os SWUTS reference 
Add reference to channel_os SWUTS in the SWUTS.h document.

JIRA NVGPU-3898

Change-Id: I2d2a7fb7644aabfcc61871b1cc1f78f09159e8de
Signed-off-by: Prateek sethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2203608
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:05:52 -06:00