- Add test scenarios for achieving branch coverage
for failure of dynamic memory allocation while
preparing ucode blob.
- Add more branch coverage for nvgpu_acr_bootstrap_hs_acr()
- Move GR reg space required for ACR tests to ACR unit test
itself to remove dependency on GR unit
JIRA NVGPU-4319
Change-Id: I770a696a1681eb05243c7168878793a30cd59c13
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2286257
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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ACR ucode is encrypted using different keys for prod/dbg boards.
This change adds a check to select ACR ucode based on board type.
Note: This support is added only for t19x.
This patch also enables the prints "DEBUG MODE" indicative of board/
acr_ucode signature type and sctl and cpuctl reg values.
Bug 2350733
Bug 2672832
Bug 2672836
JIRA NVGPU-4001
Change-Id: I936b811b5836152206b11ec615ee75d201939968
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2268880
Reviewed-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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* Updated types and added error checks
* Modified GR condition for ctxsw disable count
CERT-C error check was added to detect error on integer overflow
But below logic couldn't detect first overflow, so updated condition
INT_MAX < gr->ctxsw_disable_count --> it became true after overflow
So, we didn't detected in first overflow and lead to assert on enable
JIRA NVGPU-3400
Change-Id: I6b0265a464f8f19efa7b0761612c6e9ffb3bd2bd
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2206282
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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to acr_blob_construct.c/h
JIRA NVGPU-2516
Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
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Removed HS self-load & bootstrap public function as no other unit access
this function. Made changes to ACR bootstrap function to load & bootstrap
ACR HS ucode on respective Engine Falcon using Falcon unit HS ucode load
& bootstrap function.
JIRA NVGPU-3811
Change-Id: I293f12137e568610a0b95f668a8408f9fce0a5f0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195018
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Moving HS ucode bootstrap from ACR unit to Falcon unit as HS ucode
bootstrap needs to be accessed by multiple units. Currently FB unit
calls ACR unit function to do self HS load & bootstrap memory unlock
HS ucode. This adds dependency on ACR unit which is not correct. So,
moving to Falcon unit to make it generic.
JIRA NVGPU-3811
Change-Id: I3696296c9df661d821199cb93872265ef6d10bfc
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2195016
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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ACR HS ucode is currently loaded by pmu_bl.bin (falcon bootloader),
but ACR ucode can be loaded without bootloader support by directly
copying non-secure/secure code to respective IMEM offset along with
required data to DMEM, with this bootloader dependency is removed.
This patch uses nvgpu_acr_self_hs_load_bootstrap to directly load
acr ucode to imem using priv writes. This also removes the bootloader
related code
JIRA NVGPU-3811
Change-Id: Ie2632eb26e421de3765a99c5426471eb37bf1bc9
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2169976
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Advisory Rule 5.9 states that identifiers that define objects or functions
with internal linkage should be unique.
This change eliminates an Advisory Rule 5.9 violation in our acr code
due to duplicate definitions of flcn64_set_dma() by placing a single
inline version in flcnif_cmn.h.
Jira NVGPU-3178
Change-Id: Id9171059ee490cbadd46204f520fccefc44669f7
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2190074
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Advisory Rule 2.7 states that there should be no unused
parameters in functions.
This patch removes unused function parameters from the following:
* acr_hs_bl_exec() -> remove 'acr' param
Jira NVGPU-3178
Change-Id: I46197964aa832bae24ea2fcbc8eeea1cac7f8909
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2179495
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Rule 11.3 states that a cast shall not be performed
between a pointer and object type and a pointer to
a different object type.
Fix this violation by first casting the pointer to
void pointer (void *) and then casting that void
pointer to the required pointer type.
JIRA NVGPU-3571
Change-Id: I2dae55c5b1f4cda3beb3062844ecc853e45ac0a3
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2135035
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Sagar Kamble <skamble@nvidia.com>
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
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Safety build does not support vidmem. This patch compiles out vidmem
related changes - vidmem, dma alloc, cbc/acr/pmu alloc based on
vidmem and corresponding tests like pramin, page allocator &
gmmu_map_unmap_vidmem..
As vidmem is applicable only in case of DGPUs the code is compiled
out using CONFIG_NVGPU_DGPU.
JIRA NVGPU-3524
Change-Id: Ic623801112484ffc071195e828ab9f290f945d4d
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132773
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Fix the following MISRA rule violations in bitops unit,
MISRA Rule 10.1
MISRA Rule 10.3
MISRA Rule 10.4
MISRA Rule 11.8
MISRA Rule 21.2
Introduce nvgpu specific functions for bitops and bitmap operations
with unsigned integer as parameter for offset. OS specific type
conversions and handling of these inerfaces are taken care in the
respective OS files.
Jira NVGPU-3545
Change-Id: Ib1ef76563db6ba1d879a0b4d365b2958ea03f85c
Signed-off-by: ajesh <akv@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2129513
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