AHUB and its child nodes ports are part of platform DTS and with new
platform support these entries need to be defined again.
As they are common across the platforms, moving them to SoC
DTSI to avoid code duplicacy.
AHUB HW accelerators are used for audio processing and typically all of
these are made available. Platforms can enable all of these just by
enabling the AHUB parent device. However IO interfaces (which are also
children of AHUB) are selectively enabled based on what the platform
actually exposes for interaction with external world.
Upstream commit ID: 71a3b9b17537a114705d2d01d227e19fd7353bff
Bug 4429992
TAS-2240
Change-Id: I3c148efaa5ea7ca1ac2063e3425fa54172aff346
Signed-off-by: sheetal <sheetal@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3086458
(cherry picked from commit 6790d74964)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3151093
Tested-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
The MGBE power-domains on Tegra234 are mapped to the MGBE controllers as
follows:
MGBE0 (0x68000000) --> Power-Domain MGBEB
MGBE1 (0x69000000) --> Power-Domain MGBEC
MGBE2 (0x6a000000) --> Power-Domain MGBED
Update the device-tree nodes for Tegra234 to correct this.
Bug 3820445
Bug 4293378
Fixes: 610cdf3186bc ("arm64: tegra: Add MGBE nodes on Tegra234")
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Change-Id: I470a7128e2bc05c5c66539fab544d091b2f846a4
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3082846
Reviewed-by: Brad Griffis <bgriffis@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
The Tegra SYSRAM contains regions access to which is restricted to
certain hardware blocks on the system, and speculative accesses to
those will cause issues.
Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted
to resolve this by only mapping the regions specified in the device
tree on the assumption that there are no such restricted areas within
the 64K-aligned area of memory that contains the memory we wish to map.
Turns out this assumption is wrong, as there are such areas above the
4K pages described in the device trees. As such, we need to use the
bigger hammer that is no-memory-wc, which causes the memory to be
mapped as Device memory to which speculative accesses are disallowed.
As such, the previous patch in the series,
'firmware: tegra: bpmp: do only aligned access to IPC memory area',
is required with this patch to make the BPMP driver only issue aligned
memory accesses as those are also required with Device memory.
Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
[mperttunen@nvidia.com: port to downstream dts]
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Change-Id: I8a864a5a858077a1f1d2d45da706559637bc3a94
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2908381
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
This change is based on mainline change
commit 27f1568b1d5fe35014074f92717b250afbe67031
Author: Pierre Gondois <pierre.gondois@arm.com>
arm64: tegra: Update cache properties
Bug 4057304
Change-Id: Idb402b1d8f29873d2403d340bbd6e4902d9b5f05
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2886422
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
The #address-cells and #size-cells properties for the top-level bus were
set to 1 because that was enough to represent the register ranges of all
the IP blocks on that bus. However, most of these devices can do DMA to
a larger address space, so translation of DMA addresses needs to happen
in a 64-bit address space.
Partially this was already done by the memory controller increasing that
address space by setting #address-cells and #size-cells to 2, but a full
DMA address translation would still cause truncation when traversing to
the top-level bus.
Fix this by setting #address-cells = <2> and #size-cells = <2> on the
top-level bus and adjusting all "reg" and "ranges" properties of its
children.
While at it, also move the PCI and GPU nodes back under the top-level
bus where they belong. The were put outside of it to work around this
same problem.
This change is based on the below change from mainline v6.3-rc5:
commit 2838cfddbc1c4e12dacf8219efb481ab11c114a4
Bug 4057304
Change-Id: Iedd79836dac2a6760a604da6e61db4735e246435
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2884732
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Nodes in device tree should be sorted by unit-address, followed by nodes
without a unit-address, sorted alphabetically. Some exceptions are the
top-level aliases, chosen, firmware, memory and reserved-memory nodes,
which are expected to come first.
These rules apply recursively with some exceptions, such as pinmux nodes
or regulator nodes, which often follow more complicated ordering (often
by "importance").
This is based on the work done by Thierry in the mainline
commit 79ed18d9ece474c15a2578e1cc5bfb4fce7a8eb7
Author: Thierry Reding <treding@nvidia.com>
arm64: tegra: Sort nodes by unit-address, then alphabetically
The reference is taken from v6.3-rc5
Bug 4057304
Change-Id: I4a190193e2d106948fb1879ec1ad9fc4d29e33c8
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2882047
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
commit edf408b946d3 ("PCI: dwc: Validate iATU outbound mappings against
hardware constraints") exposes an issue with the existing partitioning of
the aperture space where the Prefetchable apertures of controllers
C5, C7 and C9 in Tegra234 cross the 32GB boundary hardware constraint.
This patch makes sure that the Prefetchable region doesn't spill over
the 32GB boundary.
Cherry picked from below mainline commit:
248400656b1c: arm64: tegra: Fix Prefetchable aperture ranges of Tegra234 PCIe controllers
Bug 3835199
Bug 3970434
Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Change-Id: I9309fa26a357f6b5dd042968b331593b3133763a
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2859930
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Copy tegra234.dtsi from kernel to make available to
create top level DTS files for the platforms which are
not upstreamed yet.
This file is copied only without any editing.
DTSI is synced from the
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Tag: Linux 6.1-rc4v6.1-rc4
Change list from top for arch/arm64/boot/dts/nvidia$ are:
8e4428051df1 arm64: tegra: Add GPCDMA support for Tegra I2C
af4c27738c92 arm64: tegra: Add iommus for HDA on Tegra234
0a4fa2504217 arm64: tegra: Enable HDA node for Jetson AGX Orin
b35f5b53a87b arm64: tegra: Add context isolation domains on Tegra234
b0c1a994f660 arm64: tegra: Fixup iommu-map property formatting
a1e3de6ea519 arm64: dts: tegra: smaug: Add Wi-Fi node
a63c0cd83720 arm64: dts: tegra: smaug: Add Bluetooth node
8aec2c17b95e arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
Bug 3860258
Change-Id: I4ff9a00d7c310fc58609b72ea488df023cee67e0
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2807224
Reviewed-by: svcacv <svcacv@nvidia.com>
