nvgpu_gr_init_fs_state is right now defined in common.gr.gr unit
This API also needs to be called from common.gr.obj_ctx unit so obj_ctx
unit depends on gr unit for this.
common.gr.gr unit already depends on common.gr.obj_ctx for context
initialization. So this causes a circular dependency
Fix this by moving this API to new standalone unit common.gr.fs_state
Rename it to nvgpu_gr_fs_state_init
Jira NVGPU-1887
Change-Id: I88ca8e1a7bc3c544459462493116f95d92b9ab01
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090496
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Moved fecs_host_int_enable ops from gr to gr falcon.
Created required hals in gm20b and gv11b gr falcon units.
gr_gk20a_fecs_host_int_enable -> gm20b_gr_falcon_fecs_host_int_enable
gr_gv11b_fecs_host_int_enable -> gv11b_gr_falcon_fecs_host_int_enable
JIRA NVGPU-1881
Change-Id: Ice9d5170928068b0447cc4644e6668f7ff75b8d6
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Moved following functionality from gr to gr falcon common
gr_gk20a_init_ctxsw -> nvgpu_gr_falcon_init_ctxsw
gr_gk20a_init_ctx_state -> nvgpu_gr_falcon_init_ctx_state
gk20a_init_gr_bind_fecs_elpg -> nvgpu_gr_falcon_bind_fecs_elpg
Replaced code in gr_gk20a.c by calling corresponding gr falcon common
calls and moved all relevant code to gr falcon unit.
Moved following gr ops from gr to gr falcon:
int (*init_ctx_state)(struct gk20a *g);
Moved functionality from gr to relevant gr falcon hals:
gr_gk20a_init_ctx_state -> gm20b_gr_falcon_init_ctx_state
gr_gp10b_init_ctx_state -> gp10b_gr_falcon_init_ctx_state
JIRA NVGPU-1881
Change-Id: I027e1972a7747275311df99679235804dc0e16fe
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084391
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move all fecs methods related code to gr falcon unit and handle it
through generic gr.falocn.ctrl_ctxsw hal.
Following methods are moved from gr_gk20a.c to gr falcon unit.
fecs method and corresponding new fecs method def in gr_falcon.h:
gr_fecs_method_push_adr_discover_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_IMAGE_SIZE
gr_fecs_method_push_adr_discover_pm_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_PM_IMAGE_SIZE
gr_fecs_method_push_adr_discover_reglist_image_size_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_DISCOVER_IMAGE_SIZE
gr_fecs_method_push_adr_set_reglist_bind_instance_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_BIND_INSTANCE
gr_fecs_method_push_adr_set_reglist_virtual_address_v ->
NVGPU_GR_FALCON_METHOD_REGLIST_SET_VIRTUAL_ADDRESS
Following fecs methods are moved from obj_ctx.c to gr falcon unit.
gr_fecs_method_push_adr_bind_pointer_v ->
NVGPU_GR_FALCON_METHOD_ADDRESS_BIND_PTR
gr_fecs_method_push_adr_wfi_golden_save_v ->
NVGPU_GR_FALCON_METHOD_GOLDEN_IMAGE_SAVE
Following fecs methods are moved from gr_gp10b.c to gr falcon unit.
gr_fecs_method_push_adr_discover_preemption_image_size_v ->
NVGPU_GR_FALCON_METHOD_PREEMPT_IMAGE_SIZE
gr_fecs_method_push_adr_configure_interrupt_completion_option_v ->
NVGPU_GR_FALCON_METHOD_CONFIGURE_CTXSW_INTR
Following fecs method is moved from zcull_gm20b.c:
gr_fecs_method_push_adr_discover_zcull_image_size_v ->
NVGPU_GR_FALCON_METHOD_CTXSW_DISCOVER_ZCULL_IMAGE_SIZE
Following fecs method is moved from fecs_trace_gp10b.c:
gr_fecs_method_push_adr_write_timestamp_record_v
-> NVGPU_GR_FALCON_METHOD_FECS_TRACE_FLUSH
Added new HAL in gr falcon for moving fecs_current_ctx_data from
gr_gk20a.c to gr_falcon_gm20b.c.
u32 (*get_fecs_current_ctx_data)(struct gk20a *g,
struct nvgpu_mem *inst_block);
Added overlay for gm20b_gr_falcon_ctrl_ctxsw in newly added in
gr_falcon_gp10b.c for handling gp10b+ specific fecs methods:
gp10b_gr_falcon_ctrl_ctxsw
JIRA NVGPU-1881
Change-Id: I662d06f5176b29e6837d63c25e42de67505d48f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087148
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move handle_semaphore_pending to hal.gr.intr
gr_gk20a_handle_semaphore_pending function is moved from
gr_gk20a.c to common.gr.intr as nvgpu_gr_handle_semaphore_pending
JIRA NVGPU-3016
JIRA NVGPU-1891
Change-Id: Id731bb4169de9dcfff012e401165ad5a7f43bffa
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089173
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Move handle_notify_pending hal to hal.gr.intr
Move gk20a_gr_handle_notify_pending code from gr_gk20a.c to
common.gr.intr as nvgpu_gr_intr_handle_notify_pending function.
JIRA NVGPU-1891
JIRA NVGPU-3016
Change-Id: Ib3284a83253b03e5708674fce683331ee20b8213
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089172
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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New tpc_exception_sm_disable hal to disable and
tpc_exception_sm_enable hal to enable the sm bit in tpc_exception
register.
These hals are added to avoid the register access in common gr code.
JIRA NVGPU-3016
Change-Id: I21634e2cd3b2b8007081e6f7608ec2da9c74813f
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088311
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Added following new hals in gr falcon:
u32 (*get_current_ctx)(struct gk20a *g);
-> to get current context in execution.
u32 (*get_ctx_ptr)(u32 ctx);
-> related ctx_ptr for the context
Updated gr_gk20a.c, gr_gm20b.c, gr_gp10b.c and gr_gv11b.c
to use these new hals.
JIRA NVGPU-1881
Change-Id: I1c1cef8e4b0ca04e3e3218d552b6e8e08fcfa7d0
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087039
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Change gk20a_gr_nonstall_isr function to hal under hal.gr.intr
Use nvgpu_gr_gpc_offset and nvgpu_gr_tpc_offset call in
gm20b_gr_intr_handle_tex_exception function.
Update gk20a_gr_nonstall_isr call as g->ops.gr.intr.nonstall_isr
JIRA NVGPU-3016
Change-Id: I9ff39cf1a99bf5b3d215cda6bc68fab1ecae51e3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088133
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Move handle_gcc_exception to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable pointers
as function parameter to avoid dereferencing the g->ecc struct
inside the hal function
Update g->ops.gr.handle_gcc_exception to
g->ops.gr.intr.handle_gcc_exception
JIRA NVGPU-3016
Change-Id: Iaac9bd1763673567d8c29258d2f1952d061785a6
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087199
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Move handle_gpc_gpcmmu_exception to hal.gr.intr
Pass g->ecc.gr.mmu_l1tlb_ecc_corrected_err_count[gpc].counter
and g->ecc.gr.mmu_l1tlb_ecc_uncorrected_err_count[gpc].counter pointers
as function parameter to avoid dereferencing g->ecc inside hal function
Update g->ops.gr.handle_gpc_gpcmmu_exception to
g->ops.gr.intr.handle_gpc_gpcmmu_exception
JIRA NVGPU-3016
Change-Id: I9698cf71b568caf8e259996f84b4f26aded865f5
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087198
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gr_gk20a_commit_global_ctx_buffers() is h/w independent, hence move it
to common unit common.gr.obj_ctx and rename it as
nvgpu_gr_obj_ctx_commit_global_ctx_buffers()
Delete g->ops.gr.commit_global_ctx_buffers hal
Jira NVGPU-1887
Change-Id: If1c840237b8ba2c13bed40a4315810073756aeb9
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088506
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Following functions are moved from gr_gk20a.c to common gr_falcon.c
gr_gk20a_disable_ctxsw -> nvgpu_gr_falcon_disable_ctxsw
gr_gk20a_enable_ctxsw -> nvgpu_gr_falcon_enable_ctxsw
gr_gk20a_halt_pipe -> nvgpu_gr_falcon_halt_pipe
Added new gr falcon hal to control ctxsw:
int gm20b_gr_falcon_ctrl_ctxsw(struct gk20a *g, u32 fecs_method,
u32 data, u32 *ret_val)
Parameters:
fecs_method: will be specified by a generic define provided in gr_falcon.h
header.
data: input data parameter (if any), set it to zero, if method did not
require any data input.
ret_val: pointer to expected output.
Added following ops for gr falcon:
int (*halt_pipe)(struct gk20a *g); -> this is moved from gr
int (*disable_ctxsw)(struct gk20a *g);
int (*enable_ctxsw)(struct gk20a *g);
JIRA NVGPU-1881
Change-Id: Idb3b7355b5a0bd3b9bb01f9f424c5d607616f540
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081308
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move handle_gpc_gpccs_exception hal to hal.gr.intr
Pass g->ecc.gr.gpccs_ecc_corrected_err_count[gpc].counter and
g->ecc.gr.gpccs_ecc_uncorrected_err_count[gpc].counter variable address
as parameter to function to avoid dereferencing g->ecc variable
inside hal function.
Update g->ops.gr.handle_gpc_gpcss_exception call to
g->ops.gr.intr.handle_gpc_gpcss_exception
JIRA NVGPU-3016
Change-Id: I6cab6428eb6785261f34ca21f2ce055a9995b408
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087197
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Add new hal to get_tpc_exception to hal.gr.intr
This hal helps to avoid register read from the
common handle_tpc_exception function. Add a new struct to report the
tpc_exception type back to the common code to handle the exception.
JIRA NVGPU-3016
Change-Id: Ib504ade0b06b85cd38ccf166328784bab072573e
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085387
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add a new unit common.gr.obj_ctx which allocates and initializes GR
context. This unit also takes care of creating global golden image
used to initialize every context.
Add private header obj_ctx_priv.h that defines struct
nvgpu_gr_obj_ctx_golden_image
Add public header obj_ctx.h that exposes functions supported by new unit
This unit now exposes below API to allocate and initialize context
nvgpu_gr_obj_ctx_alloc()
Remove below functions from gk20a/gr_gk20a.c and move them to new unit
with below renames
gr_gk20a_fecs_ctx_bind_channel() -> nvgpu_gr_obj_ctx_bind_channel()
gr_gk20a_fecs_ctx_image_save() -> nvgpu_gr_obj_ctx_image_save()
gk20a_init_sw_bundle() -> nvgpu_gr_obj_ctx_alloc_sw_bundle()
gr_gk20a_alloc_gr_ctx() -> nvgpu_gr_obj_ctx_gr_ctx_alloc()
gr_gk20a_init_golden_ctx_image() ->
nvgpu_gr_obj_ctx_alloc_golden_ctx_image()
Use new APIs in gk20a_alloc_obj_ctx() to allocate context
For now this unit includes <nvgpu/gr/gr.h> and some h/w headers.
But they will be removed in follow up patches
Jira NVGPU-1887
Change-Id: Ib95ec1c19c5b74810f85c2feed8fdd63889d3d22
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2087662
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
In this CL, following ctxsw related code is moved to hal gr falcon.
1. gr_gk20a_wait_ctxsw_ready -> gm20b_gr_falcon_wait_ctxsw_ready
2. gr_gk20a_submit_fecs_method_op ->
gm20b_gr_falcon_submit_fecs_method_op
3. gr_gk20a_submit_fecs_sideband_method_op->
gm20b_gr_falcon_submit_fecs_sideband_method_op
Above functions are populated with following gr.falcon hals and called
from the current code as required:
int (*wait_ctxsw_ready)(struct gk20a *g);
int (*submit_fecs_method_op)(struct gk20a *g,
struct fecs_method_op_gk20a op, bool sleepduringwait);
int (*submit_fecs_sideband_method_op)(struct gk20a *g,
struct fecs_method_op_gk20a op);
Following static function also moved to gr_gk20a.c to hal gr falcon.
gr_gk20a_ctx_wait_ucode -> gm20b_gr_falcon_ctx_wait_ucode
JIRA NVGPU-1881
Change-Id: Icb4238dcacaf46ecfcada8bc8dcdeb68b6278bab
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085189
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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Add new hal g->ops.gr.falcon.set_current_ctx_invalid() in hal.gr.falcon
unit to invalidate current_ctx by setting invalid flag in register
gr_fecs_current_ctx_r()
Use new hal in gr_gk20a_init_golden_ctx_image() instead of accessing the
register directly
Define the hal for all supported chips
Jira NVGPU-2961
Change-Id: I756dac505c661ea2754abdbf6934927d1b469be3
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2085032
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move handle_tex_exception hal function to hal.gr.intr
Move hal function for gm20b and gp10b chips.
Removed the null implementation in gv11b hal.
Modify ops->gr.handle_tex_exception call to
ops->gr.intr.handle_tex_exception
JIRA NVGPU-3016
Change-Id: Ifd88ab6f35301525f7a58e8ccf2f4796dda640bf
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2084387
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Code for secure/non-secure ctxsw booting spread across gr_gk20a.c
and gr_gm20b.c. With this change this code is move to gr falcon unit.
Ctxsw loading is now supported with 2 supported common functions:
1.Non secure boot:
int nvgpu_gr_falcon_load_ctxsw_ucode(struct gk20a *g);
2.Secure boot:
int nvgpu_gr_falcon_load_secure_ctxsw_ucode(struct gk20a *g);
Now gr ops function "int (*load_ctxsw_ucode)(struct gk20a *g);" is moved to
gr falcon ops and in chip hals it is set with secure/non-secure booting.
Non-secure booting: nvgpu_gr_falcon_load_ctxsw_ucode support ctxsw loading
in 2 methods: bit-banging uode or booting with bootloader
A. Common and hal functions for non-secure bit-banging ctxsw loading:
Common: static void nvgpu_gr_falcon_load_dmem(struct gk20a *g) ->
Hals: void (*load_gpccs_dmem)(struct gk20a *g,i
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_dmem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Common: static void nvgpu_gr_falcon_load_imem(struct gk20a *g) ->
Hals: void (*load_gpccs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
void (*load_fecs_imem)(struct gk20a *g,
const u32 *ucode_u32_data, u32 size);
Other basic HALs:
void (*configure_fmodel)(struct gk20a *g); -> configure fmodel for ctxsw loading
void (*start_ucode)(struct gk20a *g); -> start running ctxcw ucode
B.Common and hal functions for non-secure ctxsw loading with bootloader
First get the ctxsw ucode using: nvgpu_gr_falcon_init_ctxsw_ucode, then
Common: static void nvgpu_gr_falcon_load_with_bootloader(struct gk20a *g)
void nvgpu_gr_falcon_bind_instblk((struct gk20a *g) ->
Hal: void (*bind_instblk)(struct gk20a *g, struct nvgpu_mem *mem, u64 inst_ptr);
Common: nvgpu_gr_falcon_load_ctxsw_ucode_segments ->
nvgpu_gr_falcon_load_ctxsw_ucode_header ->
nvgpu_gr_falcon_load_ctxsw_ucode_boot for both fecs and gpccs ->
Hals: void (*load_ctxsw_ucode_header)(struct gk20a *g, u32 reg_offset,
u32 boot_signature, u32 addr_code32, u32 addr_data32,
u32 code_size, u32 data_size);
void (*load_ctxsw_ucode_boot)(struct gk20a *g, u64 reg_offset, u32 boot_entry,
u32 addr_load32, u32 blocks, u32 dst);
Other basic HAL to get gpccs start offset:
u32 (*get_gpccs_start_reg_offset)(void);
C.Secure booting is support with gpmu and acr and with following additional
common function in gr falcon.
static void nvgpu_gr_falcon_load_gpccs_with_bootloader(struct gk20a *g) ->
nvgpu_gr_falcon_bind_instblk and nvgpu_gr_falcon_load_ctxsw_ucode_segments
Additional basic hals:
void (*start_gpccs)(struct gk20a *g);
void (*start_fecs)(struct gk20a *g);
Following ops from gr is removed, since it is not required to set by chip hals:
void (*falcon_load_ucode)(struct gk20a *g, u64 addr_base,
struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
Now this is handled by static common function:
static int nvgpu_gr_falcon_copy_ctxsw_ucode_segments( struct gk20a *g,
struct nvgpu_mem *dst, struct gk20a_ctxsw_ucode_segments *segments,
u32 *bootimage, u32 *code, u32 *data)
JIRA NVGPU-1881
Change-Id: I895a03faaf1a21286316befde24765c8b55075cf
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083388
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Add new hal g->ops.gr.init.load_sw_bundle_init() in hal.gr.init unit
and move corresponding code from gk20a_init_sw_bundle()
Add this hal to all the supported chips
Move g->ops.gr.init_sw_veid_bundle() hal to hal.gr.init unit
Move definition of hal to gv11b chip file of hal.gr.init
Add this hal for gv11b/gv100/tu104
Move g->ops.gr.init_sw_bundle64() hal to hal.gr.init unit
Move definition of hal to tu104 chip file of hal.gr.init
Add this hal for tu104
Jira NVGPU-2961
Change-Id: I560c2ba95fb820275d5ccb46939007c58481ccbb
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2083631
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move functions related to init_ctxsw_ucode to common
falcon from gr_gk20a.c. Modified code to call this new
function and modified function names in common falcon
to reflect new re-org.
JIRA NVGPU-1881
Change-Id: I389f5c902bfbec17cdb4b16840a5ba66f6b1e331
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081331
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Created gr falcon hal unit with moving following hal functions
from gr to gr falcon:
u32 (*fecs_base_addr)(void);
u32 (*gpccs_base_addr)(void);
void (*dump_stats)(struct gk20a *g);
u32 (*fecs_ctxsw_mailbox_size)(void);
u32 (*get_fecs_ctx_state_store_major_rev_id)(struct gk20a *g);
Modified chip hals to populate these new functions and related code
now refers to gr falcon hals.
Modified kernel headers to have following defs for
fecs/gpccs base address in gm20b/gp10b/gv11b/tu104:
static inline u32 gr_fecs_irqsset_r(void);
static inline u32 gr_gpcs_gpccs_irqsset_r(void);
Created base gm20b hals for fecs/gpccs_base_addr and
removed redundant gp106 related hals.
JIRA NVGPU-1881
Change-Id: I16e820cc1c89223f57988f1e5723fd8fdcbfe89d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081245
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Group gr falcon init related function together during init and
gr_reset sequence. This init sequence has following functions:
gr_gk20a_init_ctxsw
gr->ops.gr.init_ctx_state
gk20a_init_gr_bind_fecs_elpg
This init sequence will be moved to common gr falcon unit.
During gk20a_gr_reset sequence, instead of separate function calls
for fecs reglist operations, switched to helper function
gk20a_init_gr_bind_fecs_elpg. Also, this call needs to be protected
with g->can_elpg setting since it involves gpmu instblk.
JIRA NVGPU-1881
Change-Id: I74542ccb5f5ffce11374d30b8d5a5cc705feed9f
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081244
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.commit_global_cb_manager() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_cb_manager()
Move hal definitions to gm20b/gp10b hal files appropriately
Add nvgpu_gr_config pointer to the parameter list of this hal so that
it does not have to dereference struct gr_gk20a in hal.gr.init unit
Jira NVGPU-2961
Change-Id: Iaff476648fa6abdf5a79be500f65a40eb90c0b08
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077219
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.commit_global_attrib_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_attrib_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b/gv11b hal files appropriately
Jira NVGPU-2961
Change-Id: I5437a190a9e027997f63ef0e741d99e6bbebab3f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077218
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.commit_global_pagepool() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_pagepool()
Also move g->ops.gr.pagepool_default_size() hal to
g->ops.gr.init.pagepool_default_size()
Add global_ctx boolean flag as parameer to
g->ops.gr.init.commit_global_pagepool() to distinguish between
committing global pagepool v/s ctxsw pagepool buffers
Remove register header accessors from gr_gk20a_commit_global_ctx_buffers()
and move them to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Remove g->ops.gr.pagepool_default_size() hal for gv11b since gv11b can
re-use gp10b hal
Jira NVGPU-2961
Change-Id: Id532defe05edf2e5d291fec9ec1aeb5b8e33c544
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move init_gpc_mmu hal to hal.gr.init and update the
g->ops.gr.init_gpc_mmu call as g->ops.gr.init.gpc_mmu
Add new hal, pes_vsc_stream which will enable the master bit to
take floorsweep into consideration.
Modify the disable_rd_coalesce hal as su_coalesce hal and
set_rd_coalesce call as lg_coalesce hal and move to hal.gr.init
su_coalesce hal function touches only the surface read coalesce bit.
lg_coalesce hal function touches only the lg read coalesce bit.
JIRA NVGPU-2951
Change-Id: Ifc5e36f7e75d3b74142a83a3c78a9cb2b81752eb
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079532
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Create interrupt hal unit under hal.gr.intr.
This holds the interrupt and exception related hals.
Move enable_exceptions and enable_gpc_exceptions hal functions to
hal.gr.init location.
Modify enable_exceptions hal to pass gr->config and enable or disable
parameters.
Modify enable_gpc_exceptions to pass gr->config parameter.
Add new hal function enable_interrupts with enable or disable parameter
This hal helps to enable and disable the gr interrupts as needed.
gr init calls that use these hals are modified to
g->ops.gr.intr.enable_exceptions
g->ops.gr.intr.enable_gpc_exceptions
JIRA NVGPU-3016
Change-Id: Ib62f8bf0b5289b815c8eff4d32a47387f24af51b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077857
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.commit_global_bundle_cb() hal to hal.gr.init unit as
g->ops.gr.init.commit_global_bundle_cb()
Remove register header accessor from gr_gk20a_commit_global_ctx_buffers()
and move it to hal functions
Move hal definitions to gm20b/gp10b hal files appropriately
Jira NVGPU-2961
Change-Id: I6358dce963857402aa1d4d5606bf75398b9be83d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077216
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Move g->ops.gr.get_global_ctx_cb_buffer_size() and
g->ops.gr.get_global_ctx_pagepool_buffer_size() hals to hal.gr.init
unit
Move corresponding hal definitions to hal.gr.init unit
Jira NVGPU-2961
Change-Id: Ifff3e2073f6d9bca5b37244f7e107bad885e7ca7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2077215
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
