g->ops.gr.init.get_access_map() returns whitelist of register addresses
that can be accessed by SET_FALCON methods when added into pushbuffer.
SET_FALCON method does not need to be supported in safety.
Hence install an empty register access map in safety build by adding
a new flag CONFIG_NVGPU_SET_FALCON_ACCESS_MAP.
Compile out g->ops.gr.init.get_access_map() and code that writes
whitelist in access map buffer.
Note that we still need to configure base address of access map in
context image even for safety.
Jira NVGPU-3995
Bug 2686235
Change-Id: I111b46f96821a09929aff32fcba5bb2215c81b9a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2185469
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix misra errors in gr units
misra 14.3 rule - there shall be no dead code.
misra_c_2012_rule_14_3_violation: The condition
"graphics_preempt_mode != 0U" cannot be true.
misra_c_2012_rule_16_1_violation: The switch statement is not
well formed.
misra_c_2012_rule_10_8_violation: Cast from 32 bit width expression
"(regval >> 1U) & 1U" to a wider 64 bit type.
Jira NVGPU-3872
Change-Id: Ibb53d0756d464d2ae3279d1b841b3c91a16df9be
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2182562
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Advisory Rule 2.7 states that there should be no unused
parameters in functions.
This patch removes the unused 'post_event', 'fault_ch' and
'hww_global_esr' parameters from the following:
* gv11b_gr_intr_handle_l1_tag_exception()
* gv11b_gr_intr_handle_lrf_exception()
* gv11b_gr_intr_handle_cbu_exception()
* gv11b_gr_intr_handle_l1_data_exception()
* gv11b_gr_intr_handle_icache_exception()
These changes allowed the same parameters to be removed from the
the gr.intr.handle_tpc_sm_ecc_exception() interface.
Jira NVGPU-3178
Change-Id: I4d5dcbf2a5325e38782cdac67f9dd0b223fa1a18
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171220
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Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
This patch fixes above mentined errors in hal/gr/init/gr_init_gm20b.h,
hal/gr/init/gr_init_gm20b_fusa.c and hal/gr/init/gr_init_gp10b.h.
Jira NVGPU-3828
Change-Id: I915c837a05f62e7bfa543a08e488d118376b23b7
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158379
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Fix misra errors in gr init unit
Misra violation Rule 10.4: Essential type of the left hand operand
unsigned is not the same as that of the right operand signed.
Misra violation Rule 5.7: Identifier "class" is already used to
represent a type.
Misra violation Rule 10.8: Cast of composite expression of essential
type signed to essential type unsigned.
Jira NVGPU-3854
Change-Id: Ic4fe14207aea2ef6f16844ed45b22ffb19fd6bdb
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2173939
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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Fix MISRA 8.6 violation in gr config and interrupt units.
Rule 8.6 requires each identifier with external linkage to have
exactly one external definitions.
Move unused function definitions under CONFIG_NVGPU_HAL_NON_FUSA
checking.
Jira NVGPU-3854
Change-Id: I0661ea00ef9df700b0b928c8bf77e9a0fa4be29b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171386
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
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Added following gr init related gv11b hal for safety golden context
creation:
void gv11b_gr_init_restore_stats_counter_bundle_data(struct gk20a *g,
struct netlist_av_list *sw_bundle_init);
int gv11b_gr_init_load_sw_bundle_init(struct gk20a *g,
struct netlist_av_list *sw_bundle_init);
gv11b_gr_init_restore_stats_counter_bundle_data implements functionality
required to re-store stats bundle data, to avoid fe and mme mismatch.
gv11b_gr_init_load_sw_bundle_init implements functionality required for
disable stats idle clock counter to avoid mismatches
with two golden context saves.
JIRA NVGPU-3558
Change-Id: I73886770dac30934cbd3989b19ba87553286453d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2167211
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Reduce code complexity of following functions in gr.falcon unit
gm20b_gr_falcon_ctx_wait_ucode(complexity : 21 to 9)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create two sub functions from gm20b_gr_falcon_ctx_wait_ucode function
Sub functions to check the opcode failure and opcode success.
gm20b_gr_falcon_check_ctx_opcode_success(with complexity : 7)
gm20b_gr_falcon_check_ctx_opcode_failure(with complexity : 7)
and reduce gm20b_gr_falcon_ctx_wait_ucode complexity to 9
Jira NVGPU-3662
Change-Id: I445dab4e4149af2cc88d19a5b18b105077dece5f
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165217
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Reduce code complexity of following functions in gr.falcon unit
gv11b_gr_falcon_handle_fecs_ecc_error(complexity : 12 to 8)
Create sub functions by moving the control statement codes from
the function which has high complexity above 10.
Create one sub functions from gv11b_gr_falcon_handle_fecs_ecc_error function
One sub function to set the fecs_ecc_error status locally.
gr_falcon_set_fecs_ecc_error_status(with complexity : 5) and
reduce gv11b_gr_falcon_handle_fecs_ecc_error complexity to 8
Jira NVGPU-3662
Change-Id: I9ce3cd7b6b4fb453445457ba5f19faf7086b5fc6
Signed-off-by: vinodg <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2165190
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Moved non-secure gr falcon boot related code to non-functional safety file.
Also added HAL initialization related to these functions under
CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT flag.
JIRA NVGPU-3741
Change-Id: I72fb92c04dc6e76c338e9a0e0cd86b12109ce284
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158936
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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This patch adds the support to handle and report graphics related
exceptions to 3LSS. Specifically, it adds the following exceptions:
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_CROP
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_ZROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE
JIRA NVGPU-3457
Change-Id: Ib24b67ed33ae139317ec85bba3fbb80ba51fd384
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158609
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The following DEVCTLs not needed in safety build
Compiled out below DEVCTLs for safety build
* NVGPU_GPU_DEVCTL_SET_THERM_ALERT_LIMIT
* NVGPU_GPU_DEVCTL_GET_TPC_EXCEPTION_EN_STATUS
* NVGPU_GPU_DEVCTL_GET_CPU_TIME_CORRELATION_INFO
Also added config flag CONFIG_NVGPU_IOCTL_NON_FUSA
JIRA NVGPU-3768
Change-Id: Ia233d0aac8201268524581f588d97390a913ab9c
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159398
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Reduce code complexity of following functions in gr.ecc unit
gp10b_ecc_init(complexity : 17)
gp10b_ecc_detect_enabled_units(complexity : 15)
gv11b_ecc_init(complexity : 23)
gv11b_ecc_detect_enabled_units(complexity : 30)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create four sub functions from gp10b_ecc_init function for
sub units init.
gp10b_ecc_init_lts(complexity : 2)
gp10b_ecc_init_tpc(complexity : 2)
gp10b_ecc_init_tpc_tex(complexity : 8)
gp10b_ecc_init_tpc_sm(complexity : 5)
and reduce gp10b_ecc_init complexity to 3
Create four sub functions from gp10b_ecc_detect_enabled_units function
gp10b_ecc_enable_ltc(with complexity : 4)
gp10b_ecc_enable_tex(with complexity : 4)
gp10b_ecc_enable_smshm(with complexity : 4)
gp10b_ecc_enable_smlrf(with complexity : 4)
and reduce gp10b_ecc_detect_enabled_units complexity to 3
Create four sub functions from gv11b_ecc_init function for
sub units init.
gv11b_ecc_init_tpc(complexity : 10)
gv11b_ecc_init_gpc(complexity : 6)
gv11b_ecc_init_fb(complexity : 6)
gv11b_ecc_init_other_units(complexity : 6)
and reduce gv11b_ecc_init complexity to 5
Create six sub functions from gv11b_ecc_detect_enabled_units function
gv11b_ecc_enable_smlrf(with complexity : 4)
gv11b_ecc_enable_sml1data(with complexity : 4)
gv11b_ecc_enable_sml1tag(with complexity : 4)
gv11b_ecc_enable_smicache(with complexity : 6)
gv11b_ecc_enable_ltc(with complexity : 4)
gv11b_ecc_enable_smcbu(with complexity : 4)
and reduce gv11b_ecc_detect_enabled_units complexity to 3
Jira NVGPU-3662
Change-Id: Id10be4f9a500c300f66756ebae41bfff3b734aea
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159050
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
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MISRA Advisory Rule 12.3 states that the comma operator should
not be used.
This change fixes several violations of this rule in gr falcon
code.
The remaining violations of this advisory rule will be covered
in a rule-specific deviation record.
JIRA NVGPU-3798
Change-Id: Iea579356ac1da03c6730f738f5316b57e26afa7c
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155616
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Following common and corresponding hal functions are non-safe. They are
either required for intr handling or for debug. Compile them out for
igpu safety release. Moved corresponding HALs to falcon_gk20a.c.
nvgpu_falcon_copy_from_emem
nvgpu_falcon_copy_to_emem
nvgpu_falcon_clear_halt_intr_status
nvgpu_falcon_set_irq
nvgpu_falcon_copy_from_dmem
nvgpu_falcon_copy_from_imem
nvgpu_falcon_print_dmem
nvgpu_falcon_print_imem
nvgpu_falcon_get_ctls
nvgpu_falcon_dump_stats can be used in the safety debug build.
JIRA NVGPU-898
JIRA NVGPU-2214
Change-Id: Icb7f904b088aa74b976f75a6a0ecdb783486bab3
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152978
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Reduce code complexity of following functions in gr.config unit
gv100_gr_config_init_sm_id_table(complexity : 13)
gr_gv100_scg_estimate_perf(complexity : 23)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create two sub functions from gv100_gr_config_init_sm_id_table function
gr_gv100_scg_estimate_perf_for_all_gpc_tpc(complexity : 5)
gv100_gr_config_set_sminfo(complexity : 3)
and reduce gv100_gr_config_init_sm_id_table complexity to 8
Create four sub functions from
gv100_gr_config_init_sm_id_table function
gr_gv100_find_max_gpc(with complexity : 2)
gr_gv100_remove_logical_tpc(with complexity : 4)
gr_gv100_calc_valid_pes(with complexity : 6)
gr_gv100_scg_calculate_perf(with complexity : 7)
and reduce gr_gv100_scg_estimate_perf complexity to 10
Jira NVGPU-3661
Change-Id: Iaaef1a98f2c6c55cd7b0a1a57d1c74eb09d43869
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156744
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Reduce code complexity of following functions in gr.intr unit
gm20b_gr_intr_handle_exceptions(complexity : 13)
tu104_gr_intr_log_mme_exception(complexity : 13)
gv11b_gr_intr_handle_icache_exception(complexity : 17)
gv11b_gr_intr_handle_gpc_gpccs_exception(complexity : 13)
gv11b_gr_intr_handle_l1_tag_exception(complexity : 15)
gv11b_gr_intr_handle_gpc_gpcmmu_exception(complexity : 15)
Create sub functions by moving the control statement codes
from the function which has high complexity above 10.
Create following 8 sub functions for handling each exception from
gm20b_gr_intr_handle_exceptions function
gr_gm20b_intr_check_gr_fe_exception(complexity : 2)
gr_gm20b_intr_check_gr_memfmt_exception(complexity : 2)
gr_gm20b_intr_check_gr_pd_exception(complexity : 2)
gr_gm20b_intr_check_gr_scc_exception(complexity : 2)
gr_gm20b_intr_check_gr_ds_exception(complexity : 2)
gr_gm20b_intr_check_gr_ssync_exception(complexity : 4)
gr_gm20b_intr_check_gr_mme_exception(complexity : 3)
gr_gm20b_intr_check_gr_sked_exception(complexity : 2)
and reduce gm20b_gr_intr_handle_exceptions complexity to 3.
Create following 2 sub functions from tu104_gr_intr_log_mme_exception
function
gr_tu104_check_dma_exception(complexity : 6)
gr_tu104_check_ram_access_exception(complexity : 3)
and reduce tu104_gr_intr_log_mme_exception complexity to 6
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_icache_exception function
gv11b_gr_intr_report_icache_uncorrected_err(complexity : 5)
gv11b_gr_intr_report_icache_corrected_err(complexity : 5)
and reduce gv11b_gr_intr_handle_icache_exception complexity to 9
Create following 2 sub functions for corrected and uncorrected error
reporting from gv11b_gr_intr_handle_l1_tag_exception function
gv11b_gr_intr_report_l1_tag_uncorrected_err(complexity : 4)
gv11b_gr_intr_report_l1_tag_corrected_err(complexity : 4)
and reduce gv11b_gr_intr_handle_l1_tag_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpccs_exception function
gv11b_gr_intr_report_gpccs_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpccs_exception complexity to 9
Create following 1 sub function for error reporting from
gv11b_gr_intr_handle_gpc_gpcmmu_exception function
gv11b_gr_intr_report_gpcmmu_ecc_err(complexity : 5)
and reduce gv11b_gr_intr_handle_gpc_gpcmmu_exception complexity to 9
Jira NVGPU-3661
Change-Id: I855b9ba055f3a8578c7b62cd59e249017ec31936
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2155852
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Moved debugger/cilp functions from gr ctxsw prog hal files for various
platforms to corresponding fusa files as currently they are enabled in
the safety build. Updated the arch yaml to reflect the non-fusa and
fusa units for gr ctxsw_prog.
JIRA NVGPU-3690
Change-Id: I188d3de223aa65816b5f511b776eb8278e221219
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2156877
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
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MISRA Advisory Rule 10.5 states that the value of an expression should
not be cast to an inappropriate essential type.
This change removes five violations of this rule that involve casting
boolean results to unsigned values:
* pass 1/0 (instead of true/false) to nvgpu_atomic operations
* fix skip_mask handling in gm20b_gr_init_pd_skip_table_gpc()
* fix l3_alloc flags check in nvgpu_gmmu_map_locked()
This change also eliminates several MISRA Advisory Rule 4.6 violations.
JIRA NVGPU-3798
Change-Id: I707da8a812bfb32eaeb2200463885c0961b197b3
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153070
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.
Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.
Jira NVGPU-3690
Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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Shortcomings of ALIGN macros:
- ALIGN_MASK down aligns when there is an wrapping/overflow instead of
throwing an error. This can affect the size assumptions.
- Alignment a's check will be bypassed when ALIGN_MASK is directly
used.
Fix these issues by 1) adding compile time error for non-unsigned type
arguments 2) using unsigned type safe ops for addition and subtraction.
Also, change users of ALIGN to pass unsigned types only.
JIRA NVGPU-3515
Jira NVGPU-3411
Change-Id: I5b94a262e09aad473c420af750ead6b0f9d36a9b
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128382
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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Remove below hals since the corresponding functions are same on all
platforms and they are h/w independent
g->ops.gr.enable_ctxsw()
g->ops.gr.disable_ctxsw()
g->ops.gr.reset()
Call the functions directly at all places
Remove CONFIG_NVGPU_DEBUGGER from places where these functions are
called since they are not debugger dependent
This also helps to disable CONFIG_NVGPU_DEBUGGER and to keep recovery
sequence intact
Jira NVGPU-3506
Change-Id: Id2b208ca23dc4667e78edcd8ad242a8558e0ff64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2137255
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GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Fix MISRA 13.2 errors in hal.gr.intr unit.
misra_c_2012_rule_13_2_voilation: In hi32_lo32_to_u64, two function
calls in the arguments for which the order of evaluation is undefined.
Jira NVGPU-3621
Change-Id: I2c0d9a4492068f13edfb6ac6309f8679d1fbcee4
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2134597
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